EN 182
3139 785 31532
9.
Circuit- and IC Description
PIN DESCRIPTION AND CONFIGURATION
PACKAGE PIN #
PIN SYMBOL
FUNCTION
1
V
CC
Power supply input.
2
PWRGD
Open collector output goes low when V
FB
is out of regulation. User
must externally limit current into this pin to less than 20 mA.
3
PGDELAY
External capacitor programs PWRGD low–to–high transition delay.
4
COMP
Error amp output. PWM comparator reference input. A capacitor to
LGND provides error amp compensation and Soft Start. Pulling pin
< 0.475 V locks gate outputs to a zero percent duty cycle state.
5
GATE(H)
High–side switch FET driver pin. Capable of delivering peak currents
of 1.5 A.
6
GATE(L)
Low–side synchronous FET driver pin. Capable of delivering peak
currents of 1.5 A.
7
V
FB
Error amplifier and PWM comparator input.
8
GND
Power supply return.
IC7603 - ADV7322KST - Multi-Format 11-Bit HDTV Video Encoder
BLOCK
DIAGRAM
CLKIN_A
P_HSYNC
P_VSYNC
P_BLANK
S_HSYNC
S_VSYNC
S_BLANK
CLKIN_B
HD PIXEL
INPUT
SD PIXEL
INPUT
LUMA
AND
CHROMA
FILTERS
Y
CB
CR
TEST
PATTERN
DNR
GAMMA
SYNC
INSERTION
PS 8
u
HDTV 2
u
RGB
MATRIX
SD 16
u
2
u
OVER-
SAMPLING
DAC
DAC
DAC
DAC
DAC
DAC
F
SC
MODU-
LATION
CGMS
WSS
COLOR
CONTROL
DE-
INTER-
LEAVE
Y
CB
CR
DE-
INTER-
LEAVE
TEST
PATTERN
Y COLOR
CR COLOR
CB COLOR
TIMING
GENERATOR
TIMING
GENERATOR
CLOCK
CONTROL
AND PLL
4:2:2
TO
4:4:4
SHARPNESS
AND
ADAPTIVE
FILTER
CONTROL
05067-002
UV SSAF
V
U
Figure 9-16
