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NXP Semiconductors LPC5410x User Manual Download Page 398

UM10850

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© NXP B.V. 2016. All rights reserved.

User manual

Rev. 2.4 — 13 September 2016 

399 of 464

NXP Semiconductors

UM10850

Chapter 27: LPC5410x Mailbox

27.6 Register description

 

[1]

Reading an writing have specific side effects see detailed register description.

27.6.1 M0+ interrupt register

The IRQ0 register allows other CPUs to send interrupt requests to the Cortex-M0+ CPU. 
This is intended to allow communication between CPUs. For example, one CPU could be 
handling certain peripherals and signalling another CPU when data is available Each bit 
can represent a different situation. The use of this feature is entirely up to the user.

 

27.6.2 Cortex M0+ interrupt set register 

The IRQ0SET register is used to set bits in the IRQ0 register.

 

27.6.3 M0+ interrupt clear register 

The IRQ0SET register is used to clear bits in the IRQ0 register.

 

Table 439. Register overview: Mailbox (base address 0x1C02 C000)

Name

Access

Address 
offset

Description

Reset value

Reference

IRQ0

R/W

0x000

Interrupt request register for the Cortex-M0+ CPU.

0

Table 440

IRQ0SET

WO

0x004

Set bits in IRQ0

-

Table 441

IRQ0CLR

WO

0x008

Clear bits in IRQ0

-

Table 442

IRQ1

R/W

0x010

Interrupt request register for the Cortex M4 CPU.

0

Table 443

IRQ1SET

WO

0x014

Set bits in IRQ1

-

Table 444

IRQ1CLR

WO

0x018

Clear bits in IRQ1

-

Table 445

MUTEX

R/W 

0x0F8

Mutual exclusion register

[1]

0x1

Table 446

Table 440. M0+ interrupt register (IRQ0, address 0x1C02 C000) bit description

Bit

Symbol

Description

Reset value

31:0

INTREQ

If any bit is set, an interrupt request is sent to the Cortex-M0+ 
interrupt controller.

0

Table 441. M0+ interrupt set register (IRQ0SET, address 0x1C02 C004) bit description

Bit

Symbol

Description

Reset Value

31:0

INTREQ
SET

Writing 1 sets the corresponding bit in the IRQ0 register.

-

Table 442. M0+ interrupt clear register (IRQ0CLR, address 0x1C02 C008) bit description

Bit

Symbol

Description

Reset Value

31:0

INTREQ
CLR

Writing 1 clears the corresponding bit in the IRQ0 register.

-

Summary of Contents for LPC5410x

Page 1: ...M10850 LPC5410x User manual Rev 2 4 13 September 2016 User manual Document information Info Content Keywords LPC5410x ARM Cortex M4 ARM Cortex M0 microcontroller sensor hub Abstract LPC5410x User Manual ...

Page 2: ...2 to Section 30 4 2 Chip_POWER_SetVoltage Deleted Param0 mode and Low power mode was section 30 4 2 1 Added Section 30 4 3 Chip_POWER_EnterPowerMode Updated Section 30 5 Functional description 2 2 20160331 Removed Section 4 5 51 Device ID1 register values and moved Table 89 Device ID1 register values to section Section 4 5 50 Device ID1 register Removed IrDA mode from Section 21 5 General descript...

Page 3: ...esired frequency in MHz Removed text from Section 5 2 General description list 3 or for monitoring analog inputs comparators and internal voltage reference and temperature sensor via one of the comparators Removed comparator from Section 13 5 General description This provides an extremely powerful control tool particularly when the SCT inputs and outputs are connected to other on chip resources AD...

Page 4: ...he USART peripheral Fixed the reset value of MSTTIME Master timing configuration was 0x77 now 0x56 See Table 340 Register overview I2C0 1 2 register base addresses 0x4009 4000 I2C0 0x4009 8000 I2C1 0x4009 C000 I2C2 Added the Flash Management Registers FMSSTART and FMSSTOPUpdated to Chapter 28 LPC5410x Flash signature generator Typographic errors have been corrected and minor pieces of information ...

Page 5: ...v 2 4 13 September 2016 5 of 464 Contact information For more information please visit http www nxp com For sales office addresses please send an email to salesaddresses nxp com NXP Semiconductors UM10850 LPC5410x User manual 1 0 20141104 Initial release of the LPC5410x User Manual Revision history continued Rev Date Description ...

Page 6: ...the Cortex M4 with the inclusion of the 32 bit Floating Point Unit The ARM Cortex M0 coprocessor available on some devices is an energy efficient and easy to use 32 bit core which is code and tool compatible with the Cortex M4 core The Cortex M0 coprocessor offers up to 100 MHz performance with a simple instruction set and reduced code size Refer to LPC5410x data sheets for complete details on spe...

Page 7: ... up to 1Mbit s and with multiple address recognition and monitor mode Each I2C bus interface also supports High Speed Mode as a slave The slave function is able to wake up the device from Deep sleep and Power down modes Digital peripherals DMA controller with 22 channels and 20 programmable triggers able to access all memories and DMA capable peripherals Up to 50 General Purpose I O GPIO pins Most...

Page 8: ...RC oscillator factory trimmed for accuracy that can optionally be used as a system clock External clock input for up 24 MHz Internal low power watchdog oscillator WDOSC with a nominal frequency of 500 kHz 32 kHz low power RTC oscillator System PLL allows CPU operation up to the maximum CPU rate without the need for a high frequency external clock May be run from the internal RC oscillator the exte...

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Page 10: ...tween the CPU and the DMA controller and also for peripherals on the asynchronous bridge to have a fixed clock that does not track the system clock 1 5 ARM Cortex M4 processor The Cortex M4 is a general purpose 32 bit microprocessor which offers high performance and very low power consumption The Cortex M4 offers a Thumb 2 instruction set low interrupt latency interruptible continuable multiple lo...

Page 11: ...N block to save power See Section 4 5 22 AHB Clock Control register 0 and Section 4 5 38 Power Configuration register 2 1 1 1 SRAM2 An additional on chip static RAM memory SRAM2 is available that is not contiguous to SRAM0 and SRAM1 This can be used for example as the location for the program stack or any other use SRAM2 can be disabled or enabled in the SYSCON block to save power See Section 4 5 ...

Page 12: ...a at some point even when all such data is read from or sent to a peripheral by DMA So minimizing stalls is likely to involve putting data to from different peripherals in RAM on each port Alternatively sequences of data from the same peripheral could be alternated between RAM on each port this could be helpful if DMA fills or empties a RAM buffer then signals the CPU before proceeding on to a sec...

Page 13: ... 5HS QW 7LPHU UHVHUYHG QSXW 0X UHVHUYHG 57 DWFKGRJ 7LPHU UHVHUYHG ODVK FRQWUROOHU 0LFUR7LFN 7LPHU 2 21 3 17 17 17 7LPHU 7LPHU 7LPHU 6 VFRQ 3 SHULSKHUDOV DFWLYH LQWHUUXSW YHFWRUV UHVHUYHG SULYDWH SHULSKHUDO EXV 3 SHULSKHUDO JURXS 3 SHULSKHUDO JURXS UHVHUYHG UHVHUYHG UHVHUYHG UHVHUYHG UHVHUYHG RRW DQG ULYHU 520 3 SHULSKHUDO ELW EDQG DGGUHVVLQJ 65 0 XS WR N 65 0 XS WR N N IODVK PHPRU 0HPRU VSDFH 0DLO...

Page 14: ... allowing peripherals that are on different slave ports of the matrix to be accessed simultaneously by different bus masters Figure 1 shows details of the potential matrix connections 2 1 4 Memory Protection Unit MPU The Cortex M4 processor has a memory protection unit MPU that provides fine grain memory control enabling applications to implement security privilege levels separating code data and ...

Page 15: ...king Vector table offset register VTOR Support for NMI from any interrupt see Section 4 5 3 3 3 General description The tight coupling to the NVIC to the CPU allows for low interrupt latency and efficient processing of late arriving interrupts 3 3 1 Interrupt sources Table 2 lists the interrupt sources for each peripheral function Each peripheral device may have one or more interrupt lines to the ...

Page 16: ...upts 16 SCT0 State configurable timer interrupt EVFLAG SCT event 17 UART0 USART0 interrupt See Table 310 18 UART1 USART1 interrupt Same as USART0 19 UART2 USART2 interrupt Same as USART0 20 UART3 USART3 interrupt Same as USART0 21 I2C0 I2C0 interrupt See Table 348 22 I2C1 I2C1 interrupt Same as I2C0 23 I2C2 I2C2 interrupt Same as I2C0 24 SPI0 SPI0 interrupt See Table 325 25 SPI1 SPI1 interrupt Sam...

Page 17: ... 11 IABR0 1 RO 0x300 Interrupt Active Bit Register 0 This register allows reading the current interrupt active state for specific peripheral functions 0 Table 12 IABR1 1 RO 0x304 Interrupt Active Bit Register 1 See IABR0 description 0 Table 13 IPR0 R W 0x400 Interrupt Priority Register 0 This register contains the 3 bit priority fields for interrupts 0 to 3 0 Table 14 IPR1 R W 0x404 Interrupt Prio...

Page 18: ... Pin interrupt pattern match engine slice 1 interrupt 7 ISE_PINT2 1 Pin interrupt pattern match engine slice 2 interrupt 8 ISE_PINT3 1 Pin interrupt pattern match engine slice 3 interrupt 9 ISE_UTICK 1 Micro Tick Timer interrupt enable 10 ISE_MRT 1 Multi Rate Timer interrupt enable 11 ISE_CT32B0 1 Standard counter timer CT32B0 interrupt enable 12 ISE_CT32B1 1 Standard counter timer CT32B1 interrup...

Page 19: ... register allows setting the pending state of the first 32 peripheral interrupts or for reading the pending state of those interrupts The remaining interrupts can have their pending state set via the ISPR1 register Section 3 4 6 Clearing the pending state of interrupts is done through the ICPR0 and ICPR1 registers Section 3 4 7 and Table 5 Interrupt Set Enable Register 1 register Bit Name Value Fu...

Page 20: ...ISPR1 registers Section 3 4 5 and Section 3 4 6 Table 8 Interrupt Set Pending Register 0 register Bit Name Function 31 0 ISP_ Peripheral interrupt pending set Bit numbers match ISER0 registers Table 4 Unused bits are reserved Write writing 0 has no effect writing 1 changes the interrupt state to pending Read 0 indicates that the interrupt is not pending 1 indicates that the interrupt is pending Ta...

Page 21: ...2 priorities where 0 is the highest priority 3 4 12 Interrupt Priority Register 1 The IPR1 register controls the priority of the second group of 4 peripheral interrupts Each interrupt can have one of 32 priorities where 0 is the highest priority Table 12 Interrupt Active Bit Register 0 Bit Name Function 31 0 IAB_ Peripheral interrupt active Bit numbers match ISER0 registers Table 4 Unused bits are...

Page 22: ...ty 31 0x1F lowest priority 28 24 Unused 31 29 IP_PINT2 Pin interrupt pattern match engine slice 2 priority 0 highest priority 31 0x1F lowest priority Table 15 Interrupt Priority Register 1 continued Bit Name Function Table 16 Interrupt Priority Register 2 Bit Name Function 4 0 Unused 7 5 IP_PINT3 Pin interrupt pattern match engine slice 3 priority 0 highest priority 31 0x1F lowest priority 12 8 Un...

Page 23: ...rity 12 8 Unused 15 13 IP_USART0 USART 0 interrupt priority 0 highest priority 31 0x1F lowest priority 20 16 Unused 23 21 IP_USART1 USART 1 interrupt priority 0 highest priority 31 0x1F lowest priority 28 24 Unused 31 29 IP_USART2 USART 2 interrupt priority 0 highest priority 31 0x1F lowest priority Table 19 Interrupt Priority Register 5 Bit Name Function 4 0 Unused 7 5 IP_USART3 USART 3 interrupt...

Page 24: ...t Name Function 4 0 Unused 7 5 IP_ADC0THOV ADC 0 threshold and error interrupt priority 0 highest priority 31 0x1F lowest priority 12 8 Unused 15 13 IP_RTC Real Time clock RTC interrupt priority 0 highest priority 31 0x1F lowest priority 20 16 Unused 23 21 Reserved 28 24 Unused 31 29 IP_MAILBOX Mailbox interrupt priority 0 highest priority 31 0x1F lowest priority present on LPC54102 devices Table ...

Page 25: ...er is not available for the Cortex M0 By default only privileged software can write to the STIR register Unprivileged software can be given this ability if privileged software sets the USERSETMPEND bit in the CCR register The interrupt number to be programmed in this register is listed in Table 2 Table 24 Interrupt Priority Register 10 Bit Name Function 4 0 Unused 7 5 IP_RIT Repetitive interrupt T...

Page 26: ... function are selected in the input mux block See Table 131 4 2 1 Set up the PLL The PLL creates a stable output clock at a higher frequency than the input clock If a main clock is needed with a frequency higher than the 12 MHz IRC clock use the PLL to boost the input frequency The PLL can be set up by calling an API supplied by NXP Semiconductors Also see Section 4 6 4 PLL functional description ...

Page 27: ... watchdog oscillator which varies over a wide range depending on process and temperature The clock frequency to be measured and the reference clock are selected in the input mux block See Section 8 6 4 Frequency measure function reference clock select register and Section 8 6 5 Frequency measure function target clock select register Details on the accuracy and measurement process are described in ...

Page 28: ...ed to use a number of clock inputs and produce an output clock in the range of 1 2 MHz up to the maximum chip frequency and can be used to run most on chip functions The output of the PLL can be monitored through the CLKOUT pin Fig 3 Clock generation 6 VWHP 3 VHWWLQJV V VFON SOOBFON 6 VWHP FORFN GLYLGHU 9 0DLQ FORFN VHOHFW 0 1 6 NBFON 38 ORFN LYLGHU 6 VWHP 3 3 1 0DLQ FORFN VHOHFW 0 1 6 ZGWBFON LUF...

Page 29: ...Table 33 SYSRSTSTAT R W 0x040 System reset status register Note 2 Table 34 PRESETCTRL0 R W 0x044 Peripheral reset control 0 0x0 Table 35 PRESETCTRL1 R W 0x048 Peripheral reset control 1 0x0 Table 36 PRESETCTRLSET0 WO 0x04C Set bits in PRESETCTRL0 Table 37 PRESETCTRLSET1 WO 0x050 Set bits in PRESETCTRL1 Table 38 PRESETCTRLCLR0 WO 0x054 Clear bits in PRESETCTRL0 Table 39 PRESETCTRLCLR1 WO 0x058 Clea...

Page 30: ...ster 0xD80500 Table 72 PDRUNCFGSET WO 0x214 Set bits in PDRUNCFG Table 73 PDRUNCFGCLR WO 0x218 Clear bits in PDRUNCFG Table 74 STARTER0 R W 0x240 Start logic 0 wake up enable register 0x0 Table 75 STARTER1 R W 0x244 Start logic 1 wake up enable register 0x0 Table 76 STARTERSET0 WO 0x248 Set bits in STARTER0 Table 77 STARTERSET1 WO 0x24C Set bits in STARTER1 Table 78 STARTERCLR0 WO 0x250 Clear bits...

Page 31: ...SYNCAPBCLKCTRLCLR WO 0x018 Clear bits in ASYNCAPBCLKCTRL Table 95 ASYNCAPBCLKSELA R W 0x020 Async APB clock source select A 0x0 Table 96 ASYNCAPBCLKSELB R W 0x024 Async APB clock source select B 0x0 Table 97 ASYNCCLKDIV R W 0x028 Async APB clock divider 0x1 Table 98 FRGCTRL R W 0x030 USART fractional rate generator control 0xFF Table 99 Table 28 Register overview Asynchronous system configuration ...

Page 32: ...pherals Table 31 System tick timer calibration register SYSTCKCAL address 0x4000 0014 bit description Bit Symbol Description Reset value 23 0 CAL System tick timer calibration value 0 24 SKEW Initial value for the Systick timer 25 NOREF Initial value for the Systick timer 31 26 Reserved Table 32 NMI source selection register NMISRC address 0x4000 001C bit description Bit Symbol Description Reset v...

Page 33: ...ars this reset 1 EXTRST Status of the external RESET pin External reset status 0 No reset event detected 1 Reset detected Writing a one clears this reset 2 WDT Status of the Watchdog reset 0 No WDT reset detected 1 WDT reset detected Writing a one clears this reset 3 BOD Status of the Brown out detect reset 0 No BOD reset detected 1 BOD reset detected Writing a one clears this reset 4 SYSRST Statu...

Page 34: ...or reset control 0 Clear reset to this function 1 Assert reset to this function 0 22 WWDT_RST Watchdog timer reset control 0 Clear reset to this function 1 Assert reset to this function 0 26 23 Reserved Read value is undefined only zero should be written 0 27 ADC0_RST ADC0 reset control 0 Clear reset to this function 1 Assert reset to this function 0 31 28 Reserved Read value is undefined only zer...

Page 35: ...eset control 0 Clear reset to this function 1 Assert reset to this function 0 31 28 Reserved Read value is undefined only zero should be written Table 36 Peripheral reset control register 1 PRESETCTRL1 address 0x4000 0048 bit description Bit Symbol Description Reset value Table 37 Peripheral reset control set register 0 PRESETCTRLSET0 address 0x4000 004C bit description Bit Symbol Description Rese...

Page 36: ...other than a power on reset occurs Each bit represents the reset state of one GPIO pin This register is a read only register Table 40 Peripheral reset control clear register 1 PRESETCTRLCLR1 address 0x4000 0058 bit description Bit Symbol Description Reset value 31 0 RST_CLR1 Writing ones to this register clears the corresponding bit or bits in the PRESETCTRL1 register if they are implemented Bits ...

Page 37: ...ain clock source select register A see Table 45 which selects one of the three internal oscillators IRC system oscillator or watchdog oscillator Remark Note that this selection is internally synchronized the clock being switched from and the clock being switched to must both be running and have occurred in specific states before the selection actually changes 4 5 18 ADC clock source select registe...

Page 38: ...ck being switched to must both be running and have occurred in specific states before the selection actually changes 4 5 20 CLKOUT clock source select register B This register selects the clock source visible on the CLKOUT pin The internal oscillators are pre selected in the CLKOUTSELA register see Table 48 Remark Note that this selection is internally synchronized the clock being switched from an...

Page 39: ...ing switched to must both be running and have occurred in specific states before the selection actually changes Table 49 CLKOUT clock source select register CLKOUTSELB address 0x4000 0098 bit description Bit Symbol Value Description Reset value 1 0 SEL CLKOUT clock source 0 0x0 CLKOUTSELA Clock source selected in the CLKOUTSELA register 0x1 reserved 0x2 reserved 0x3 RTC 32 kHz clock 31 2 Reserved ...

Page 40: ...ming not for flash read 1 8 FMC Enables the clock for the Flash accelerator 0 Disable 1 Enable This clock is needed if the flash is being read 1 10 9 Reserved Read value is undefined only zero should be written 0 11 INPUTMUX Enables the clock for the input muxes 0 Disable 1 Enable 0 12 Reserved Read value is undefined only zero should be written 0 13 IOCON Enables the clock for the IOCON block 0 D...

Page 41: ... Disable 1 Enable 0 2 SCT0 Enables the clock for SCT0 0 Disable 1 Enable 0 8 3 Reserved Read value is undefined only zero should be written 9 FIFO Enables the clock for system FIFOs 0 Disable 1 Enable 0 10 UTICK Enables the clock for the Micro tick Timer 0 Disable 1 Enable 0 21 11 Reserved Read value is undefined only zero should be written 0 22 CT32B2 Enables the clock for CT32B 2 0 Disable 1 Ena...

Page 42: ...0D0 bit description Bit Symbol Description Reset value 31 0 CLK_CLR0 Writing ones to this register clears the corresponding bit or bits in the AHBCLKCTRL0 register if they are implemented Bits that do not correspond to defined bits in AHBCLKCTRL0 are reserved and only zeroes should be written to them Table 56 Clock control clear register 1 AHBCLKCTRLCLR1 address 0x4000 00D4 bit description Bit Sym...

Page 43: ...gister for more on this function Table 59 ADC clock source divider ADCCLKDIV address 0x4000 0108 bit description Bit Symbol Description Reset value 7 0 DIV ADC clock divider value 0 Disable ADC clock 1 Divide by 1 to 255 Divide by 255 0 31 8 Reserved Read value is undefined only zero should be written Table 60 CLKOUT clock divider register CLKOUTDIV address 0x4000 010C bit description Bit Symbol D...

Page 44: ...ruction fetches 0x2 00 Instruction fetches from flash are not buffered Every fetch request from the CPU results in a read of the flash memory This setting may use significantly more power than when buffering is enabled 01 One buffer is used for all instruction fetches 10 All buffers may be used for instruction fetches 11 Reserved setting do not use 3 2 DATACFG Data read configuration This field de...

Page 45: ...o 72 MHz 0x4 5 system clocks flash access time for system clock rates up to 84 MHz 0x5 6 system clocks flash access time for system clock rates up to 100 MHz others Value 1 system clocks flash access time 31 16 Reserved Table 62 Flash configuration register FLASHCFG main syscon address 0x4000 0124 bit description Bit Symbol Value Description Reset value Table 63 FIFO control register FIFOCTRL addr...

Page 46: ...ster enables the 32 kHz output of the RTC oscillator This clock can be used to create the main clock when the PLL input or output is selected as the clock source to the main clock Table 64 IRC control register IRCCTRL address 0x4000 0184 bit description Bit Symbol Description Reset value 7 0 TRIM Trim value Initially 0x80 Boot code will alter to a device specific value Users should not write to th...

Page 47: ...DIV2 Bypass feedback clock divide by 2 0 0 Divide by 2 The CCO feedback clock is divided by 2 in addition to the programmed M divide 1 Bypass The CCO feedback clock is divided only by the programmed M divide 17 UPLIMOFF Disable upper frequency limiter For spread spectrum mode SEL_EXT 0 BANDSEL 0 and UPLIMOFF 1 0 0 Normal mode 1 Upper frequency limiter disabled 18 BANDSEL PLL filter control Set thi...

Page 48: ...e do not change the NDEC value Changing the NDEC value changes the FCCO frequency and can cause the system to fail The valid range for N is 1 to 2 8 This value is encoded into a 10 bit NDEC value The relationship can be expressed through the following pseudo code N_max 0x00000100 x 0x00000080 switch N case 0 x 0xFFFFFFFF case 1 x 0x00000302 case 2 x 0x00000202 default for i N i N_max i x x x 2 x 3...

Page 49: ...ch can decrease electromagnetic interference EMI The Spread Spectrum Clock Generator can be used in several ways It can encode M divider values between 1 and 255 to produce the MDEC value used directly by the PLL saving the need for executing encoding algorithm code or hard coding predetermined values into an application It can provide a fractional rate feature to the PLL It can be set up to autom...

Page 50: ...he values for SELP SELI and SELR depend on the value for M as expressed by the following pseudo code if M 60 then SELP M 1 1 else SELP 31 if M 16384 then SELI 1 else if M 8192 then SELI 2 else if M 2048 then SELI 4 else if M 501 then SELI 8 Table 70 System PLL spread spectrum control register 0 SYSPLLSSCTRL0 address 0x4000 01C0 bit description Bit Symbol Value Description Reset value 16 0 MDEC Dec...

Page 51: ...nges the FCCO frequency and can cause the system to fail 4 5 37 5 2 System PLL spread spectrum control register 1 Table 71 System PLL spread spectrum control register 1 SYSPLLSSCTRL1 address 0x4000 01C4 bit description Bit Symbol Value Description Reset value 18 0 MD M divider value with fraction MD 18 11 integer portion of the feedback divider value MD 10 0 fractional portion of the feedback divi...

Page 52: ...put of the PLL giving a flat frequency spectrum 0b00 no compensation 0b10 recommended setting 0b11 max compensation 0 28 PD Power down 1 0 Enabled Spread spectrum controller is enabled 1 Disabled Spread spectrum controller is disabled 29 DITHER Select modulation frequency 0 0 Fixed Fixed modulation frequency 1 Dither Randomly dither between two modulation frequencies 31 30 Reserved Read value is u...

Page 53: ...iption Bit Symbol Description Reset value 2 0 3 PDEN_IRC_OSC IRC oscillator output 0 Powered 1 Powered down 0 4 PDEN_IRC IRC oscillator 0 Powered 1 Powered down 0 5 PDEN_FLASH Flash memory 0 Powered 1 Powered down 0 6 Reserved 7 PDEN_BOD_RST Brown out Detect reset 0 Powered 1 Powered down 0 8 PDEN_BOD_INTR Brown out Detect interrupt 0 Powered 1 Powered down 1 9 Reserved 10 PDEN_ADC0 ADC0 0 Powered...

Page 54: ...NCFGSET address 0x4000 0214 bit description Bit Symbol Description Reset value 31 0 PD_SET Writing ones to this register sets the corresponding bit or bits in the PDRUNCFG register if they are implemented Bits that do not correspond to defined bits in PDRUNCFG are reserved and only zeroes should be written to them Table 74 Power configuration clear register PDRUNCFGCLR address 0x4000 0218 bit desc...

Page 55: ...ned only zero should be written 3 DMA DMA wake up 0 Wake up disabled 1 Wake up enabled Typically used in sleep mode only since the peripheral clock must be running for it to function 0 4 GINT0 Group interrupt 0 wake up 0 Wake up disabled 1 Wake up enabled 0 5 PINT0 GPIO pin interrupt 0 wake up 0 Wake up disabled 1 Wake up enabled Not for pattern match 0 6 PINT1 GPIO pin interrupt 1 wake up 0 Wake ...

Page 56: ...l interrupt 0 19 USART2 USART2 interrupt wake up 0 Wake up disabled 1 Wake up enabled Peripheral interrupt 0 20 USART3 USART2 interrupt wake up 0 Wake up disabled 1 Wake up enabled Peripheral interrupt 0 21 I2C0 I2C0 interrupt wake up 0 Wake up disabled 1 Wake up enabled Peripheral interrupt 0 22 I2C1 I2C1 interrupt wake up 0 Wake up disabled 1 Wake up enabled Peripheral interrupt 0 23 I2C2 I2C2 i...

Page 57: ...pt 5 wake up 0 Wake up disabled 1 Wake up enabled Not for pattern match 0 3 PINT6 GPIO pin interrupt 6 wake up 0 Wake up disabled 1 Wake up enabled Not for pattern match 0 4 PINT7 GPIO pin interrupt 7 wake up 0 Wake up disabled 1 Wake up enabled Not for pattern match 0 7 5 Reserved Read value is undefined only zero should be written 0 8 RIT Repetitive Interrupt Timer interrupt wake up 0 Wake up di...

Page 58: ... address 0x4000 0250 bit description Bit Symbol Description Reset value 31 0 START_CLR0 Writing ones to this register clears the corresponding bit or bits in the STARTER0 register if they are implemented Bits that do not correspond to defined bits in STARTER0 are reserved and only zeroes should be written to them Table 80 Start enable clear register 1 STARTERCLR1 address 0x4000 0254 bit descriptio...

Page 59: ...ue 0 MASTERCPU Indicates which CPU is considered the master This is factory set assign the Cortex M4 as the master The master CPU cannot have its clock turned off via the related CMnCLKEN bit or be reset via the related CMxRSTEN in this register The slave CPU wakes up briefly following device reset then goes back to sleep until activated by the master CPU 1 0 M0 Cortex M0 is the master CPU 1 M4 Co...

Page 60: ... register to an appropriate address that is different than the master CPU 4 5 47 4 Coprocessor Status register CPU_STAT provides some status for dual CPUs This register can be read by software at run time or with a debugger Table 82 Coprocessor Boot register CPBOOT address 0x4000 0304 bit description Bit Symbol Description Reset value 31 0 BOOTADDR Slave processor boot address 0 Table 83 Coprocess...

Page 61: ...escription Bit Symbol Description Reset value 31 0 PARTID Part ID part dependent Table 87 Device ID0 register values Part number Part ID LPC54101J256 0x8845 4101 LPC54101J512 0x8885 4101 LPC54102J256 0x8845 4102 LPC54102J512 0x8885 4102 Table 88 Device ID1 register DEVICE_ID1 address 0x4000 03FC bit description Bit Symbol Description Value 31 0 REVID Revision part dependent Table 89 Device ID1 reg...

Page 62: ...lear reset to this function 1 Assert reset to this function 0 3 USART2 USART2 reset control 0 Clear reset to this function 1 Assert reset to this function 0 4 USART3 USART3 reset control 0 Clear reset to this function 1 Assert reset to this function 0 5 I2C0 I2C0 reset control 0 Clear reset to this function 1 Assert reset to this function 6 I2C1 I2C1 reset control 0 Clear reset to this function 1 ...

Page 63: ...l Description Reset value 0 Reserved Read value is undefined only zero should be written 1 USART0 Controls the clock for USART0 0 Disable 1 Enable 0 2 USART1 Controls the clock for USART1 0 Disable 1 Enable 0 3 USART2 Controls the clock for USART2 0 Disable 1 Enable 0 4 USART3 Controls the clock for USART3 0 Disable 1 Enable 0 5 I2C0 Controls the clock for I2C0 0 Disable 1 Enable 6 I2C1 Controls t...

Page 64: ... both be running and have occurred in specific states before the selection actually changes 4 5 58 Asynchronous clock source select register B This register selects the clock source for the asynchronous APB clock Remark Note that this selection is internally synchronized the clock being switched from and the clock being switched to must both be running and have occurred in specific states before t...

Page 65: ...rator 0xFF must first be written to the DIV value to yield a denominator value of 256 All other values are not supported See also Section 21 3 1 Configure the USART clock and baud rate and Section 21 7 1 Clocking and baud rates Table 97 Asynchronous clock source select register B ASYNCAPBCLKSELB address 0x4008 0024 bit description Bit Symbol Value Description Reset value 1 0 SEL Clock source for a...

Page 66: ...4 6 Functional description 4 6 1 Reset Reset has the following sources The RESET pin Watchdog reset Power On Reset POR Brown Out Detect BOD ARM software reset ISP AP debug reset Table 100 BOD control register BODCTRL address 0x4002 C044 bit description Bit Symbol Value Description Reset value 1 0 BODRSTLEV BOD reset level 0 0x0 Level 0 1 5 V 0x1 Level 1 1 85 V 0x2 Level 2 2 0 V 0x3 Level 3 2 3 V 2...

Page 67: ...e following processes are initiated 1 The IRC is enabled or starts up if not running 2 The flash wake up timer starts This takes approximately 250 ms or less 3 The boot code in the ROM starts The boot code performs the boot tasks and may jump to the flash When the internal Reset is removed the processor begins executing at address 0 which is initially the Reset vector mapped from the boot block At...

Page 68: ...ake up the chip from reduced power modes not including deep power down On the LPC5410x the BOD is enabled by default after power up At this time the BOD is set to the lowest value 1 5v with no factory trimming applied In the BOD block the interrupt portion is turned off and only the reset portion is on After POR BOD resets the BootROM takes over and applies the factory BOD trim value so that the t...

Page 69: ...ency must be in the range of 75 MHz to 150 MHz The multiplier works by dividing the CCO output by the value of M then using a phase frequency detector to compare the divided CCO output to the multiplier input The error value is filtered and used to adjust the CCO frequency There are additional dividers at the PLL output to bring the frequency down to what is needed for the CPU USB and other periph...

Page 70: ...h once it has regained lock on the input clock 4 6 4 3 Operating modes The PLL includes several main operating modes and a power down mode These are summarized in Table 101 and detailed in the following sections 1 Use 1 if the PLL output is used even though the PLL is not altering the frequency 4 6 4 3 1 Normal modes Typical operation of the PLL includes an optional pre divide of the PLL input fol...

Page 71: ...ut Fcco 2 x P M x Fin N x 2 x P 4 6 4 3 2 Fractional divider mode The PLL includes an fractional divide mode The fractional mode uses an integer divide value and that value plus 1 in a ratio determined by the fractional part of the divide value in order to obtain an average rate that is a fractional multiple of the PLL reference frequency The SEL_EXT bit in the SYSPLLSSCTRL0 register determines wh...

Page 72: ...nd any peripherals that are not meant to stopped as well must be running from some other clock source 4 6 4 4 PLL Related registers The PLL is controlled by registers described elsewhere in this chapter summarized below Fig 6 PLL block diagram showing spread spectrum and fractional divide operation LYLGH E 0 LYLGH E 3 5 72 3 66 5 7 LOWHU 3 66 2 9 1 15 4 0 05 4 3 35 4 2 6 6 5 6 3 LYLGH E 1 3 FRQWUR...

Page 73: ...ency must be either the actual desired output frequency or the desired output frequency times 2 x P where P is from 2 to 32 The Fcco frequency must also be a multiple of the PLL reference frequency which is either the PLL input or the PLL input divided by N where N is from 2 to 256 4 There may be several ways to obtain the same PLL output frequency PLL power depends on Fcco a lower frequency uses ...

Page 74: ...y measure function The Frequency Measure circuit is based on two 14 bit counters one clocked by the reference clock and one by the target clock Synchronization between the clocks is performed at the start and end of each count sequence A measurement cycle is initiated by software setting a control status bit in the FREQMECTRL register Table 61 The software can then poll this same measurement in pr...

Page 75: ... for example the 1 accuracy of the IRC will add to the measurement error of the target clock In general though this additional error is less than the uncertainty of the reference clock There can also be a modest loss of accuracy if the reference frequency exceeds the target frequency by a very large margin 25x or more Accuracy is not a simple function of the magnitude of the frequency difference h...

Page 76: ...ed by Vdd and includes the RTC and wakeup timer This domain always has power as long as sufficient voltage is supplied to Vdd Power use is controlled by settings in register within the SYSCON block regulator settings controlled via a Power API and the operating mode of a CPU The ROM based power configuration API configures the part for each reduced power mode The following modes are supported in o...

Page 77: ...own mode Deep power down mode IRC Software configurable Off Off Off Flash Software configurable On Off Off BOD Software configurable Software configurable Software configurable Off PLL Software configurable Off Off Off Watchdog osc and WWDT Software configurable Software configurable Software configurable Off USART Software configurable Off but can create a wake up interrupt in synchronous slave m...

Page 78: ...in the STARTER0 register RTC 1 kHz timer time out and alarm Enable the RTC 1 Hz oscillator and the RTC 1 kHz oscillator in the RTC CTRL register Start RTC 1 kHz timer by writing a time out value to the RTC WAKE register Enable the RTCWAKE interrupt in the STARTER0 register Micro tick timer specifically intended ultra low power wake up from Power down mode Enable the watchdog oscillator in the PDRU...

Page 79: ...ol register 1 Generally speaking in order to save power functions that are not needed by the application should be turned off If specific times are known when certain functions will not be needed they can be turned off temporarily and turned back on when they will be needed The power to various analog blocks RAMs PLL oscillators the BOD circuit and the flash block can be controlled individually th...

Page 80: ...uration in Sleep mode Power consumption in Sleep mode is configured by the same settings as in Active mode The clock remains running The system clock frequency remains the same as in Active mode but the processor is not clocked Analog and digital peripherals are powered and selected as in Active mode through the PDRUNCFG AHBCLKCTRL0 AHBCLKCTRL1 registers 5 3 3 2 Programming Sleep mode The followin...

Page 81: ... selected wake up events in the STARTER registers Table 75 and Table 76 and in the NVIC 2 Select the IRC as the main clock and set the AHBCLKDIV register to 1 See Table 45 Table 46 and Table 58 3 Call the power API with the parameter peripheral set to enable the analog peripherals the serve as wake up sources see Table 471 Chip_POWER_EnterPowerMode routine pPWRD power_mode_configure DEEP_SLEEP per...

Page 82: ...s and in the NVIC In addition any related analog block e g the RTC oscillator or the watchdog oscillator must be explicitly enabled through the power API function power_mode_configure for wake up See Table 104 5 3 5 2 Programming Power down mode The following steps must be performed to enter Power down mode 1 Select wake up sources and enable all related wake up events in the STARTER registers Tab...

Page 83: ...ly the RTC is powered as long as power is supplied to the device 5 3 6 2 Wakeup from Deep power down mode Wakeup from Deep power down can be accomplished via the reset pin or the RTC 5 3 6 3 Programming Deep power down mode using the RTC for wake up The following steps must be performed to enter Deep power down mode when using the RTC for waking up 1 Set up the RTC high resolution timer Write to t...

Page 84: ...every time the part is powered on or reset see Figure 7 The loader can execute the ISP command handler or the user application code The boot loader version can be read by ISP IAP calls see Table 490 or Table 502 Assuming that power supply pins are at their nominal levels when the rising edge on RESET pin is generated it may take up to 3 ms before the boot pins are sampled and the decision whether ...

Page 85: ...13 September 2016 86 of 464 NXP Semiconductors UM10850 Chapter 6 LPC5410x Boot process 6 3 1 Boot process flowchart Fig 7 Boot process flowchart 5 6 7 1 7 5 9 5 67 5 48 1 581 63 200 1 1 5 581 872 8 53 1 7 2 6 7 53 12B 63 1 17 5 63 02 86 5 2 9 86 5 2 9 872 8 68 66 8 87 17 51 86 5 2 1 8 HV HV HV HV HV HV HV QR QR QR QR QR QR QR 86 57 63 ...

Page 86: ...nverted function Pins PIO0_23 through PIO0_28 are true open drain pins that can be configured for different I2C bus speeds 7 3 Basic configuration Enable the clock to the IOCON in the AHBCLKCTRL0 register Table 51 Once the pins are configured the IOCON clock can be disabled in order to conserve power UM10850 Chapter 7 LPC5410x I O pin configuration IOCON Rev 2 4 13 September 2016 User manual Table...

Page 87: ...ins that have an analog alternate function have an analog mode can be selected Details of the IOCON registers are in Section 7 4 2 The following sections describe specific characteristics of pins Multiple connections Since a particular peripheral function may be allowed on more than one pin it is possible to configure more than one pin to perform the same function If a peripheral output function i...

Page 88: ...red as an input and is not driven externally Such state retention is not applicable to the Deep Power down mode Repeater mode may typically be used to prevent a pin from floating and potentially using significant power if it floats to an indeterminate state if it is temporarily not driven 7 4 2 3 Hysteresis The input buffer for digital functions has built in hysteresis See the appropriate specific...

Page 89: ... I2C with specialized pad electronics P0 23 through P0 28 have additional configuration bits These have multiple configurations to support I2C variants These are not hard wired so that the pins can be more easily used for non I2C functions See Table 113 for recommended mode settings For non I2C operation these pins remain open drain and can only drive low regardless of how I2CSLEW and I2CDRIVE are...

Page 90: ...Offset Description Reset value 1 Pin type Section PIO0_ 0 1 R W 0x000 0x004 Digital I O control for port 0 pins PIO0_0 to PIO0_1 0x0190 D 7 5 1 PIO0_ 4 22 R W 0x010 0x058 Digital I O control for port 0 pins PIO4 to PIO0_22 PIO0_16 17 0x0195 others 0x0190 D 7 5 1 PIO0_ 23 28 R W 0x05C 0x070 Digital I O control for port 0 pins PIO0_23 to PIO0_28 These pins support I2C with true open drain drive and ...

Page 91: ...ODE Selects function mode on chip pull up pull down resistor control 10 0x0 Inactive Inactive no pull down pull up resistor enabled 0x1 Pull down Pull down resistor enabled 0x2 Pull up Pull up resistor enabled 0x3 Repeater Repeater mode 5 Reserved Read value is undefined only zero should be written NA 6 INVERT Input polarity 0 0 Disabled Input function is not inverted 1 Enabled Input is function i...

Page 92: ...0_5 U1_RXD SCT0_OUT6 CT32B0_MAT0 PIO0_6 PIO0_6 U1_TXD CT32B0_MAT1 PIO0_7 PIO0_7 U1_SCLK SCT0_OUT0 CT32B0_MAT2 CT32B0_CAP2 PIO0_8 PIO0_8 U2_RXD SCT0_OUT1 CT32B0_MAT3 PIO0_9 PIO0_9 U2_TXD SCT0_OUT2 CT32B3_CAP0 SPI0_SSELN0 PIO0_10 PIO0_10 U2_SCLK SCT0_OUT3 CT32B3_MAT0 PIO0_11 PIO0_11 SPI0_SCK U1_RXD CT32B2_MAT1 PIO0_12 PIO0_12 SPI0_MOSI U1_TXD CT32B2_MAT3 PIO0_13 PIO0_13 SPI0_MISO SCT0_OUT4 CT32B2_MA...

Page 93: ...is not inverted 1 Enabled Input is function inverted 7 DIGIMODE Select Analog Digital mode 1 0 Analog mode 1 Digital mode 8 FILTEROFF Controls input glitch filter 1 0 Filter enabled Noise pulses below approximately 10 ns are filtered out 1 Filter disabled No input filtering is done 9 I2CDRIVE Controls the current sink capability of the pin 0 0 Low drive Output drive sink is 4 mA This is sufficient...

Page 94: ...0 Table 115 Address map PIO0_ 29 31 registers Peripheral Base address Offset Increment Dimension IOCON 0x4001 C000 0x074 0x07C 0x4 3 Table 116 Type A IOCON registers PIO0_ 29 31 address offsets 0x074 0x07C bit description Bit Symbol Value Description Reset value 2 0 FUNC Selects pin function 0 4 3 MODE Selects function mode on chip pull up pull down resistor control 10 0x0 Inactive Inactive no pul...

Page 95: ...n Bit Symbol Value Description Reset value 2 0 FUNC Selects pin function 0 4 3 MODE Selects function mode on chip pull up pull down resistor control 10 0x0 Inactive Inactive no pull down pull up resistor enabled 0x1 Pull down Pull down resistor enabled 0x2 Pull up Pull up resistor enabled 0x3 Repeater Repeater mode 5 Reserved Read value is undefined only zero should be written NA 6 INVERT Input po...

Page 96: ...egister 000 001 010 011 100 101 110 111 PIO0_29 PIO0_29 ADC_0 SCT0_OUT2 CT32B0_MAT3 CT32B0_CAP1 CT32B0_MAT1 PIO0_30 PIO0_30 ADC_1 SCT0_OUT3 CT32B0_MAT2 CT32B0_CAP2 PIO0_31 PIO0_31 ADC_2 U2_CTS CT32B2_CAP2 CT32B0_CAP3 CT32B0_MAT3 PIO1_0 PIO1_0 ADC_3 U2_RTS CT32B3_MAT1 CT32B0_CAP0 PIO1_1 PIO1_1 ADC_4 SWO SCT0_OUT4 PIO1_2 PIO1_2 ADC_5 SPI1_SSELN3 SCT0_OUT5 PIO1_3 PIO1_3 ADC_6 SPI1_SSELN2 SCT0_OUT6 SP...

Page 97: ... Inactive Inactive no pull down pull up resistor enabled 0x1 Pull down Pull down resistor enabled 0x2 Pull up Pull up resistor enabled 0x3 Repeater Repeater mode 5 Reserved Read value is undefined only zero should be written NA 6 INVERT Input polarity 0 0 Disabled Input function is not inverted 1 Enabled Input is function inverted 7 DIGIMODE Select Analog Digital mode 1 0 Analog mode 1 Digital mod...

Page 98: ...gisters FUNC values and pin functions Value of FUNC field in IOCON register Register 000 001 010 011 100 101 110 111 PIO1_9 PIO1_9 SPI0_MOSI CT32B0_CAP2 PIO1_10 PIO1_10 U1_TXD SCT0_OUT4 PIO1_11 PIO1_11 U1_RTS CT32B1_CAP0 PIO1_12 PIO1_12 U3_RXD CT32B1_MAT0 SPI1_SCK PIO1_13 PIO1_13 U3_TXD CT32B1_MAT1 SPI1_MOSI PIO1_14 PIO1_14 U2_RXD SCT0_OUT7 SPI1_MISO PIO1_15 PIO1_15 SCT0_OUT5 CT32B1_CAP3 SPI1_SSEL...

Page 99: ... description The input multiplexer has no dedicated pins However all digital pins of ports 0 and 1 can be selected as inputs to the pin interrupts Multiplexer inputs from external pins work independently of any other function assigned to the pin as long as no analog function is enabled 8 5 General description The inputs to the DMA triggers to the eight pin interrupts and to the frequency measure b...

Page 100: ... engine multiplexes all existing pins from ports 0 and 1 8 5 2 DMA trigger input multiplexing Fig 9 Pin interrupt multiplexing L L 9 7 7 2 9 7 7 2 3 176 3 176 DOO SLQV 3 2 BP DOO SLQV 3 2 BP 1387 08 19 SLQ LQWHUUXSW 19 SLQ LQWHUUXSW 3DWWHUQ PDWFK HQJLQH VOLFHV WR 3DWWHUQ PDWFK HQJLQH VOLFHV WR Fig 10 DMA trigger multiplexing 0 FKDQQHO Q 0 B275 B 108 0 B 75 B 108 Q 0 B275 B 108 1387 08 13B1 13B1 13...

Page 101: ... DMA_ITRIG_INMUX5 R W 0x0F4 Trigger select register for DMA channel 5 0x1F Table 128 DMA_ITRIG_INMUX6 R W 0x0F8 Trigger select register for DMA channel 6 0x1F Table 128 DMA_ITRIG_INMUX7 R W 0x0FC Trigger select register for DMA channel 7 0x1F Table 128 DMA_ITRIG_INMUX8 R W 0x100 Trigger select register for DMA channel 8 0x1F Table 128 DMA_ITRIG_INMUX9 R W 0x104 Trigger select register for DMA chan...

Page 102: ...he pin interrupts must be enabled in the NVIC see Table 2 before it becomes active To use the selected pins for pin interrupts or the pattern match engine see Section 10 5 2 Pattern match engine DMA_OTRIG_INMUX3 R W 0x14C DMA output trigger selection to become DMA trigger 19 0x1F Table 130 FREQMEAS_REF R W 0x160 Clock selection for frequency measurement function reference clock 0x1F Table 131 FREQ...

Page 103: ...127 Address map DMA_ITRIG_INMUX 0 21 registers Peripheral Base address Offset Increment Dimension INPUTMUX 0x4005 0000 0x0E0 0x134 0x4 22 Table 128 DMA trigger Input mux registers DMA_ITRIG_INMUX 0 21 address offsets 0x0E0 0x134 bit description Bit Symbol Description Reset value 4 0 INP Trigger input number decimal value for DMA channel n n 0 to 21 0 ADC0 Sequence A interrupt 1 ADC0 Sequence B int...

Page 104: ...tember 2016 105 of 464 NXP Semiconductors UM10850 Chapter 8 LPC5410x Input multiplexing INPUT MUX Table 130 DMA output trigger feedback mux registers DMA_OTRIG_INMUX 0 3 address offset 0x140 0x14C bit description Bit Symbol Description Reset value 4 0 INP DMA trigger output number decimal value for DMA channel n n 0 to 19 0x1F 31 5 Reserved ...

Page 105: ... See Section 4 6 5 Frequency measure function Section 4 2 3 Measure the frequency of a clock signal Section 4 5 32 Frequency measure function control register and Section 8 6 4 above for more on this function Table 131 Frequency measure function frequency clock select register FREQMEAS_REF address 0x4005 0160 bit description Bit Symbol Description Reset value 4 0 CLKIN Clock source number decimal ...

Page 106: ...o be sensed and set individually 9 4 General description The GPIO pins can be used in several ways to set pins as inputs or outputs and use the inputs as combinations of level and edge sensitive interrupts The GPIOs can be used as external interrupts together with the pin interrupt and group interrupt blocks see Chapter 10 and Chapter 11 The GPIO port registers configure each GPIO pin as input or ...

Page 107: ...ers port 0 0 32 9 5 3 DIR1 R W 0x2004 Direction registers port 1 0 32 9 5 3 MASK0 R W 0x2080 Mask register port 0 0 32 9 5 4 MASK1 R W 0x2084 Mask register port 1 0 32 9 5 4 PIN0 R W 0x2100 Port pin register port 0 ext 32 9 5 5 PIN1 R W 0x2104 Port pin register port 1 ext 32 9 5 5 MPIN0 R W 0x2180 Masked port register port 0 ext 32 9 5 6 MPIN1 R W 0x2184 Masked port register port 1 ext 32 9 5 6 SE...

Page 108: ...ts Table 135 Address map B 0 49 registers Peripheral Base address Offset Increment Dimension GPIO 0x1C00 0000 0x000 0x031 0x1 50 Table 136 GPIO port byte pin registers B 0 49 address offset 0x0000 0x0031 bit description Bit Symbol Description Reset value Access 0 PBYTE Read state of the pin PIOm_n regardless of direction masking or alternate function except that pins configured as analog I O alway...

Page 109: ...t 0x2000 0x2004 bit description Bit Symbol Description Reset value Access 31 0 DIRP Selects pin direction for pin PIOm_n Supported pins depends on the specific device and package 0 input 1 output 0 R W Table 141 Address map MASK 0 1 registers Peripheral Base address Offset Increment Dimension GPIO 0x1C00 0000 0x2080 0x2084 0x4 2 Table 142 GPIO mask port register MASK 0 1 address offset 0x2080 0x20...

Page 110: ...ase address Offset Increment Dimension GPIO 0x1C00 0000 0x2180 0x2184 0x4 2 Table 146 GPIO masked port pin register MPIN 0 1 address offset 0x2180 0x2184 bit description Bit Symbol Description Reset value Access 31 0 MPORTP Masked port register Supported pins depends on the specific device and package 0 Read pin is LOW and or the corresponding bit in the MASK register is 1 write clear output bit i...

Page 111: ... 1 Clear output bit NA WO Table 151 Address map NOT 0 1 registers Peripheral Base address Offset Increment Dimension GPIO 0x1C00 0000 0x2300 0x2304 0x4 2 Table 152 GPIO toggle port register NOT 0 1 address offset 0x2300 0x2304 bit description Bit Symbol Description Reset value Access 31 0 NOTP Toggle output bits Supported pins depends on the specific device and package 0 no operation 1 Toggle outp...

Page 112: ...9 5 12 GPIO port direction toggle registers Direction bits can be set by writing ones to these write only registers Table 155 GPIO port direction toggle register DIRNOT 0 1 offset 0x2480 0x2484 bit description Bit Symbol Description Reset value Access 28 0 DIRNOTP Toggle direction bits bit 0 PIOn_0 bit 1 PIOn_1 etc Supported pins depends on the specific device and package 0 no operation 1 Toggle d...

Page 113: ...ts are the targets of write operations to the pins Two conditions must be met in order for a pin s output bit to be driven onto the pin 1 The pin must be selected for GPIO operation via IOCON this is the default and 2 the pin must be selected for output by a 1 in its port s DIR register If either or both of these conditions is are not met writing to the pin has no effect There are seven ways to ch...

Page 114: ...y to protect a block of code that uses a MASK register is to disable interrupts before setting the MASK register and re enable them after the last operation that uses the MPORT or MASK register More efficiently software can dedicate a semaphore to the MASK registers and set capture the semaphore controlling exclusive use of the MASK registers before setting the MASK registers and release the semap...

Page 115: ... sensitive interrupt pins can be HIGH or LOW active Pattern match engine Up to 8 pins can be selected from all digital pins on ports 0 and 1 to contribute to a boolean expression The boolean expression consists of specified levels and or transitions on various combinations of these pins Each bit slice minterm product term comprising the specified boolean expression can generate its own dedicated i...

Page 116: ...he pin selection process is the same for pin interrupts and the pattern match engine The two features are mutually exclusive Enable the clock to the pin interrupt register block in the AHBCLKCTRL0 register Table 51 Each bit slice of the pattern match engine is assigned to one interrupt in the NVIC interrupts 5 through 8 for pin interrupts 0 to 3 and 33 through 36 for pin interrupts 4 through 7 10 ...

Page 117: ... on rising or falling edges or on the input level on the pin 10 5 2 Pattern match engine The pattern match feature allows complex boolean expressions to be constructed from the same set of eight GPIO pins that were selected for the GPIO pin interrupts Each term in the boolean expression is implemented as one slice of the pattern match engine A slice consists of an input selector and a detect logic...

Page 118: ...ges can create a pin interrupt by combining a level detect with an event detect See Section 10 7 3 for details The connections between the pins and the pattern match engine are shown in Figure 12 All pins that are inputs to the pattern match engine are selected in the Syscon block and can be GPIO port pins or other pin function depending on the IOCON configuration Remark note that the pattern matc...

Page 119: ...te that if the pin interrupts are selected the RXEV request to the CPU can still be enabled for pattern matches Remark Pattern matching cannot be used to wake the part up from power down modes Pin interrupts must be selected in order to use the GPIO for wake up The pattern match module is constructed of eight bit slice elements Each bit slice is programmed to represent one component of one minterm...

Page 120: ...nitors for a rising edge on input IN3 If this combination is detected that is if all three terms are true the interrupt associated with bit slice 2 will be asserted In the second minterm IN1 IN2 bit slice 3 monitors input IN1 for a high level bit slice 4 monitors input IN2 for a high level If this combination is detected the interrupt associated with bit slice 4 will be asserted In the third minte...

Page 121: ...nterrupt set register NA Table 159 CIENR WO 0x00C Pin interrupt level rising edge interrupt clear register NA Table 160 IENF R W 0x010 Pin interrupt active level or falling edge interrupt enable register 0 Table 161 SIENF WO 0x014 Pin interrupt active level or falling edge interrupt set register NA Table 162 CIENF WO 0x018 Pin interrupt active level or falling edge interrupt clear register NA Tabl...

Page 122: ...he IENR register depending on the pin interrupt mode configured in the ISEL register If the pin interrupt mode is edge sensitive PMODE 0 the rising edge interrupt is set If the pin interrupt mode is level sensitive PMODE 1 the level interrupt is set Table 157 Pin interrupt mode register ISEL address 0x4001 8000 bit description Bit Symbol Description Reset value Access 7 0 PMODE Selects the interru...

Page 123: ...DE 1 the active level of the level interrupt HIGH or LOW is configured 10 6 6 Pin interrupt active level or falling edge interrupt set register For each of the 8 pin interrupts selected in the PINTSELn registers see Table 126 one bit in the SIENF register sets the corresponding bit in the IENF register depending on the pin interrupt mode configured in the ISEL register If the pin interrupt mode is...

Page 124: ... regardless of whether they are interrupt enabled Table 162 Pin interrupt active level or falling edge interrupt set register SIENF address 0x4001 8014 bit description Bit Symbol Description Reset value Access 7 0 SETENAF Ones written to this address set bits in the IENF thus enabling interrupts Bit n sets bit n in the IENF register 0 No operation 1 Select HIGH active interrupt or enable falling e...

Page 125: ...This register also allows the current state of any pattern matches to be read If the pattern match feature is not used either for interrupt generation or for RXEV assertion bits SEL_PMATCH and ENA_RXEV of this register should be left at 0 to conserve power Remark Set up the pattern match configuration in the PMSRC and PMCFG registers before writing to this register to enable or re enable the patte...

Page 126: ...rupts are driven in response to the standard pin interrupt function 1 Pattern match Interrupts are driven in response to pattern matches 1 ENA_RXEV Enables the RXEV output to the CPU and or to a GPIO output when the specified boolean expression evaluates to true 0 0 Disabled RXEV output to the CPU is disabled 1 Enabled RXEV output to the CPU is enabled 23 2 Reserved Do not write 1s to unused bits ...

Page 127: ... pin selected in the PINTSEL6 register as the source to bit slice 2 0x7 Input 7 Selects the pin selected in the PINTSEL7 register as the source to bit slice 2 19 17 SRC3 Selects the input source for bit slice 3 0 0x0 Input 0 Selects the pin selected in the PINTSEL0 register as the source to bit slice 3 0x1 Input 1 Selects the pin selected in the PINTSEL1 register as the source to bit slice 3 0x2 I...

Page 128: ...pin selected in the PINTSEL6 register as the source to bit slice 5 0x7 Input 7 Selects the pin selected in the PINTSEL7 register as the source to bit slice 5 28 26 SRC6 Selects the input source for bit slice 6 0 0x0 Input 0 Selects the pin selected in the PINTSEL0 register as the source to bit slice 6 0x1 Input 1 Selects the pin selected in the PINTSEL1 register as the source to bit slice 6 0x2 In...

Page 129: ...rmines whether slice 0 is an endpoint 0 0 No effect Slice 0 is not an endpoint 1 endpoint Slice 0 is the endpoint of a product term minterm Pin interrupt 0 in the NVIC is raised if the minterm evaluates as true 1 PROD_EN DPTS1 Determines whether slice 1 is an endpoint 0 0 No effect Slice 1 is not an endpoint 1 endpoint Slice 1 is the endpoint of a product term minterm Pin interrupt 1 in the NVIC i...

Page 130: ... occurs on an event i e when either a rising or falling edge is first detected on the specified input this is a non sticky version of value 0x3 This bit is cleared after one clock cycle 13 11 CFG1 Specifies the match contribution condition for bit slice 1 0b000 0x0 Constant HIGH This bit slice always contributes to a product term match 0x1 Sticky rising edge Match occurs if a rising edge on the sp...

Page 131: ...a rising or falling edge is first detected on the specified input this is a non sticky version of value 0x3 This bit is cleared after one clock cycle 19 17 CFG3 Specifies the match contribution condition for bit slice 3 0b000 0x0 Constant HIGH This bit slice always contributes to a product term match 0x1 Sticky rising edge Match occurs if a rising edge on the specified input has occurred since the...

Page 132: ...a rising or falling edge is first detected on the specified input this is a non sticky version of value 0x3 This bit is cleared after one clock cycle 25 23 CFG5 Specifies the match contribution condition for bit slice 5 0b000 0x0 Constant HIGH This bit slice always contributes to a product term match 0x1 Sticky rising edge Match occurs if a rising edge on the specified input has occurred since the...

Page 133: ...a rising or falling edge is first detected on the specified input this is a non sticky version of value 0x3 This bit is cleared after one clock cycle 31 29 CFG7 Specifies the match contribution condition for bit slice 7 0b000 0x0 Constant HIGH This bit slice always contributes to a product term match 0x1 Sticky rising edge Match occurs if a rising edge on the specified input has occurred since the...

Page 134: ... IN6fe IN5 IN7ev with IN6fe sticky falling edge on input 6 IN7ev non sticky event rising or falling edge on input 7 Each individual term in the expression shown above is controlled by one bit slice To specify this expression program the pattern match bit slice source and configuration register fields as follows PMSRC register Table 168 Since bit slice 5 will be used to detect a sticky event on inp...

Page 135: ... on the selected input input 3 for bit slice 4 CFG5 010 sticky falling edge on the selected input input 6 for bit slice 5 CFG6 000 high level on the selected input input 5 for bit slice 6 CFG7 111 event any edge non sticky on the selected input input 7 for bit slice 7 PMCTRL register Table 167 Bit0 Setting this bit will select pattern matches to generate the pin interrupts in place of the normal p...

Page 136: ...352 B 1376 VWLFN ULVLQJ HGJH GHWHFWLRQ 1 65 352 B 1376 QRQ VWLFN HGJH GHWHFWLRQ 19 SLQ LQWHUUXSW DQG 3 2B 17B 0 7 RXWSXW V VWHP FORFN VOLFH 1 UH VOLFH 1 HY PLQWHUP 1 UH 1 HY SLQ LQWHUUXSW UDLVHG RQ IDOOLQJ HGJH RQ LQSXW DQ WLPH DIWHU 1 KDV JRQH Figure shows pattern match functionality only and accurate timing is not implied Inputs INn are shown synchronized to the system clock for simplicity Fig 1...

Page 137: ... shows pattern match functionality only and accurate timing is not implied Inputs INn are shown synchronized to the system clock for simplicity Fig 16 Pattern match engine examples Windowed non sticky edge detect evaluates as false V VWHP FORFN 1 65 352 B 1376 KLJK OHYHO GHWHFWLRQ 1 65 352 B 1376 QRQ VWLFN HGJH GHWHFWLRQ 19 SLQ LQWHUUXSW DQG 3 2B 17B 0 7 RXWSXW VOLFH 1 VOLFH 1 HY PLQWHUP 1 1 HY QR...

Page 138: ...lexing Make sure that no analog function is selected on pins that are input to the group interrupts Selecting an analog function in IOCON disables the digital pad and the digital signal is tied to 0 11 3 General description The GPIO pins can be used in several ways to set pins as inputs or outputs and use the inputs as combinations of level and edge sensitive interrupts For each port pin connected...

Page 139: ...ster overview GROUP0 interrupt base address 0x4001 0000 GINT0 and 0x4001 4000 GINT1 Name Access Address offset Description Reset value Reference CTRL R W 0x000 GPIO grouped interrupt control register 0 Table 172 PORT_POL0 R W 0x020 GPIO grouped interrupt port 0 polarity register 0xFFFF FFFF Table 173 PORT_POL1 R W 0x024 GPIO grouped interrupt port 1 polarity register 0xFFFF FFFF Table 173 PORT_ENA...

Page 140: ...ses 0x4001 0000 GINT0 and 0x4001 4000 GINT1 bit description Bit Symbol Value Description Reset value 0 INT Group interrupt status This bit is cleared by writing a one to it Writing zero has no effect 0 0 No request No interrupt request is pending 1 Request active Interrupt request is active 1 COMB Combine enabled inputs for group interrupt 0 0 Or OR functionality A grouped interrupt is generated w...

Page 141: ...register The level on each pin is exclusive ORed with its polarity bit and the result is ANDed with its enable bit These results are then inclusive ORed among all the pins in the port to create the port s raw interrupt request The raw interrupt request from each of the two group interrupts is sent to the NVIC which can be programmed to treat it as level or edge sensitive or it can be edge detected...

Page 142: ... up to eight priority levels Continuous priority arbitration Address cache with four entries each entry is a pair of addresses Efficient use of data bus Supports single transfers up to 1 024 words Address increment options allow packing and or unpacking data 12 3 Basic configuration Configure the DMA as follows Use the AHBCLKCTRL0 register Table 51 to enable the clock to the DMA registers interfac...

Page 143: ...uts as a trigger source to a different channel in order to support complex transfers on selected peripherals This kind of transfer can for example use more than one peripheral DMA request An example use would be to input data to a holding buffer from one peripheral and then output the data to another peripheral with both transfers being paced by the appropriate peripheral DMA request This kind of ...

Page 144: ...76 DMA requests DMA channel Request input DMA trigger mux 0 USART0 RX DMA_ITRIG_INMUX0 1 USART0 TX DMA_ITRIG_INMUX1 2 USART1 RX DMA_ITRIG_INMUX2 3 USART1 TX DMA_ITRIG_INMUX3 4 USART2 RX DMA_ITRIG_INMUX4 5 USART2 TX DMA_ITRIG_INMUX5 6 USART3 RX DMA_ITRIG_INMUX6 7 USART3 TX DMA_ITRIG_INMUX7 8 SPI0 RX DMA_ITRIG_INMUX8 9 SPI0 TX DMA_ITRIG_INMUX9 10 SPI1 RX DMA_ITRIG_INMUX10 11 SPI1 TX DMA_ITRIG_INMUX1...

Page 145: ...on and can be a signal from an unrelated peripheral Peripherals that generate triggers are the SCT and the ADC In addition the DMA triggers also create an trigger output that can trigger DMA transactions on another channel Triggers can be used to send a character or a string to a USART or other serial output at a fixed time interval or when an event occurs A DMA channel using a trigger can respond...

Page 146: ...er length XFERCOUNT the address increment as defined by SRCINC and DSTINC The link to the next descriptor is used only if it is a linked transfer After the channel has had a sufficient number of DMA requests and or triggers depending on its configuration the initial descriptor will be exhausted At that point if the transfer configuration directs it the channel descriptor will be reloaded with data...

Page 147: ...e the channel descriptor is exhausted additional DMA requests or triggers will have no effect until the channel configuration is updated by software 12 5 4 Ping Pong Ping pong is a special case of a linked transfer It is described separately because it is typically used more frequently than more complicated versions of linked transfers A ping pong transfer uses two buffers alternately At any one t...

Page 148: ...he difference would be that descriptor B would not link back to descriptor A but would continue on to another different descriptor This could continue as long as desired and can be ended anywhere or linked back to any point to repeat a sequence of descriptors Of course any descriptor not currently in use can be altered by software as well 12 5 6 Address alignment for data transfers Transfers of 16...

Page 149: ...Set the trigger type to edge sensitive by clearing bit TRIGTYPE in the channel configuration register Configure the trigger edge to falling edge by clearing bit TRIGPOL in the channel configuration register After completion of channel x the descriptor may be reloaded if configured so but remains untriggered To configure the chain to auto trigger itself setup channels x and y for channel chaining a...

Page 150: ...0 Table 190 INTENSET0 R W 0x048 Interrupt Enable read and Set for all DMA channels 0 Table 191 INTENCLR0 WO 0x050 Interrupt Enable Clear for all DMA channels NA Table 192 INTA0 R W 0x058 Interrupt A status for all DMA channels 0 Table 193 INTB0 R W 0x060 Interrupt B status for all DMA channels 0 Table 194 SETVALID0 WO 0x068 Set ValidPending control bits for all DMA channels NA Table 195 SETTRIG0 W...

Page 151: ... Control and status register for DMA channel 8 Table 202 XFERCFG8 R W 0x488 Transfer configuration register for DMA channel 8 Table 204 Channel 9 registers CFG9 R W 0x490 Configuration register for DMA channel 9 Table 199 CTLSTAT9 RO 0x494 Control and status register for DMA channel 9 Table 202 XFERCFG9 R W 0x498 Transfer configuration register for DMA channel 9 Table 204 Channel 10 registers CFG1...

Page 152: ...17 RO 0x514 Control and status register for DMA channel 17 Table 202 XFERCFG17 R W 0x518 Transfer configuration register for DMA channel 17 Table 204 Channel 18 registers CFG18 R W 0x520 Configuration register for DMA channel 18 Table 199 CTLSTAT18 RO 0x524 Control and status register for DMA channel 18 Table 202 XFERCFG18 R W 0x528 Transfer configuration register for DMA channel 18 Table 204 Chan...

Page 153: ...ster CTRL address 0x1C00 4000 bit description Bit Symbol Value Description Reset value 0 ENABLE DMA controller master enable 0 0 Disabled The DMA controller is disabled This clears any triggers that were asserted at the point when disabled but does not prevent re triggering when the DMA controller is re enabled 1 Enabled The DMA controller is enabled 31 1 Reserved Read value is undefined only zero...

Page 154: ...riptor for DMA channel 0 0x000 Channel descriptor for DMA channel 1 0x010 Channel descriptor for DMA channel 2 0x020 Channel descriptor for DMA channel 3 0x030 Channel descriptor for DMA channel 4 0x040 Channel descriptor for DMA channel 5 0x050 Channel descriptor for DMA channel 6 0x060 Channel descriptor for DMA channel 7 0x070 Channel descriptor for DMA channel 8 0x080 Channel descriptor for DM...

Page 155: ...hen the read occurs This registers is read only A DMA channel is considered busy when there is any operation related to that channel in the DMA controller s internal pipeline This information can be used after a DMA channel is disabled by software but still active allowing confirmation that there are no remaining operations in progress for that channel Table 187 Enable Clear register 0 ENABLECLR0 ...

Page 156: ...gister The INTENCLR0 register is used to clear interrupt enable bits in INTENSET0 The register is write only 12 6 11 Interrupt A register The IntA0 register contains the interrupt A status for each DMA channel The status will be set when the SETINTA bit is 1 in the transfer configuration for a channel when the descriptor becomes exhausted Writing a 1 to a bit in this register clears the related IN...

Page 157: ...nce to pause at the Descriptor until software triggers the continuation If during DMA transmission a Channel Descriptor is found with CFGVALID set to 0 the DMA checks for a previously buffered SETVALID0 setting for the channel If found the DMA will set the descriptor valid clear the SV setting and resume processing the descriptor Otherwise the DMA pauses until the channels SETVALID0 bit is set 12 ...

Page 158: ...nger busy by checking the corresponding bit in BUSY Finally write a 1 to the proper bit of ABORT This prevents the channel from restarting an incomplete operation when it is enabled again Table 196 Set Trigger 0 register SETTRIG0 address 0x1C00 4070 bit description Bit Symbol Description Reset value 21 0 TRIG Set Trigger control bit for DMA channel 0 Bit n corresponds to DMA channel n 0 no effect ...

Page 159: ... trigger for this channel 0 0 Active low falling edge Hardware trigger is active low or falling edge triggered based on TRIGTYPE 1 Active high rising edge Hardware trigger is active high or rising edge triggered based on TRIGTYPE 5 TRIGTYPE Trigger Type Selects hardware trigger as edge triggered or level triggered 0 0 Edge Hardware trigger is edge triggered Transfers will be initiated and complete...

Page 160: ...A burst reading the same registers again for each burst 0 0 Disabled Source burst wrapping is not enabled for this DMA channel 1 Enabled Source burst wrapping is enabled for this DMA channel 15 DSTBURSTWRAP Destination Burst Wrap When enabled the destination data address for the DMA is wrapped meaning that the destination address range for each burst will be the same As an example this could be us...

Page 161: ...ch data is transferred for each trigger 1 1 1 Hardware DMA trigger is high level sensitive The BURSTPOWER field controls address wrapping if enabled via SrcBurstWrap and or DstBurstWrap and also determines how much data is transferred for each trigger Table 200 Trigger setting summary TrigBurst TrigType TrigPol Description Table 201 Address map CTLSTAT 0 21 registers Peripheral Base address Offset...

Page 162: ...ed SETVALID0 setting 1 Valid The current channel descriptor is considered valid 1 RELOAD Indicates whether the channel s control structure will be reloaded when the current descriptor is exhausted Reloading allows ping pong and linked transfers 0 0 Disabled Do not reload the channels control structure when the current descriptor is exhausted 1 Enabled Reload the channels control structure when the...

Page 163: ...th for each transfer This is the usual case when the source is memory 0x2 2 x width The source address is incremented by 2 times the amount specified by Width for each transfer 0x3 4 x width The source address is incremented by 4 times the amount specified by Width for each transfer 15 14 DSTINC Determines whether the destination address is incremented for each DMA transfer 0 0x0 No increment The ...

Page 164: ...Software triggering is accomplished by writing a 1 to the appropriate bit in the SETTRIG register Hardware triggering requires setup of the HWTRIGEN TRIGPOL TRIGTYPE and TRIGBURST fields in the CFG register for the related channel When a channel is initially set up the SWTRIG bit in the XFERCFG register can be set causing the transfer to begin immediately Once triggered transfer on a channel will ...

Page 165: ...limit halt the timer or change counting direction toggle outputs change the state Counter value can be loaded into capture register triggered by a match or input output toggle PWM features Counters can be used in conjunction with match registers to toggle outputs and create time proportioned PWM signals Up to 8 single edge or 6 dual edge PWM outputs with independent duty cycle and common PWM cycle...

Page 166: ...CTimer PWM SCT in the AHBCLKCTRL1 register Section 4 5 23 to enable the register interface and the peripheral clock Clear the SCT peripheral reset using the PRESETCTRL register Section 4 5 7 The SCT uses interrupt in slot 16 in the NVIC Table 2 Use the IOCON registers to connect the SCT outputs to external pins See Chapter 7 The SCT DMA request lines are connected to the DMA trigger inputs via the...

Page 167: ..._7 PIO018 IOCON register for the related pin See Chapter 7 SCT0_OUT1 PIO0_1 PIO0_8 PIO0_19 SCT0_OUT2 PIO0_9 PIO0_29 SCT0_OUT3 PIO0_0 PIO0_10 PIO0_30 SCT0_OUT4 PIO0_13 PIO1_1 PIO1_10 SCT0_OUT5 PIO0_14 PIO1_2 PIO1_15 SCT0_OUT6 PIO0_5 PIO1_3 SCT0_OUT7 PIO1_4 PIO1_14 internal ADC0 trigger SEQ_A SEQ_B Table 417 Table 418 Table 432 Table 207 Suggested SCT input pin settings IOCON bit s Type D pin Type A...

Page 168: ...rect response to one if these user defined events without any software overhead Any event can be enabled to Start stop or halt the counter Limit the counter which means to clear the counter in unidirectional mode or change its direction in bi directional mode Set clear or toggle any SCT output Force a capture of the count value into any capture registers Generate an interrupt of DMA request The SC...

Page 169: ...iltering out events in either state In such a two state system different waveforms at the SCT output can be created depending on the event history Changing between states is event driven and happens without any intervention by the CPU Formally the SCTimer PWM can be programmed as state machine generator The ability to perform switching between groups of events provides the SCT the unique capabilit...

Page 170: ... setting of the UNIFY bit is reflected in the register map UNIFY 1 Only one register is used for operation as one 32 bit counter timer UNIFY 0 Access the L and H registers by a 32 bit read or write operation or can be read or written to individually for operation as two 16 bit counter timers Typically the UNIFY bit is configured by writing to the CONFIG register before any other registers are acce...

Page 171: ...W 0x016 SCT start event select register high counter 16 bit 0x0000 0000 Table 215 COUNT R W 0x040 SCT counter register 0x0000 0000 Table 216 COUNT_L R W 0x040 SCT counter register low counter 16 bit 0x0000 0000 Table 216 COUNT_H R W 0x042 SCT counter register high counter 16 bit 0x0000 0000 Table 216 STATE R W 0x044 SCT state register 0x0000 0000 Table 217 STATE_L R W 0x044 SCT state register low ...

Page 172: ...GMODE12_L 1 0x0000 0000 Table 232 CAPCTRL0_H to CAPCTRL12_H R W 0x202 to 0x232 SCT capture control register 0 to 12 high counter 16 bit REGMODE0 1 to REGMODE12 1 0x0000 0000 Table 232 EV0_STATE R W 0x300 SCT event state register 0 0x0000 0000 Table 233 EV0_CTRL R W 0x304 SCT event control register 0 0x0000 0000 Table 234 EV1_STATE R W 0x308 SCT event state register 1 0x0000 0000 Table 233 EV1_CTRL...

Page 173: ...235 OUT0_CLR R W 0x504 SCT output 0 clear register 0x0000 0000 Table 236 OUT1_SET R W 0x508 SCT output 1 set register 0x0000 0000 Table 235 OUT1_CLR R W 0x50C SCT output 1 clear register 0x0000 0000 Table 236 OUT2_SET R W 0x510 SCT output 2 set register 0x0000 0000 Table 235 OUT2_CLR R W 0x514 SCT output 2 clear register 0x0000 0000 Table 236 OUT3_SET R W 0x518 SCT output 3 set register 0x0000 000...

Page 174: ...ter direction select one EVm_CTRL event m EVm_STATE OUT_SET OUT_CLR OUT p 0 _SET OUT p 0 _CLR SET CLRm yes no select event m to capture the counter value in CAPn CAPCTRL i 0 CAPCTRL CAPCONm yes no select event m to limit the counter LIMIT LIMMSKm event m event m event m event m yes no select event m to raise the SCT interrupt EVEN IENm event m yes no select event m to trigger DMA requests 0 and 1 ...

Page 175: ...h a match reload register which automatically reloads the match register at the beginning of each counter cycle This register group includes the following registers One REGMODE register per match capture register to configure each match capture register for either storing a match value or a capture value A set of match capture registers with each register depending on the setting of REGMODE either...

Page 176: ... dual counter mode the events can be selected independently for each output 13 6 1 6 Event select registers for capturing a counter value This group contains registers that select events which capture the counter value and store it in one of the CAP registers Each capture register m has one associated CAPCTRLm register which in turn selects the events to capture the counter value 13 6 1 7 Event se...

Page 177: ...st being synchronized to the system clock The minimum pulse width on the clock input is 1 bus clock period This mode is the low power sampled clock mode 0x3 Asynchronous Mode The entire SCT module is clocked directly by the input edge selected by the CKSEL field In this mode the SCT outputs are switched synchronously to the SCT input clock not the system clock The input clock rate must be at least...

Page 178: ...0 bit 10 input 1 bit 12 input 3 all other bits are reserved A 1 in one of these bits subjects the corresponding input to synchronization to the SCT clock before it is used to create an event If an input is known to already be synchronous to the SCT clock this bit may be set to 0 for faster input response Note The SCT clock is the system clock for CKMODEs 0 2 It is the selected asynchronous SCT inp...

Page 179: ...lways reads as 0 0 4 BIDIR_L L or unified counter direction select 0 0 Up The counter counts up to a limit condition then is cleared to zero 1 Up down The counter counts up to a limit then counts down to a limit condition or to 0 12 5 PRE_L Specifies the factor by which the SCT clock is prescaled to produce the L or unified counter clock The counter clock is clocked at the rate of the SCT clock di...

Page 180: ...eature see Table 210 If UNIFY 1 in the CONFIG register only the _L bits are used If UNIFY 0 in the CONFIG register this register can be written to as two registers LIMIT_L and LIMIT_H Both the L and H registers can be read or written individually or in a single 32 bit read or write operation 13 6 5 SCT halt event select register The running counter can be disabled halted by an event When any of th...

Page 181: ...etc Setting a bit will cause its associated event to serve as a STOP event To define the actual event that causes the counter to stop a match an I O pin toggle etc see the EVn_CTRL register Remark Software can stop and restart the counter by writing to the CTRL register If UNIFY 1 in the CONFIG register only the _L bits are used If UNIFY 0 in the CONFIG register this register can be written to as ...

Page 182: ...fied register is only allowed when the corresponding counter is halted HALT bits are set to 1 in the CTRL register Attempting to write to the counter when it is not halted causes a bus error Software can read the counter registers at any time 13 6 9 SCT state register Each group of enabled and disabled events is assigned a number called the state variable For example a state variable with a value ...

Page 183: ...of the state variable during multiple counter cycles reflects how the associated state machine moves from one state to the next If UNIFY 1 in the CONFIG register only the _L bits are used If UNIFY 0 in the CONFIG register this register can be written to as two registers STATE_L and STATE_H Both the L and H registers can be read or written individually or in a single 32 bit read or write operation ...

Page 184: ...r toggled only by events However using this register software can write to any of the output registers when both counters are halted to control the outputs directly Writing to the OUT register is only allowed when Table 218 SCT input register INPUT address 0x5000 4048 bit description Bit Symbol Description Reset value 0 AIN0 Input 0 state Input 0 state on the last SCT clock edge 1 AIN1 Input 1 sta...

Page 185: ... direction of any counter 0x1 Set and clear are reversed when counter L or the unified counter is counting down 0x2 Set and clear are reversed when counter H is counting down Do not use if UNIFY 1 3 2 SETCLR1 Set clear operation on output 1 Value 0x3 is reserved Do not program this value 0 0x0 Set and clear do not depend on the direction of any counter 0x1 Set and clear are reversed when counter L...

Page 186: ... 0x5000 4058 bit description Bit Symbol Value Description Reset value 1 0 O0RES Effect of simultaneous set and clear on output 0 0 0x0 No change 0x1 Set output or clear based on the SETCLR0 field in the OUTPUTDIRCTRL register 0x2 Clear output or set based on the SETCLR0 field 0x3 Toggle output 3 2 O1RES Effect of simultaneous set and clear on output 1 0 0x0 No change 0x1 Set output or clear based ...

Page 187: ...p it is unlikely that software will see this flag it will be cleared rapidly by the DMA service The flag remaining set could point to an issue with DMA setup 0 Table 224 SCT DMA 1 request register DMAREQ1 address 0x5000 4060 bit description Bit Symbol Description Reset value 15 0 DEV_1 If bit n is one event n triggers DMA request 1 event 0 bit 0 event 1 bit 1 The number of bits number of events in...

Page 188: ...o the next value When a Match event limits its counter as described in Section 13 6 4 the value in the Match register is the last value of the counter before it is cleared to zero or decremented if BIDIR is 1 There is no write through from Reload registers to Match registers Before starting a counter software can write one value to the Match register used in the first cycle of the counter and a di...

Page 189: ... read or write the lower 16 bits of the 32 bit value to be compared to the unified counter 0 31 16 MATCHn_H When UNIFY 0 read or write the 16 bit value to be compared to the H counter When UNIFY 1 read or write the upper 16 bits of the 32 bit value to be compared to the unified counter 0 Table 230 SCT capture registers 0 to 12 CAP 0 12 address 0x5000 4100 CAP0 to 0x5000 4130 CAP12 bit description ...

Page 190: ... t change that is the state variable always remains at its reset value of 0 writing 0x01 permanently enables this event 13 6 25 SCT event control registers 0 to 12 This register defines the conditions for an event to occur based on the counter values or input and output states Once the event is configured it can be selected to trigger multiple actions for example stop the counter and toggle an out...

Page 191: ...lected by MATCHSEL 1 Selects the H state and the H match register selected by MATCHSEL 5 OUTSEL Input output select 0 0 Selects the inputs elected by IOSEL 1 Selects the outputs selected by IOSEL 9 6 IOSEL Selects the input or output signal number 0 to 3 for inputs or 0 to 5 for outputs associated with this event if any Do not select an input in this register if CKMODE is 1x In this case the clock...

Page 192: ...pin toggle etc see the EVn_CTRL register 20 MATCHMEM If this bit is one and the COMBMODE field specifies a match component to the triggering of this event then a match is considered to be active whenever the counter value is GREATER THAN OR EQUAL TO the value specified in the match register when counting up LESS THEN OR EQUAL TO the match value when counting down If this bit is zero a match is onl...

Page 193: ...This is true regardless of what triggered the event Table 236 SCT output clear register OUT 0 7 _CLR address 0x5000 4504 OUT0_CLR to 0x5000 453C OUT7_CLR bit description Bit Symbol Description Reset value 15 0 CLR A 1 in bit m selects event m to clear output n or set it if SETCLRn 0x1 or 0x2 event 0 bit 0 event 1 bit 1 up to the number of bits number of events in this SCT When the counter is used ...

Page 194: ...Event selection State variables allow control of the SCT across more than one cycle of the counter Counter matches input output edges and state values are combined into a set of general purpose events that can switch outputs request interrupts and change state values Fig 23 Match logic RXQWHU RXQWHU 0DWFK L 0DWFK 5HJ L 0DWFK 5HORDG L 0DWFK 5HJ L 0DWFK 5HORDG L 0DWFK L 81 Fig 24 Capture logic 6 7 F...

Page 195: ...ate when a user defined event triggers a state change The state change is triggered through each event s EV_CTRL register in one of the following ways The event can increment the current state number by a new value The event can write a new state value If an event increments the state number beyond the number of available states the SCT enters a locked state in which all further events are ignored...

Page 196: ... Clearing the prescaler When enabled by a non zero PRE field in the Control register the prescaler acts as a clock divider for the counter like a fractional part of the counter value The prescaler is cleared whenever the counter is cleared or loaded for any of the following reasons Hardware reset Software writing to the counter register Software writing a 1 to the CLRCTR bit in the control registe...

Page 197: ...e specific action of the SCT An action or multiple actions of the SCT uniquely define an event A state is defined by which events are enabled to trigger an SCT action or actions in any stage of the counter Events not selected for this state are ignored In a multi state configuration states change in response to events A state change is an additional action that the SCT can perform when the event o...

Page 198: ...ad register MATCHRELOAD sets a reload value that is loaded into the match register when the counter reaches a limit condition or the value 0 13 7 10 3 Configure events and event responses 1 Define when each event can occur in the following way in the EVn_CTRL registers up to 6 one register per event Select whether the event occurs on an input or output changing on an input or output level a match ...

Page 199: ...he corresponding event bit in the EVEN and the EVFLAG registers to enable the event to contribute to the SCT interrupt 13 7 10 4 Configure multiple states 1 In the EVn_STATE register for each event up to the maximum number of events on this device one register per event select the state or states up to 2 in which this event is allowed to occur Each state can be selected for more than one event 2 D...

Page 200: ...ut HIGH or LOW directly by writing to the OUT register The current state can be read at any time by reading the STATE register To change the current state by software that is independently of any event occurring set the HALT bit and write to the STATE register to change the state value Writing to the STATE register is only allowed when the counter is halted the HALT_L and or HALT_H bits are set an...

Page 201: ...unction 2 states This application of the SCT uses the following configuration all register values not listed in Table 238 are set to their default values Fig 28 SCT configuration example 67 7 67 7 67 7 6 7 RXWSXW 6 7 FRXQWHU 6 7 LQSXW PDWFK HYHQWV 9 9 9 9 9 9 9 9 9 9 0 7 872 0 7 9 9 9 9 LQSXW WUDQVLWLRQ HYHQWV 0 7 872 0 7 0 7 872 0 7 0 7 872 0 7 0 7 872 0 7 0 7 872 0 7 Table 238 SCT configuration ...

Page 202: ... associated with event 3 Define when event 4 occurs EV4_CTRL Set COMBMODE 0x1 Event 4 uses match condition only Set MATCHSEL 0x4 Select match value of match register 4 The match value of MAT4 is associated with event 4 Define when event 5 occurs EV5_CTRL Set COMBMODE 0x3 Event 5 uses match condition and I O condition Set IOSEL 0 Select input 0 Set IOCOND 0x3 Input 0 is HIGH Set MATCHSEL 0 Chooses ...

Page 203: ...75 14 3 Features Each is a 32 bit counter timer with a programmable 32 bit prescaler Four of the timers include external capture and match pin connections Counter or timer operation For each timer with pin connections up to 4 32 bit capture channels that can take a snapshot of the timer value when an input signal transitions A capture event may also optionally generate an interrupt The timer and p...

Page 204: ...three match registers can be used to provide a single edge controlled PWM output on the match output pins One match register is used to control the PWM cycle length 14 5 1 Capture inputs The capture signal can be configured to load the Capture Register with the value in the counter timer and optionally generate an interrupt The capture signal is generated by one of the pins with a capture function...

Page 205: ... UM10850 Chapter 14 LPC5410x Standard counter timers CT32B0 1 2 3 4 Fig 29 32 bit counter timer block diagram UHVHW 0 9 7 0 5 21752 5 67 5 35 6 5 67 5 35 6 2817 5 3 HQDEOH 3785 5 67 5 3785 5 67 5 0 7 5 67 5 0 7 5 67 5 0 7 5 67 5 0 7 5 67 5 3785 21752 5 67 5 21752 7 0 5 2817 5 61 7 3785 5 67 5 17 55837 5 67 5 7 51 0 7 5 67 5 0 7 21752 5 67 5 0 7 17 55837 3 6723 21 0 7 5 6 7 21 0 7 2 ...

Page 206: ...ture signal as a clock source instead of the PCLK derived clock For more details see Section 14 7 11 CT32B0_MAT1 0 CT32B1_MAT1 0 CT32B2_MAT3 0 CT32B3_MAT1 0 Output External Match Output When a match register MR3 0 equals the timer counter TC this output can either toggle go low go high or do nothing The External Match Register EMR controls the functionality of this output Match Output functionalit...

Page 207: ...he 32 bit PC is a counter which is incremented to the value stored in PR When the value in PR is reached the TC is incremented and the PC is cleared The PC is observable and controllable through the bus interface 0 Table 251 MCR R W 0x14 Match Control Register The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs 0 Table 253 MR0 R W 0x18 Match Register ...

Page 208: ...0 1 CT32B1 0x400B 8000 0x000 1 CT32B2 0x4000 4000 0x000 1 CT32B3 0x4000 8000 0x000 1 CT32B4 0x4000 C000 0x000 1 Table 243 Interrupt Register IR address offset 0x000 bit description Bit Symbol Description Reset Value 0 MR0INT Interrupt flag for match channel 0 0 1 MR1INT Interrupt flag for match channel 1 0 2 MR2INT Interrupt flag for match channel 2 0 3 MR3INT Interrupt flag for match channel 3 0 ...

Page 209: ...can be used to detect an overflow if needed 1 CRST Counter reset 0 0 Disabled Do nothing 1 Enabled The Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of PCLK The counters remain reset until TCR 1 is returned to zero 31 2 Reserved Read value is undefined only zero should be written NA Table 245 Timer Control Register TCR address offset 0x004 bit description...

Page 210: ...when PR 0 every 2 pclks when PR 1 etc 14 7 6 Match Control Register The Match Control Register is used to control what operations are performed when one of the Match Registers matches the Timer Counter Table 248 Address map PR register Peripheral Base address Offset Increment Dimension CT32B0 0x400B 4000 0x00C 1 CT32B1 0x400B 8000 0x00C 1 CT32B2 0x4000 4000 0x00C 1 CT32B3 0x4000 8000 0x00C 1 CT32B...

Page 211: ...the TC 0 disabled 1 enabled 0 3 MR1I Interrupt on MR1 an interrupt is generated when MR1 matches the value in the TC 0 disabled 1 enabled 0 disabled 1 enabled 0 4 MR1R Reset on MR1 the TC will be reset if MR1 matches it 0 disabled 1 enabled 0 5 MR1S Stop on MR1 the TC and PC will be stopped and TCR 0 will be set to 0 if MR1 matches the TC 0 disabled 1 enabled 0 6 MR2I Interrupt on MR2 an interrupt...

Page 212: ...ion Bit Symbol Description Reset Value 0 CAP0RE Rising edge of capture channel 0 a sequence of 0 then 1 causes CR0 to be loaded with the contents of TC 0 disabled 1 enabled 0 1 CAP0FE Falling edge of capture channel 0 a sequence of 1 then 0 causes CR0 to be loaded with the contents of TC 0 disabled 1 enabled 0 2 CAP0I Generate interrupt on channel 0 capture event a CR0 load generates an interrupt ...

Page 213: ...match pins In the descriptions below n represents the timer number 0 or 1 and m represent a Match number 0 through 3 Match events for Match 0 and Match 1 in each timer can cause a DMA request see Section 14 8 2 If the match outputs are configured as PWM output the function of the external match registers is determined by the PWM rules Section 14 8 1 Rules for single edge controlled PWM outputs on ...

Page 214: ...n a match occurs between the TC and MR3 this bit can either toggle go LOW go HIGH or do nothing as selected by MR 11 10 This bit is driven to the MAT pins if the match function is selected via IOCON 0 LOW 1 HIGH 0 5 4 EMC0 External Match Control 0 Determines the functionality of External Match 0 00 0x0 Do Nothing 0x1 Clear Clear the corresponding External Match bit output to 0 MAT0 pin is LOW if p...

Page 215: ...n the same CAP input in this case cannot be shorter than 1 PCLK Bits 7 4 of this register are also used to enable and configure the capture clears timer feature This feature allows for a designated edge on a particular CAP input to reset the timer to all zeros Using this mechanism to clear the timer on the leading edge of an input pulse and performing a capture on the trailing edge permits direct ...

Page 216: ... for the other 3 CAPn inputs in the same timer 0 0x0 Channel 0 CAPn 0 for CT32Bn 0x1 Channel 1 CAPn 1 for CT32Bn 0x2 Channel 2 CAPn 2 for CT32Bn 0x3 Channel 3 CAPn 3 for CT32Bn 4 ENCC Setting this bit to 1 enables clearing of the timer and the prescaler when the capture edge event specified in bits 7 5 occurs 0 7 5 SELCC Edge select When bit 4 is 1 these bits select which capture input edge will c...

Page 217: ...nterrupt indicating that a match occurred is generated CT32B2 0x4000 4000 0x074 1 CT32B3 0x4000 8000 0x074 1 CT32B4 0x4000 C000 0x074 1 Table 264 Address map PWMC register Peripheral Base address Offset Increment Dimension Table 265 PWM Control Register PWMC address offset 0x074 bit description Bit Symbol Value Description Reset value 0 PWMEN0 PWM mode enable for channel0 0 0 Match CT32Bn_MAT0 is ...

Page 218: ...then the PWM output will be reset to LOW on the next clock tick after the timer reaches the match value Therefore the PWM output will always consist of a one clock tick wide positive pulse with a period determined by the PWM cycle length i e the timer reload value 5 If a match register is set to zero then the PWM output will go to HIGH the first time the timer goes back to zero and will stay HIGH ...

Page 219: ...troller must be configured correctly When a timer is initially set up to generate a DMA request the request may already be asserted before a match condition occurs An initial DMA request may be avoided by having software write a one to the interrupt flag location as if clearing a timer interrupt See Section 14 7 1 A DMA request will be cleared automatically when it is acted upon by the DMA control...

Page 220: ...ernal fixed pre scaler Selectable time period from 1 024 watchdog clocks TWDCLK 256 4 to over 67 million watchdog clocks TWDCLK 224 4 in increments of 4 watchdog clocks Safe watchdog operation Once enabled requires a hardware reset or a Watchdog reset to be disabled Incorrect feed sequence causes immediate watchdog event if enabled The watchdog reload value can optionally be protected such that it...

Page 221: ...watchdog feed is also treated as a watchdog event This allows preventing situations where a system failure may still feed the watchdog For example application code could be stuck in an interrupt service that contains a watchdog feed Setting the window such that this would result in an early feed will generate a watchdog event allowing for system recovery The Watchdog consists of a fixed divide by ...

Page 222: ...nter reaches zero the CPU will be reset loading the stack pointer and program counter from the vector table as for an external reset The Watchdog time out flag WDTOF can be examined to determine if the Watchdog has caused the reset condition The WDTOF flag must be cleared by software When the Watchdog Timer is configured to generate a warning interrupt the interrupt will occur when the counter mat...

Page 223: ...CPU can read the TV register Remark Because of the synchronization step software must add a delay of three WDCLK clock cycles between the feed sequence and the time the WDPROTECT bit is enabled in the MOD register The length of the delay depends on the selected watchdog clock WDCLK 15 5 3 Using the WWDT lock features The WWDT supports several lock features which can be enabled to ensure that the W...

Page 224: ...followed by 0x55 to this register reloads the Watchdog timer with the value contained in the TC register NA Table 270 TV RO 0x00C Watchdog timer value register This 24 bit register reads out the current value of the Watchdog timer 0xFF Table 271 0x010 Reserved WARNINT R W 0x014 Watchdog Warning Interrupt compare value 0 Table 272 WINDOW R W 0x018 Watchdog Window compare value 0xFF FFFF Table 273 T...

Page 225: ...able 75 Start enable register 0 STARTER0 address 0x4000 0240 bit description 4 WDPROTECT Watchdog update mode This bit can be set once by software and is only cleared by a reset 0 0 Flexible The watchdog time out value TC can be changed at any time 1 Threshold The watchdog time out value TC can be changed only after the counter is below the value of WDWARNINT and WDWINDOW 5 LOCK Once this bit is s...

Page 226: ...es an immediate reset interrupt when the Watchdog is enabled and sets the WDTOF flag The reset will be generated during the second PCLK following an incorrect access to a Watchdog register during a feed sequence It is good practice to disable interrupts around a feed sequence if the application is such that an interrupt might result in rescheduling processor control away from the current task in t...

Page 227: ... maximum time of 1 023 watchdog timer counts 4 096 watchdog clocks for the interrupt to occur prior to a watchdog event If WARNINT is 0 the interrupt will occur at the same time as the watchdog event 15 6 6 Watchdog Timer Window register The WINDOW register determines the highest TV value allowed when a watchdog feed is performed If a feed sequence occurs when TV is greater than the value in WINDO...

Page 228: ...WDT 15 7 Functional description The following figures illustrate several aspects of Watchdog Timer operation Fig 35 Early watchdog feed with windowed mode enabled DWFKGRJ RXQWHU DUO HHG YHQW DWFKGRJ 5HVHW RQGLWLRQV 1 2 51 17 7 Fig 36 Correct watchdog feed with windowed mode enabled RUUHFW HHG YHQW DWFKGRJ RXQWHU DWFKGRJ 5HVHW RQGLWLRQV 1 2 51 17 7 Fig 37 Watchdog warning interrupt DWFKGRJ QWHUUXSW...

Page 229: ...are reset use the RTC CTRL register See Table 276 The RTC is reset only by initial power up of the device or when an RTC software reset is applied it is not initialized by other system resets The RTC provides an interrupt to NVIC slot 29 for the RTC_WAKE and RTC_ALARM functions To enable the RTC interrupts for waking up from Deep sleep and Power down modes enable the interrupts in the STARTER0 reg...

Page 230: ...ake up the part from any low power mode if enabled 2 The high resolution wake up timer This 16 bit timer uses a 1 kHz clock and operates as a one shot down timer Once the timer is loaded it starts counting down to 0 at which point an interrupt is raised The interrupt can wake up the part from any low power mode if enabled This timer is intended to be used for timed wake up from Deep sleep power do...

Page 231: ...fforded by the main RTC counter For these applications a higher frequency secondary timer has been provided This secondary timer is an independent stand alone wake up or general purpose timer for timing intervals of up to 64 seconds with approximately one millisecond of resolution The High Resolution Wake up Timer is a 16 bit down counter which is clocked at a 1 kHz rate when it is enabled Writing...

Page 232: ...tware reset control 1 0 Not in reset The RTC is not held in reset This bit must be cleared prior to configuring or initiating any operation of the RTC 1 In reset The RTC is held in reset All register bits within the RTC will be forced to their reset value except the OFD bit This bit must be cleared before writing to any register in the RTC including writes to set any of the other bits within this ...

Page 233: ...n and the RTC operation is disabled This bit should be 0 when writing to load a value in the RTC counter register 1 Enable The 1 Hz RTC clock is running and RTC operation is enabled This bit must be set to initiate operation of the RTC The first clock to the RTC counter occurs 1 s after this bit is set To also enable the high resolution 1 kHz clock set bit 6 in this register 31 8 Reserved Read val...

Page 234: ...ution wake up register Table 279 RTC high resolution wake up register WAKE address 0x4003 C00C bit description Bit Symbol Description Reset value 15 0 VAL A read reflects the current value of the high resolution wake up timer A write pre loads a start count value into the wake up timer and initializes a count down sequence Do not write to this register while counting is in progress 0 31 16 Reserve...

Page 235: ...the register interface Clear the MRT reset using the PRESETCTRL1 register Table 36 The global MRT interrupt is connected to an interrupt slot in the NVIC see Table 2 17 4 Pin description The MRT is not associated with any device pins 17 5 General description The Multi Rate Timer MRT provides a repetitive interrupt timer with four channels Each channel can be programmed with an independent time int...

Page 236: ...lue Change the interval value on the fly immediately by writing a new value 0 to the INTVALn register and setting the LOAD bit to 1 The timer immediately starts to count down from the new timer interval value An interrupt is generated when the timer reaches 0 Stop the timer at the end of time interval by writing a 0 to the INTVALn register and setting the LOAD bit to 0 An interrupt is generated wh...

Page 237: ... when the delay needed is less than the time it takes to get to an interrupt service routine This mode is designed for very low software overhead requiring only a single write to the INTVAL register if the channel is already configured for one shot stall mode The MRT times the requested delay while stalling the bus write operation concluding the write when the delay is complete No interrupt or sta...

Page 238: ...x18 MRT1 Control register This register controls the MRT1 modes 0 Table 283 STAT1 R W 0x1C MRT1 Status register 0 Table 284 MRT Timer 2 registers INTVAL2 R W 0x20 MRT2 Time interval value register This value is loaded into the TIMER2 register 0 Table 281 TIMER2 R W 0x24 MRT2 Timer register This register reads the value of the down counter 0xFF FFFF Table 282 CTRL2 R W 0x28 MRT2 Control register Th...

Page 239: ...s immediately If LOAD 0 the timer stops at the end of the time interval 0 30 24 Reserved Read value is undefined only zero should be written 31 LOAD Determines how the timer interval value IVALUE 1 is loaded into the TIMERn register This bit is write only Reading this bit always returns 0 0 0 No force load The load from the INTVALn register to the TIMERn register is processed at the end of the tim...

Page 240: ...t stall mode 0x3 Reserved 31 3 Reserved 0 Table 284 Status register STAT 0 3 address 0x4007 400C STAT0 to 0x4007 403C STAT3 bit description Bit Symbol Value Description Reset value 0 INTFLAG Monitors the interrupt flag 0 0 No pending interrupt Writing a zero is equivalent to no operation 1 Pending interrupt The interrupt is pending because TIMERn has reached the end of the time interval If the INT...

Page 241: ...ed for further use When IDLE_CH is read returning a channel number of an idle channel the INUSE flag for that channel is set by hardware That channel will not be considered idle until its RUN flag 0 there is no interrupt pending and its INUSE flag 0 This allows reserving an MRT channel with a single register read and no need to start the channel before it is no longer considered idle by IDLE_CH It...

Page 242: ...ss 0x4007 40F8 bit description Bit Symbol Value Description Reset value 0 GFLAG0 Monitors the interrupt flag of TIMER0 0 0 No pending interrupt Writing a zero is equivalent to no operation 1 Pending interrupt The interrupt is pending because TIMER0 has reached the end of the time interval If the INTEN bit in the CONTROL0 register is also set to 1 the interrupt for timer channel 0 and the global in...

Page 243: ... interrupt 48 bit compare value 48 bit compare mask An interrupt is generated when the counter value equals the compare value after masking This allows for combinations not possible with a simple compare 18 4 General description The Repetitive Interrupt Timer RIT provides a versatile means of generating interrupts at specified time intervals without using a standard timer It is intended for repeat...

Page 244: ...ctors UM10850 Chapter 18 LPC5410x Repetitive Interrupt Timer RIT Fig 40 Repetitive Interrupt Timer RI Timer block diagram ELW 2817 5 5 1 203 5 725 6 7 6 7 6 5 4 4 1 B7 0 5 1 B 5 5 175 3 86 3 86 3 86 5 6 7 5 6 7 5 6 7 6 7B 17 3 86 ZULWH WR FOHDU 3 86 3 86 5 5 6 7 17B 1 75 UHJLVWHU 5 5 6 7 1 B 203 5 203 5 B UHJLVWHUV 0 6 0 6 B UHJLVWHUV ELW 0 6 ELW 0 6 B ELW FRPSDUH ELW FRPSDUH ...

Page 245: ... value 0x0000 FFFF Table 289 MASK_H R W 0x014 Mask MSB register This register holds the 16 MSBs of the mask value A 1 written to any bit will force a compare on the corresponding bit of the counter and compare register 0 Table 290 COUNTER_H R W 0x01C Counter MSB register 16 MSBs of the counter 0 Table 292 Table 289 RI Compare Value LSB register COMPVAL address 0x4007 0000 bit description Bit Symbo...

Page 246: ...ble 291 RI Control register CTRL address 0x4007 0008 bit description Bit Symbol Value Description Reset value Table 292 RI Counter register COUNTER address 0x4007 000C bit description Bit Symbol Description Reset value 31 0 RICOUNTER 32 LSBs of the up counter Counts continuously unless RITEN bit in CTRL register is cleared or debug mode is entered if enabled by the RITNEBR bit in RICTRL Can be loa...

Page 247: ...FF FFFF FFFF it rolls over to 0 on the next clock and continues counting If the RITENCLR bit is set to 1 a valid comparison will also cause the counter to be reset to zero Counting will resume from there on the next clock edge Counting can be halted in software by writing a 0 to the RITEN bit Counting will also be halted when the processor is halted for debugging provided the RITENBR bit is set Bo...

Page 248: ... using the following registers 1 Pins The system tick timer uses no external pins 2 Power The system tick timer is enabled through the SysTick control register The system tick timer clock is fixed to half the frequency of the system clock 3 Enable the clock source for the SysTick timer in the SYST_CSR register 19 3 Features Simple 24 bit timer Uses dedicated exception vector Clocked internally by ...

Page 249: ... The SysTick timer can be used for An RTOS tick timer which fires at a programmable rate for example 100 Hz and invokes a SysTick routine A high speed alarm timer using the core clock A simple counter Software can use this to measure time to completion and time used An internal clock source control based on missing meeting durations The COUNTFLAG bit field in the control and status register can be...

Page 250: ...0x014 System Timer Reload value register 0 Table 298 SYST_CVR R W 0x018 System Timer Current value register 0 Table 299 SYST_CALIB RO 0x01C System Timer Calibration value register 0 Table 300 Table 297 SysTick Timer Control and status register SYST_CSR 0xE000 E010 bit description Bit Symbol Description Reset value 0 ENABLE System Tick counter enable When 1 the counter is enabled When 0 the counter...

Page 251: ...ter Writing any value clears the System Tick counter and the COUNTFLAG bit in STCTRL 0 31 24 Reserved Read value is undefined only zero should be written NA Table 300 System Timer Calibration value register SYST_CALIB 0xE000 E01C bit description Bit Symbol Value Description Reset value 23 0 TENMS Reload value from the SYSTCKCAL register in the SYSCON block This field is loaded from the SYSTCKCAL r...

Page 252: ...AD value rather than an arbitrary value when the timer is enabled The following examples illustrate selecting SysTick timer reload values for different system configurations All of the examples calculate an interrupt interval of 10 milliseconds as the SysTick timer is intended to be used and there are no rounding errors System clock 72 MHz Program the CTRL register with the value 0x7 which selects...

Page 253: ...ister interface The Micro Tick Timer provides an interrupt to the NVIC connected to slot 9 To enable Micro Tick Timer interrupts for waking up from Deep sleep and Power down modes enable the interrupts in the STARTER0 register Table 75 and the NVIC The Micro Tick Timer has no external pins Enable the Watchdog oscillator that provides the Micro Tick Timer clock in the syscon block via the Power API...

Page 254: ...s for the Micro tick timer Table 301 Register overview Micro Tick Timer base address 0x4002 0000 Name Access Address Offset Description Reset value Reference CTRL R W 0x00 Control register 0 Table 302 STAT R W 0x04 Status register 0 Table 303 Table 302 Control register CTRL address offset 0x00 bit description Bit Symbol Description Reset value 30 0 DELAYVAL Tick interval value The delay will be eq...

Page 255: ...detect Transmit Disable control and any GPIO as an RTS output Received data and status can optionally be read from a single register Break generation and detection Receive data is 2 of 3 sample voting Status flag set when one sample differs Built in Baud Rate Generator with auto baud function A fractional rate divider is shared among all USARTs Interrupts available for Receiver Ready Transmitter R...

Page 256: ... peripheral clock and the fractional divider for the baud rate calculation are set up in the SYSCON block as follows see Figure 43 1 The Asynchronous APB clock must be configured via the ASYNCCLKDIV register if it has not already been set up See Section 4 5 54 through Section 4 5 59 2 If a fractional value is needed to obtain a particular baud rate program the fractional rate divider FRG controlle...

Page 257: ...ous slave mode the USART block can create an interrupt on a received signal even when the USART block receives no on chip clocks that is in Deep sleep or Power down mode As long as the USART receives a clock signal from the master it can receive up to one byte in the RXDAT register while in Deep sleep or Power down mode Any interrupt raised as part of the receive data process can then wake up the ...

Page 258: ...USART interrupt in the STARTER1 register See Table 75 Start enable register 0 STARTER0 address 0x4000 0240 bit description Enable the USART interrupt in the NVIC The USART wakes up the part from Deep sleep or Power down mode on all events that cause an interrupt and areal so enabled in the INTENSET register Typical wake up events are A start bit has been received The RXDAT buffer has received a by...

Page 259: ... register and when configured to appear on a device pin When deasserted high by the external device the USART will complete transmitting any character already in progress then stop until CTS is again asserted low U0_SCLK I O Serial clock input output for USART0 in synchronous mode Clock input or output in synchronous mode U1_TXD O Transmitter output for USART1 Serial transmit data U1_RXD I Receive...

Page 260: ... The 32 kHz operating mode generates a specially timed internal clock based on the RTC oscillator frequency In synchronous slave mode data is transmitted and received using the serial clock directly In synchronous master mode data is transmitted and received using the baud rate clock without division Status information from the transmitter and receiver is saved and provided via the STAT register M...

Page 261: ...10x USARTs USART0 1 2 3 Fig 44 USART block diagram 7UDQVPLWWHU 6KLIW 5HJLVWHU 7UDQVPLWWHU ROGLQJ 5HJLVWHU 7UDQVPLWWHU 5HFHLYHU 6KLIW 5HJLVWHU 5HFHLYHU 7 5 6 6 287 6 1 5HFHLYHU XIIHU 5HJLVWHU 76 576 86 57 EORFN 86 57 LQWHUUXSW FORFNV 5 0 UHTXHVW 7 0 UHTXHVW DXG 5DWH DQG ORFN HQHUDWLRQ 2YHUVDPSOH FRQWURO XWREDXG QWHUUXSW JHQHUDWLRQ 6WDWXV GGUHVV GHWHFWLRQ ORZ RQWURO UHDN 3DULW JHQHUDWLRQ GHWHFWLRQ 5...

Page 262: ...0x0C Interrupt Enable read and Set register Contains an individual interrupt enable bit for each potential USART interrupt A complete value may be read from this register Writing a 1 to any implemented bit position causes that bit to be set 0 Table 310 INTENCLR WO 0x10 Interrupt Enable Clear register Allows clearing any combination of bits in the INTENSET register Writing a 1 to any implemented bi...

Page 263: ... unchanged For instance when re enabled the USART will immediately generate a TxRdy interrupt if enabled in the INTENSET register or a DMA transfer request because the transmitter has been reset and is therefore available 1 Enabled The USART is enabled for operation 1 Reserved Read value is undefined only zero should be written NA 3 2 DATALEN Selects the data size for the USART 00 0x0 7 bit Data l...

Page 264: ...0 Normal operation 1 Loopback mode This provides a mechanism to perform diagnostic loopback testing for USART data Serial data from the transmitter Un_TXD is connected internally to serial input of the receive Un_RXD Un_TXD and Un_RTS activity will also appear on external pins if these functions are configured to appear on device pins The receiver RTS signal is also looped back to CTS and performs...

Page 265: ...is not inverted and the stop bit is 1 1 Inverted The RX signal is inverted before being used by the USART This means that the RX rest value is 0 start bit is 1 data is inverted and the stop bit is 0 23 TXPOL Transmit data polarity 0 0 Standard The TX signal is sent out without change This means that the TX rest value is 1 start bit is 0 data is not inverted and the stop bit is 1 1 Inverted The TX ...

Page 266: ...DDRDET bit is cleared by software and further incoming data is handled normally 5 3 Reserved Read value is undefined only zero should be written NA 6 TXDIS Transmit Disable 0 0 Not disabled USART transmitter is not disabled 1 Disabled USART transmitter is disabled after any character currently being transmitted is complete This feature can be used to facilitate software flow control 7 Reserved Rea...

Page 267: ...t the transmitter is not currently in the process of sending data 1 RO 4 CTS This bit reflects the current state of the CTS signal regardless of the setting of the CTSEN bit in the CFG register This will be the value of the CTS input pin unless loopback mode is enabled NA RO 5 DELTACTS This bit is set when a change in the state is detected for the CTS flag above This bit is cleared by software 0 W...

Page 268: ...Read value is undefined only zero should be written NA NA Table 309 USART Status register STAT offset 0x08 bit description Bit Symbol Description Reset value Access 1 Table 310 USART Interrupt Enable read and set register INTENSET offset 0x0C bit description Bit Symbol Description Reset Value 0 RXRDYEN When 1 enables an interrupt when there is a received character available to be read from the RXD...

Page 269: ...ritten NA 2 TXRDYCLR Writing 1 clears the corresponding bit in the INTENSET register 0 3 TXIDLECLR Writing 1 clears the corresponding bit in the INTENSET register 0 4 Reserved Read value is undefined only zero should be written NA 5 DELTACTSCLR Writing 1 clears the corresponding bit in the INTENSET register 0 6 TXDISCLR Writing 1 clears the corresponding bit in the INTENSET register 0 7 Reserved R...

Page 270: ... Value 8 0 RXDATA The USART Receiver Data register contains the next received character The number of bits that are relevant depends on the USART configuration settings 0 12 9 Reserved the value read from a reserved bit is not defined NA 13 FRAMERR Framing Error status flag This bit is valid when there is a character to be read in the RXDAT register and reflects the status of that character This b...

Page 271: ...ote that in 32 kHz mode the baud rate generator is still used and must be set to 0 if 9600 baud is required For more information on USART clocking see Section 21 7 1 and Section 21 3 1 Remark In order to change a baud rate after a USART is running the following sequence should be used 1 Make sure the USART is not currently sending or receiving data 2 Disable the USART by writing a 0 to the Enable ...

Page 272: ...t description Bit Symbol Description Reset Value 0 RXRDY Receiver Ready flag 0 1 Reserved Read value is undefined only zero should be written NA 2 TXRDY Transmitter Ready flag 1 3 TXIDLE Transmitter Idle status 0 4 Reserved Read value is undefined only zero should be written NA 5 DELTACTS This bit is set when a change in the state of the CTS input is detected 0 6 TXDISINT Transmitter Disabled Inte...

Page 273: ...R register holds the address for hardware address matching in address detect mode with automatic address matching enabled Table 318 Address register ADDR offset 0x2C bit description Bit Symbol Description Reset value 7 0 ADDRESS 8 bit address used with automatic address matching Used when address detection is enabled ADDRDET in CTL 1 and automatic address matching is enabled AUTOADDR in CFG 1 0 31...

Page 274: ...e range of 1 to 255 This allows producing an output clock that ranges from the input clock divided by 1 1 256 to 1 255 256 just more than 1 to just less than 2 Any further division can be done specific to each USART block by the integer BRG divider contained in each USART The base clock produced by the FRG cannot be perfectly symmetrical so the FRG distributes the output clocks as evenly as is pra...

Page 275: ...eceiver DMA request is asserted when received data is available to be read When DMA is used to perform USART data transfers other mechanisms can be used to generate interrupts when needed For instance completion of the configured DMA transfer can generate an interrupt from the DMA controller Also interrupts for special conditions such as a received break can still generate useful interrupts 21 7 3...

Page 276: ...ampling configuration The result is that a value is stored in the BRG register that is as close as possible to the correct setting for the sampled character and the current clocking settings The sampled character is provided in the RXDAT and RXDATSTAT registers allowing software to double check for the expected character Autobaud includes a time out that is flagged by ABERR if no character is rece...

Page 277: ...hree data samples taken then one more oversample clock before the end of the bit time Since the oversample clock is running asynchronously from the input data skew of the input data relative to the expected timing has little room for error At 16x oversampling there are several oversample clocks before actual data sampling is done making the sampling more robust Generally speaking it is recommended...

Page 278: ...a LIN sync byte and will return the value of the sync byte as confirmation of success Wake up for LIN can potentially be handled in a number of ways depending on the system and what clocks may be running in a slave device For instance as long as the USART is receiving internal clocks allowing it to function it can be set to wake up the CPU for any interrupt including a received start bit If there ...

Page 279: ... Basic configuration If using the SPIs with FIFO support configure the FIFOs seeChapter 24 Configure SPI0 1 using the following registers In the ASYNCAPBCLKCTRL register set bit 9 10 Table 94 to enable the clock to the register interface Clear the SPI0 1 peripheral resets using the ASYNCPRESETCTRL register Table 90 Enable disable the SPI0 1 interrupts in interrupt slots 24 25 in the NVIC Configure...

Page 280: ...rom Sleep mode Configure the SPI in either master or slave mode See Table 322 Enable the SPI interrupt in the NVIC Any SPI interrupt wakes up the part from sleep mode Enable the SPI interrupt in the INTENSET register Table 325 22 3 1 2 Wake up from Deep sleep or Power down mode Configure the SPI in slave mode See Table 322 The SCK function must be connected to a pin and the pin connected to the ma...

Page 281: ...al When the SPI is a slave serial data is output to this signal MISO is driven when the SPI block is enabled the Master bit in CFG equals 0 and when the slave is selected by one or more SSEL signals SPI0_SSEL0 I O Slave Select 0 When the SPI interface is a master it will drive the SSEL signals to an active state before the start of serial data and then release them to an inactive state after the s...

Page 282: ...s type D Same as type D General comment A good choice for SPI input or output A reasonable choice for SPI input or output Not recommended for SPI functions that can be outputs in the chosen mode Table 320 Suggested SPI pin settings IOCON bit s Type D pin Type A pin Type I pin 1 Includes CPOL CPHA LSBF LEN master enable transfer_delay frame_delay pre_delay post_delay SOT EOT EOF RXIGNORE individual...

Page 283: ...ster 0 Table 322 DLY R W 0x04 SPI Delay register 0 Table 323 STAT R W 0x08 SPI Status Some status flags can be cleared by writing a 1 to that bit position 0x0102 Table 324 INTENSET R W 0x0C SPI Interrupt Enable read and Set A complete value may be read from this register Writing a 1 to any implemented bit position causes that bit to be set 0 Table 325 INTENCLR WO 0x10 SPI Interrupt Enable Clear Wr...

Page 284: ...L Clock Polarity select 0 0 Low The rest state of the clock between transfers is low 1 High The rest state of the clock between transfers is high 6 Reserved Read value is undefined only zero should be written NA 7 LOOP Loopback mode enable Loopback mode applies only to Master mode and connects transmit and receive data connected together to allow simple software testing 0 0 Disabled 1 Enabled 8 SP...

Page 285: ... is inserted 0x1 1 SPI clock time is inserted 0x2 2 SPI clock times are inserted 0xF 15 SPI clock times are inserted 0 7 4 POST_ DELAY Controls the amount of time between the end of a data transfer and SSEL deassertion 0x0 No additional time is inserted 0x1 1 SPI clock time is inserted 0x2 2 SPI clock times are inserted 0xF 15 SPI clock times are inserted 0 11 8 FRAME_ DELAY If the EOF flag is set...

Page 286: ...ined if RxOv is set 0 W1 3 TXUR Transmitter Underrun interrupt flag This flag applies only to slave mode Master 0 In this case the transmitter must begin sending new data on the next input clock if the transmitter is idle If that data is not available in the transmitter holding register at that point there is no data to transmit and the TXUR flag is set Data transmitted by the SPI should be consid...

Page 287: ...ten to TXDAT 2 RXOVEN RX overrun interrupt enable Determines whether an interrupt occurs when a receiver overrun occurs This happens in slave mode when there is a need for the receiver to move newly received data to the RXDAT register when it is already in use The interface prevents receiver overrun in Master mode by not allowing a new transmission to begin when a receiver overrun would otherwise ...

Page 288: ...d Set register INTENSET offset 0x0C bit description Bit Symbol Value Description Reset value Table 326 SPI Interrupt Enable clear register INTENCLR offset 0x10 bit description Bit Symbol Description Reset value 0 RXRDYEN Writing 1 clears the corresponding bit in the INTENSET register 0 1 TXRDYEN Writing 1 clears the corresponding bit in the INTENSET register 0 2 RXOVEN Writing 1 clears the corresp...

Page 289: ...efined 17 RXSSEL1_N Slave Select for receive This field allows the state of the SSEL1 pin to be saved along with received data The value will reflect the SSEL1 pin for both master and slave operation A zero indicates that a slave select is active The actual polarity of each slave select pin is configured by the related SPOL bit in CFG undefined 18 RXSSEL2_N Slave Select for receive This field allo...

Page 290: ... upper part of TXDATCTL bits 27 to 16 are the same bits contained in the TXCTL register The two registers simply provide two ways to access them For details on the slave select process see Section 22 7 4 For details on using multiple consecutive data transmits for transfer lengths larger than 16 bit see Section 22 7 6 Data lengths greater than 16 bits Remark If the SPI is used with FIFO support do...

Page 291: ...f a frame 1 Data EOF This piece of data is treated as the end of a frame causing the FRAME_DELAY time to be inserted before subsequent data is transmitted 22 RXIGNORE Receive Ignore This allows data to be transmitted using the SPI without the need to read unneeded data from the receiver The SPI collects receive data according to SPI clocking unless RXIGNORE is set Setting this bit simplifies the t...

Page 292: ...s data is later written to the TXDAT register Data written to TXDATCTL overwrites the TXCTL register When control information needs to be changed during transmission the TXDATCTL register should be used see Section 22 6 7 instead of TXDAT Control information can then be written along with data Table 329 SPI Transmitter Data Register TXDAT offset 0x1C bit description Bit Symbol Description Reset va...

Page 293: ...x24 bit description Bit Symbol Description Reset Value 15 0 DIVVAL Rate divider value Specifies how the PCLK for the SPI is divided to produce the SPI clock rate in master mode DIVVAL is 1 encoded such that the value 0 results in PCLK 1 the value 1 results in PCLK 2 up to the maximum possible divide value of 0xFFFF which results in PCLK 65536 0 31 16 Reserved Read value is undefined only zero shou...

Page 294: ...Section 22 6 1 Table 333 SPI mode summary CPOL CPHA SPI Mode Description SCKrest state SCK data change edge SCK data sample edge 0 0 0 The SPI captures serial data on the first clock transition of the transfer when the clock changes away from the rest state Data is changed on the following edge low falling rising 0 1 1 The SPI changes serial data on the first clock transition of the transfer when ...

Page 295: ... frames when SSEL is not deasserted Transfer_delay minimum duration of SSEL in the deasserted state between transfers 22 7 2 1 Pre_delay and Post_delay Pre_delay and Post_delay are illustrated by the examples in Figure 48 The Pre_delay value controls the amount of time between SSEL being asserted and the beginning of the subsequent data frame The Post_delay value controls the amount of time betwee...

Page 296: ...ay is inserted when the EOF bit 1 Frame_delay is illustrated by the examples in Figure 49 Note that frame boundaries occur only where specified This is because frame lengths can be any size involving multiple data writes See Section 22 7 6 for more information Fig 49 Frame_delay UDPH GHOD 3 UDPHBGHOD 3UHBGHOD 3RVWBGHOD 0RGH 32 6 UDPHBGHOD 0RGH 32 6 06 6 06 6 0 62 026 66 06 06 6HFRQG GDWD IUDPH 6 6...

Page 297: ...mount of time that SSEL is deasserted between transfers because the EOT bit 1 When Transfer_delay 0 SSEL may be deasserted for a minimum of one SPI clock time Transfer_delay is illustrated by the examples in Figure 50 Fig 50 Transfer_delay 6 32 7UDQVIHU BGHOD 6 32 06 6 06 6 0 62 026 66 06 6 06 6 0 62 026 66 6 32 6 32 06 06 6 6 LUVW GDWD IUDPH 6HFRQG GDWD IUDPH LUVW GDWD IUDPH 6 06 6 6HFRQG GDWD IU...

Page 298: ...et to run at the same speed as the selected PCLK or at lower integer divide rates The SPI rate will be PCLK_SPIn DIVVAL In slave mode the clock is taken from the SCK input and the SPI clock divider is not used 22 7 4 Slave select The SPI block provides for four Slave Select inputs in slave mode or outputs in master mode Each SSEL can be set for normal polarity active low or can be inverted active ...

Page 299: ...smitted 2 Another way is through the SPI Tx DMA interrupt handler This interrupt handler can set the SPI Status register STAT END TRANSFER control bit at the completion of the DMA transfer 3 A third way is to use the DMA controller s linked descriptor capability The DMA controller provides for a linked list of DMA transfer control descriptors The initial descriptor s can be used to transfer most o...

Page 300: ... transmitter stall will not happen in modes 1 and 3 because the transmitted data is complete at the point where a stall would otherwise occur so it is not needed Stalls are reflected in the STAT register by the Stalled status flag which indicates the current SPI status The transmitter will be stalled until data is read from the receive FIFO Use the RXIGNORE control bit setting to avoid the need to...

Page 301: ...ports both Multi master and Multi master with Slave functions Multiple I2C slave addresses supported in hardware One slave address can be selectively qualified with a bit mask or an address range in order to respond to multiple I2C bus addresses 10 bit addressing supported with software assist Supports System Management Bus SMBus Separate DMA requests for Master Slave and Monitor functions No chip...

Page 302: ...o 30 MHz and the bit rate is approximately 400 KHz The I2C0_SCL and I2C0_SDA functions must be enabled on pins PIO0_22 and PIO0_23 through IOCON See Section 7 5 2 The pins should be configured as required for the I2C bus mode that will be used SM FM FM HS via the IOCON block See Section 7 5 2 The transmission of the address and data bits is controlled by the state of the MSTPENDING status bit When...

Page 303: ... data by setting the MSTCONT bit to 1 in the Master control register See Table 358 The following happens The pending status is cleared and the I2C bus is busy The I2C master sends the data bits to the slave address 6 Wait for the pending status to be set MSTPENDING 1 by polling the STAT register 7 Stop the transmission by setting the MSTSTOP bit to 1 in the Master control register See Table 358 Ta...

Page 304: ...o the master The system clock is set to 30 MHz and the bit rate is approximately 400 KHz The I2C0_SCL and I2C0_SDA functions must be enabled on pins PIO0_22 and PIO0_23 through IOCON See Section 7 5 2 The pins should be configured as required for the I2C bus mode that will be used SM FM FM HS via the IOCON block See Section 7 5 2 The transmission of the address and data bits is controlled by the s...

Page 305: ...UE 1 in the slave control register See Table 364 3 Wait for the pending status to be set SLVPENDING 1 by polling the STAT register 4 Read 8 bits of data from the SLVDAT register See Table 366 5 Acknowledge ack the data by setting SLVCONTINUE 1 in the slave control register See Table 364 Table 337 Code example Slave read from master Slave read 1 byte from master Address 0x23 Polling mode uint8_t da...

Page 306: ...LK remains active in sleep mode the I2C can wake up the part independently of whether the I2C block is configured in master or slave mode In Deep sleep or Power down mode the I2C clock is turned off as are all peripheral clocks However if the I2C is configured in slave mode and an external master on the I2C bus provides the clock signal the I2C block can create an interrupt asynchronously This int...

Page 307: ...nterrupt signal asynchronously while the core and the peripheral are not clocked See Table 76 Start enable register 1 STARTER1 address 0x4000 0244 bit description Configure the I2C in slave mode Enable the I2C the interrupt in the I2C INTENCLR register which configures the interrupt as wake up event Examples are the following events Slave deselect Slave pending wait for read write or ACK Address m...

Page 308: ...description Table 352 Time out value register TIMEOUT address offset 0x010 bit description Table 354 I2C Clock Divider register CLKDIV offset 0x14 bit description Master function registers Table 358 Master Control register MSTCTL address offset 0x020 bit description Table 360 Master Time register MSTTIME address offset 0x024 bit description Table 362 Master Data register MSTDAT address offset 0x02...

Page 309: ...le 352 CLKDIV R W 0x14 Clock pre divider for the entire I2C block This determines what time increments are used for the MSTTIME register and controls some timing of the Slave function 0 Table 354 INTSTAT RO 0x18 Interrupt Status register for Master Slave and Monitor functions 0 Table 356 MSTCTL R W 0x20 Master control register 0 Table 358 MSTTIME R W 0x24 Master timing configuration 0x56 Table 360...

Page 310: ... are not changed but the Slave function is internally reset 0 0 Disabled The I2C slave function is disabled 1 Enabled The I2C slave function is enabled 2 MONEN Monitor Enable When disabled configurations settings for the Monitor function are not changed but the Monitor function is internally reset 0 0 Disabled The I2C monitor function is disabled 1 Enabled The I2C monitor function is enabled 3 TIM...

Page 311: ...ock will support Standard mode Fast mode and Fast mode Plus to the extent that the pin electronics support these modes Any changes that need to be made to the pin controls such as changing the drive strength or filtering must be made by software via the IOCON register associated with each I2C pin 1 High speed In addition to Standard mode Fast mode and Fast mode Plus the I2C block will support High...

Page 312: ...ion is in progress and the Master function is busy and cannot currently accept a command 1 Pending The Master function needs software service or is in the idle state If the master is not in the idle state it is waiting to receive or transmit data or the NACK bit 3 1 MSTSTATE Master State code The master state code reflects the master state when the MSTPENDING bit is set that is the master is pendi...

Page 313: ...mode See Section 23 7 1 2 2 When the I2C block is configured to be HSCAPABLE HS master codes are detected automatically Due to the requirements of the HS I2C specification slave addresses must also be detected automatically since the address must be acknowledged before the clock can be stretched 0 RO 0 In progress The Slave function does not currently need service 1 Pending The Slave function need...

Page 314: ...urrently selected That information can be found in the SLVSEL flag 1 Deselected The Slave function has become deselected This is specifically caused by the SLVSEL flag changing from 1 to 0 See the description of SLVSEL for details on when that event occurs 16 MONRDY Monitor Ready This flag is cleared when the MONRXDAT register is read 0 RO 0 No data The Monitor function does not currently have dat...

Page 315: ...Table 345 Master function state codes MSTSTATE MST STATE Description Actions DMA allowed 0x0 Idle The Master function is available to be used for a new transaction Send a Start or disable MSTPENDING interrupt if the Master function is not needed currently No 0x1 Received data is available Master Receiver mode Address plus Read was previously sent and Acknowledged by slave Read data and either cont...

Page 316: ...ster Arbitration Loss interrupt Enable 0 0 Disabled The MstArbLoss interrupt is disabled 1 Enabled The MstArbLoss interrupt is enabled 5 Reserved Read value is undefined only zero should be written NA 6 MSTSTSTPERREN Master Start Stop Error interrupt Enable 0 0 Disabled The MstStStpErr interrupt is disabled 1 Enabled The MstStStpErr interrupt is enabled 7 Reserved Read value is undefined only zero...

Page 317: ...et and read register INTENSET address offset 0x008 bit description Bit Symbol Value Description Reset value Table 349 Address map INTENCLR register Peripheral Base address Offset Increment Dimension I2C0 0x4009 4000 0x00C 1 I2C1 0x4009 8000 0x00C 1 I2C2 0x4009 C000 0x00C 1 Table 350 Interrupt Enable Clear register INTENCLR address offset 0x00C bit description Bit Symbol Description Reset value 0 M...

Page 318: ...used with the SMBus Also see Section 23 7 2 Time out 23 20 Reserved Read value is undefined only zero should be written NA 24 EVENTTIMEOUTCLR Event time out interrupt clear 0 25 SCLTIMEOUTCLR SCL time out interrupt clear 0 31 26 Reserved Read value is undefined only zero should be written NA Table 350 Interrupt Enable Clear register INTENCLR address offset 0x00C bit description continued Bit Symbo...

Page 319: ...lags Table 353 Address map CLDIV register Peripheral Base address Offset Increment Dimension I2C0 0x4009 4000 0x014 1 I2C1 0x4009 8000 0x014 1 I2C2 0x4009 C000 0x014 1 Table 354 I2C Clock Divider register CLKDIV offset 0x14 bit description Bit Symbol Description Reset value 15 0 DIVVAL This field controls how the clock PCLK is used by the I2C functions that need an internal clock in order to opera...

Page 320: ...defined only zero should be written NA 15 SLVDESEL Slave Deselected flag 0 16 MONRDY Monitor Ready 0 17 MONOV Monitor Overflow flag 0 18 Reserved Read value is undefined only zero should be written NA 19 MONIDLE Monitor Idle flag 0 23 20 Reserved Read value is undefined only zero should be written NA 24 EVENTTIMEOUT Event time out Interrupt flag 0 25 SCLTIMEOUT SCL time out Interrupt flag 0 31 26 ...

Page 321: ...G flag and the MSTDMA control bit would be cleared by software potentially at the same time as setting either the MSTSTOP or MSTSTART control bit Remark When in the idle or slave NACKed states see Table 345 set the MSTDMA bit either with or after the MSTCONTINUE bit MSTDMA can be cleared at any time Table 357 Address map MSTCTL register Peripheral Base address Offset Increment Dimension I2C0 0x400...

Page 322: ...uld be written NA Table 358 Master Control register MSTCTL address offset 0x020 bit description Bit Symbol Value Description Reset value Table 359 Address map MSTTIME register Peripheral Base address Offset Increment Dimension I2C0 0x4009 4000 0x024 1 I2C1 0x4009 8000 0x024 1 I2C2 0x4009 C000 0x024 1 Table 360 Master Time register MSTTIME address offset 0x024 bit description Bit Symbol Value Descr...

Page 323: ...locks Minimum SCL high time is 4 clock of the I2C clock pre divider 0x3 5 clocks Minimum SCL high time is 5 clock of the I2C clock pre divider 0x4 6 clocks Minimum SCL high time is 6 clock of the I2C clock pre divider 0x5 7 clocks Minimum SCL high time is 7 clock of the I2C clock pre divider 0x6 8 clocks Minimum SCL high time is 8 clock of the I2C clock pre divider 0x7 9 clocks Minimum SCL high ti...

Page 324: ...0x4009 4000 0x010 1 I2C1 0x4009 8000 0x010 1 I2C2 0x4009 C000 0x010 1 Table 364 Slave Control register SLVCTL address offset 0x040 bit description Bit Symbol Value Description Reset Value 0 SLVCONTINUE Slave Continue 0 0 No effect 1 Continue Informs the Slave function to continue to the next operation by clearing the SLVPENDING flag in the STAT register This must be done after writing transmit dat...

Page 325: ...ve Data register SLVDAT address offset 0x044 bit description Bit Symbol Description Reset Value 7 0 DATA Slave function data register Read read the most recently received data for the Slave function Write transmit data using the Slave function 0 31 8 Reserved Read value is undefined only zero should be written NA Table 367 Address map SLVADR 0 3 registers Peripheral Base address Offset Increment D...

Page 326: ...ss 0 1 Extend The SLVQUAL0 field is used to extend address 0 matching in a range of addresses 7 1 SLVQUAL0 Slave address Qualifier for address 0 A value of 0 causes the address in SLVADR0 to be used as is assuming that it is enabled If QUALMODE0 0 any bit in this field which is set to 1 will cause an automatic match of the corresponding bit of the received address when it is compared to the SLVADR...

Page 327: ...e until the end of the next piece of information from the I2C bus Details of clock stretching are different in HS mode see Section 23 7 1 2 2 Table 371 Address map MONRXDAT register Peripheral Base address Offset Increment Dimension I2C0 0x4009 4000 0x080 1 I2C1 0x4009 8000 0x080 1 I2C2 0x4009 C000 0x080 1 Table 372 Monitor data register MONRXDAT address offset 0x080 bit description Bit Symbol Val...

Page 328: ...e rise time of the open drain bus line Rate calculations give a base frequency that represents the fastest that the I2C bus could operate if nothing slows it down 23 7 1 1 Rate calculations Master timing SCL high time in I2C function clocks CLKDIV 1 MSTSCLHIGH 2 SCL low time in I2C function clocks CLKDIV 1 MSTSCLLOW 2 Nominal SCL rate I2C function clock rate SCL high time SCL low time Slave timing...

Page 329: ...e and address recognition and which affect when interrupts occur are always in effect when the I2C is configured to be HS capable This means that software does not need to know if a particular transfer is actually in HS mode or not 23 7 1 2 2 Clock stretching The I2C interface automatically stretches the clock when it does not have sufficient information on how to proceed i e software has not supp...

Page 330: ...ing slaves including masters that can be addressed as slaves do this then the bus will be released unless it is a current master causing the problem Refer to the SMBus specification for more details Both types of time out are generated only when the I2C bus is considered busy i e when there has been a Start condition more recently than a Stop condition 23 7 3 Ten bit addressing Ten bit addressing ...

Page 331: ... for Master Slave and Monitor functions 23 7 6 DMA DMA with the I2C is done only for data transfer DMA cannot handle control of the I2C Once DMA is transferring data I2C acknowledges are handled implicitly No CPU intervention is required while DMA is transferring data Generally data transfers can be handled by DMA for Master mode after an address is sent and acknowledged by a slave and for Slave m...

Page 332: ...ompletes Software causes a stop or repeated start to be sent Software will be invoked to handle any exceptions to the standard transfer 23 7 6 3 DMA as a Slave transmitter A basic sequence for a Slave transmitter Software acknowledges an I2C address Software sets up DMA to transmit a message Software starts DMA DMA completes 23 7 6 4 DMA as a Slave receiver A basic sequence for a Slave receiver So...

Page 333: ...RT and SPI timeout counter to work Enable the watchdog oscillator via the PDRUNCFG register Table 72 24 3 Features Performs transmit and receive FIFO operations for all USARTs and SPIs on a device supporting software or DMA access to each peripheral transmit and receive functions FIFOs provide additional timing elasticity which is extended when they are used in conjunction with DMA Buffer space is...

Page 334: ... rights reserved User manual Rev 2 4 13 September 2016 335 of 464 NXP Semiconductors UM10850 Chapter 24 LPC5410x System FIFO for Serial Peripherals A receiver timeout feature for USART and SPI provides a means to get data left for a time in a FIFO that has not reached its threshold to be transferred ...

Page 335: ...ig 53 System FIFO conceptual block diagram VODYH LQWHUIDFH 9 2 FRQWURO 0 UHTXHVWV IURP SHULSKHUDOV 0 UHTXHVWV WR 0 FRQWUROOHU QWHUUXSWV IURP 9 2 DWD 3DFNLQJ 8QSDFNLQJ 2 0HPRU 7LPHRXW RPSDUH 7LPHRXW 7LPHU 7B26 VODYH LQWHUIDFH Fig 54 FIFO system 3HULSKHUDO 0 UHTXHVWV PDWUL 6 VWHP 2 3 EULGJH V 38 6 VWHP 0 FRQWUROOHU 0 PXOWLSOH LQJ QWHUUXSW FRPELQLQJ QWHUUXSWV WR 38 2 0 UHTXHVWV 3HULSKHUDO LQWHUUXSW U...

Page 336: ...register NA 379 FIFOCFGSPI0 R W 0x0210 FIFO configuration register for SPI0 0 381 FIFOCFGSPI1 R W 0x0214 FIFO configuration register for SPI0 0 381 USART specific registers CFGUSART0 R W 0x1000 USART0 configuration 0 383 STATUSART0 R W 0x1004 USART0 status 0x300 385 INTSTATUSART0 RO 0x1008 USART0 interrupt status 0x300 387 CTLSETUSART0 RO W1 0x100C USART0 control read and set register A complete v...

Page 337: ... 0x1310 USART3 control clear register Writing a 1 to any implemented bit position causes the corresponding bit in the related CTLSET register to be cleared NA 391 RXDATUSART3 RO 0x1314 USART3 received data NA 393 RXDATSTATUSART3 RO 0x1318 USART3 received data with status NA 395 TXDATUSART3 WO 0x131C USART3 transmit data 0 397 SPI specific registers CFGSPI0 R W 0x2000 SPI0 configuration 0 399 STATS...

Page 338: ...include reserved bits content CTLCLRSPI1 W1 0x2110 SPI1 control clear register Writing a 1 to any implemented bit position causes the corresponding bit in the related CTLSET register to be cleared NA 407 RXDATSPI1 RO 0x2114 SPI1 received data These registers are half word addressable NA 409 TXDATCTLSPI1 WO 0x2118 SPI1 transmit data These registers are half word addressable NA 411 Table 373 Registe...

Page 339: ... FIFO allocations among the USART transmitters R W 1 9 TXPAUSED All USART transmit FIFOs are paused RO 1 10 TXEMPTY All USART transmit FIFOs are empty RO 1 15 11 Reserved Read value is undefined only zero should be written NA 23 16 RXFIFOTOTAL Reports the receive FIFO space available for USARTs on this FIFO The reset value is device specific RO 31 24 TXFIFOTOTAL Reports the transmit FIFO space ava...

Page 340: ... UPDATESIZE Writing 1 updates USART2 Tx FIFO size to match the USART2 TXSIZE Must be done for all USARTs when any USART TXSIZE is changed 0 19 USART3TX UPDATESIZE Writing 1 updates USART3 Tx FIFO size to match the USART3 TXSIZE Must be done for all USARTs when any USART TXSIZE is changed 0 31 20 Reserved Read value is undefined only zero should be written NA Table 375 USART FIFO global reset regis...

Page 341: ...written NA 8 TXPAUSE Pause all SPIs transmit FIFO operations This can be used to prepare the System FIFO to reconfigure FIFO allocations among the SPI transmitters R W 1 9 TXPAUSED All SPI transmit FIFOs are paused RO 1 10 TXEMPTY All SPI transmit FIFOs are empty RO 1 15 11 Reserved Read value is undefined only zero should be written NA 23 16 RXFIFOTOTAL Reports the receive FIFO space available fo...

Page 342: ... than the available FIFO space is allocated That is the sum of all FIFO sizes must not exceed the related FIFOTOTAL value in the FIFOCTLSPI register After configuration the FIFOs must be reset See Section 24 6 1 Configuring peripheral FIFOs Table 380 Address map FIFOCFGSPI 0 1 registers Peripheral Base address Offset Increment Dimension VFIFO 0x1C03 8000 0x210 0x214 0x4 2 Table 381 FIFO configurat...

Page 343: ...to accumulated data perhaps related to the FIFO threshold 0 5 TIMEOUT CONT ONEMPTY Timeout Continue On Empty When 0 the timeout for the related peripheral is reset when the receive FIFO becomes empty When 1 the timeout for the related peripheral is not reset when the receive FIFO becomes empty This allows the timeout to be used to flag idle peripherals and could potentially be used to indicate the...

Page 344: ...ceive FIFO threshold has been reached This is a read only bit 0 1 TXTH Transmit FIFO Threshold When 1 the transmit FIFO threshold has been reached This is a read only bit 0 3 2 Reserved Read value is undefined only zero should be written NA 4 RX TIMEOUT Receive FIFO Timeout When 1 the receive FIFO has timed out based on the timeout configuration in the CFGUSART register The timeout condition can b...

Page 345: ...hed and the related interrupt is enabled 0 3 2 Reserved Read value is undefined only zero should be written NA 4 RX TIMEOUT Receive Timeout When 1 the receive FIFO has timed out based on the timeout configuration in the CFGUSART register and the related interrupt is enabled 0 6 5 Reserved Read value is undefined only zero should be written NA 7 BUSERR Bus Error This is simply a copy of the same bi...

Page 346: ...A 8 RXFLUSH Receive FIFO flush Writing a 1 to this bit forces the receive FIFO to be empty 0 9 TXFLUSH Transmit FIFO flush Writing a 1 to this bit forces the transmit FIFO to be empty 0 31 10 Reserved Read value is undefined only zero should be written NA Table 389 Control read and set register for USARTn CTLSETUSART 0 3 address offset 0x100C 0x130C bit description Bit Symbol Description Reset Val...

Page 347: ...t description Bit Symbol Description Reset Value 8 0 RXDAT The UART Receiver Data register contains the next received character The number of bits that are relevant depends on the UART configuration settings 0 12 9 Reserved the value read from a reserved bit is not defined NA 13 FRAMERR Framing Error status flag This bit is valid when there is a character to be read in the RXDAT register and refle...

Page 348: ... timeout for the related peripheral is reset when the receive FIFO becomes empty When 1 the timeout for the related peripheral is not reset when the receive FIFO becomes empty This allows the timeout to be used to flag idle peripherals and could potentially be used to indicate the end of a transmission of indeterminate length 0 7 6 Reserved Read value is undefined only zero should be written NA 11...

Page 349: ... 0 1 registers Peripheral Base address Offset Increment Dimension VFIFO 0x1C03 8000 0x2004 0x2104 0x100 2 Table 401 Status register for SPIn STATSPI 0 1 address offset 0x2004 0x2104 bit description Bit Symbol Description Reset Value 0 RXTH Receive FIFO Threshold When 1 the receive FIFO threshold has been reached This is a read only bit 0 1 TXTH Transmit FIFO Threshold When 1 the transmit FIFO thre...

Page 350: ... TIMEOUT Receive Timeout When 1 the receive FIFO has timed out based on the timeout configuration in the CFGSPI register and the related interrupt is enabled 0 6 5 Reserved Read value is undefined only zero should be written NA 7 BUSERR Bus Error This is simply a copy of the same bit in the STATSPI register The bus error interrupt is always enabled 0 8 RXEMPTY Receive FIFO Empty This is simply a c...

Page 351: ...CTLSETSPI 0 1 address offset 0x200C 0x210C bit description Bit Symbol Description Reset Value Table 406 Address map CTLCLRSPI 0 1 registers Peripheral Base address Offset Increment Dimension VFIFO 0x1C03 8000 0x2010 0x2110 0x100 2 Table 407 Control read and clear register for SPIn CTLCLRSPI 0 1 address offset 0x2010 0x2110 bit description Bit Symbol Description Reset Value 31 0 Writing ones to thi...

Page 352: ...e operation A zero indicates that a slave select is active The actual polarity of each slave select pin is configured by the related SPOL bit in CFG NA 17 RXSSEL1_N Slave Select for receive This field allows the state of the SSEL1 pin to be saved along with received data The value will reflect the SSEL1 pin for both master and slave operation A zero indicates that a slave select is active The actu...

Page 353: ...SSEL2 pin is configured by bits in the CFG register 0 0 Asserted SSEL2 asserted 1 Not asserted SSEL2 not asserted 19 TXSSEL3_N Transmit Slave Select This field asserts SSEL3 in master mode The output on the pin is active LOW by default Remark The active state of the SSEL3 pin is configured by bits in the CFG register 0 0 Asserted SSEL3 asserted 1 Not asserted SSEL3 not asserted 20 EOT End of Trans...

Page 354: ...a is not read before new data is received 1 Ignore received data Received data is ignored allowing transmission without reading unneeded received data No receiver flags are generated 23 Reserved Read value is undefined only zero should be written NA 27 24 LEN Data Length Specifies the data length from 1 to 16 bits Note that transfer lengths greater than 16 bits are supported by implementing multip...

Page 355: ...DMA will respond if it has been configured to support that peripheral channel 24 6 3 Receiving data DMA can be configured to read received data from a peripheral FIFO and generate an interrupt when a transfer is competed An interrupt service routine could read in received data instead of DMA Potentially being aware of the actual threshold for the channel the ISR could always read in that amount of...

Page 356: ...pt service routine could send transmit data instead of DMA An ISR could always send data until the transmit FIFO is full if enough is available When a complete data packet has been written to the transmit FIFO the interrupt could be disabled to prevent further interrupts 24 6 5 Channel Priority Receive requests are given priority over transmit requests in order to minimize potential loss of data A...

Page 357: ...nsmitter Write 0x303 to FIFOCFGUSART0 selecting sizes for the USART0 RX and TX FIFOs Write 0x303 to FIFOCFGUSART1 selecting sizes for the USART1 RX and TX FIFOs Write 0x303 to FIFOCFGUSART2 selecting sizes for the USART2 RX and TX FIFOs Write 0x303 to FIFOCFGUSART3 selecting sizes for the USART3 RX and TX FIFOs Write 0xF 000F to FIFOUPDATEUSART causing the selected USART FIFO sizes to go into effe...

Page 358: ...the ADC API available from NXP or by directly controlling the registers of the ADC Configure the ADC as follows Clear the PDEN_ADC0 bit in the PDRUNCFG register Table 72 in order to enable the analog portion of the ADC Set the ADC0 bit in the AHBCLKCTRL0 register Table 51 to enable the clock to the ADC0 register interface and the ADC0 clock Clear the ADC0 peripheral reset using the PRESETCTRL0 reg...

Page 359: ... the ADC CTRL register to clock ADC conversions Use the system clock to clock the ADC in synchronous mode This option allows exact timing of triggers but requires a system clock of 80 MHz to obtain the full ADC conversion speed Use the ADC clock determined by the ADCCLKSEL register Table 47 and the ADCCLKDIV register Table 59 Some clock sources are independent of the system clock and may require e...

Page 360: ...5 0xFFF Analog Power and Ground should typically be the same voltages as VDD and VSS but should be isolated to minimize noise and error If the ADC is not used VDDA and VREFP should be tied to VDD and VSSA and VREFN should be tied to VSS Recommended IOCON settings are shown in Table 414 Table 412 ADC common supply and reference pins Pin Description VDDA Analog supply voltage VREFP must not exceed t...

Page 361: ...G0 PINT0 ADC0 pin trigger input 0 from Pin Interrupt 0 Select in SEQA_CTRL or SEQB_CTRL register ADC0_PINTRIG1 PINT1 ADC0 pin trigger input 1 from Pin Interrupt 1 Select in SEQA_CTRL or SEQB_CTRL register Table 413 ADC0 pin description Function Connect to Description Table 414 Suggested ADC input pin settings IOCON bit s Type D pin Type A pin Type I pin 10 NA OD Set to 0 NA 9 NA Not used set to 0 ...

Page 362: ...m clock as a bus clock The system clock or the asynchronous ADC clock see Figure 55 can be used to create the ADC clock which drives the successive approximation process In the synchronous operating mode this ADC clock is derived from the system clock In this mode a programmable divider is included to scale the system clock to the maximum ADC clock rate of 80 MHz In the asynchronous mode an indepe...

Page 363: ...ster This register contains the result of the most recent conversion completed on channel 1 NA Table 422 DAT2 RO 0x028 ADC Channel 2 Data Register This register contains the result of the most recent conversion completed on channel 2 NA Table 422 DAT3 RO 0x02C ADC Channel 3 Data Register This register contains the result of the most recent conversion completed on channel 3 NA Table 422 DAT4 RO 0x0...

Page 364: ... threshold comparison for any channels linked to threshold pair 1 0 Table 426 CHAN_ THRSEL R W 0x060 ADC Channel Threshold Select Register Specifies which set of threshold compare registers are to be used for each channel 0 Table 427 INTEN R W 0x064 ADC Interrupt Enable Register This register contains enable bits that enable the sequence A sequence B threshold compare and data overrun interrupts t...

Page 365: ...he launching of an ADC conversion in response to any synchronous on chip trigger In Synchronous mode with the SYNCBYPASS bit in a sequence control register set sampling of the ADC input and start of conversion will initiate 2 system clocks after the leading edge of a synchronous trigger pulse 1 Asynchronous mode The ADC clock is based on the output of the ADC clock divider ADCCLKSEL in the SYSCON ...

Page 366: ...rt of each conversion is 2 5 ADC clock periods Depending on a variety of factors including operating conditions and the output impedance of the analog source longer sampling times may be required See Section 25 7 10 The TSAMP field specifies the number of additional ADC clock cycles from zero to seven by which the sample period will be extended The total conversion time will increase by the same n...

Page 367: ... is recommended writing to this field only when SEQA_ENA bit 31 is low It is safe to change this field and set bit 31 in the same write 0x0 18 TRIGPOL Select the polarity of the selected input trigger for this conversion sequence Remark In order to avoid generating a spurious trigger it is recommended writing to this field only when SEQA_ENA bit 31 is low It is safe to change this field and set bi...

Page 368: ...n sequence is active will be ignored and lost 1 High priority Setting this bit to a 1 will permit any enabled B sequence trigger including a B sequence software start to immediately interrupt sequence A and launch a B sequence in it s place The conversion currently in progress will be terminated The A sequence that was interrupted will automatically resume after the B sequence completes The channe...

Page 369: ...er to avoid spuriously triggering the sequence care should be taken to only set the SEQA_ENA bit when the selected trigger input is in its INACTIVE state as defined by the TRIGPOL bit If this condition is not met the sequence will be triggered immediately upon being enabled 0 0 Disabled Sequence A is disabled Sequence A triggers are ignored If this bit is cleared while sequence A is in progress th...

Page 370: ... to this field only when SEQB_ENA bit 31 is low It is safe to change this field and set bit 31 in the same write 0x0 18 TRIGPOL Select the polarity of the selected input trigger for this conversion sequence Remark In order to avoid generating a spurious trigger it is recommended writing to this field only when SEQB_ENA bit 31 is low It is safe to change this field and set bit 31 in the same write ...

Page 371: ...nce Impacts when conversion complete interrupt DMA trigger for sequence B will be generated and which overrun conditions contribute to an overrun interrupt as described below 0 0 End of conversion The sequence B interrupt DMA trigger will be set at the end of each individual ADC conversion performed under sequence B This flag will mirror the DATAVALID bit in the SEQB_GDAT register The OVERRUN bit ...

Page 372: ...rmed under conversion sequence associated with this register The result is a binary fraction representing the voltage on the currently selected input channel as it falls within the range of VREFP to VREFN Zero in the field indicates that the voltage on the input pin was less than equal to or close to that on VREFN while 0xFFF indicates that the voltage on the input was close to equal to or greater...

Page 373: ...low or within the range established by the designated threshold comparison registers THRn_LOW and THRn_HIGH 19 18 THCMP CROSS Indicates whether the result of the last conversion performed represented a crossing of the threshold level established by the designated LOW threshold comparison register THRn_LOW and if so in what direction the crossing occurred 25 20 Reserved NA 29 26 CHN These bits cont...

Page 374: ...d on that channel regardless of what sequence requested the conversion or which trigger caused it The OVERRUN fields for each channel are also replicated in the FLAGS register Table 421 Address map DAT 0 11 registers Peripheral Base address Offset Increment Dimension ADC 0x1C03 2000 0x020 0x04C 0x4 12 Table 422 ADC Data Registers DAT 0 11 address offset 0x020 0x04C bit description Bit Symbol Descr...

Page 375: ... the DAT0 register 0b0001 for the DAT1 register etc NA 30 OVER RUN This bit will be set to a 1 if a new conversion on this channel completes and overwrites the previous contents of the RESULT field before it has been read i e while the DONE bit is set This bit is cleared along with the DONE bit whenever this register is read or when the data related to this channel is read from either of the globa...

Page 376: ...low this threshold and the other is equal to or above this threshold than a threshold crossing has occurred In this case the MSB of the THCMP_CROSS status bits will indicate that a threshold crossing has occurred and the LSB will indicate the direction of the crossing A threshold crossing event will also generate an interrupt DMA trigger if enabled to do so via the ADCMPINTEN bits associated with ...

Page 377: ... that channel to be set to 0b10 This result will also generate an interrupt DMA trigger if enabled to do so via the ADCMPINTEN bits associated with each channel in the INTEN register Table 425 Compare High Threshold register0 THR0_HIGH address offset 0x58 bit description Bit Symbol Description Reset value 3 0 Reserved Read value is undefined only zero should be written NA 15 4 THRHIGH High thresho...

Page 378: ...the threshold levels indicated in the THR1_LOW and THR1_HIGH registers 1 CH1_THRSEL Threshold select for channel 1 See description for channel 0 0 2 CH2_THRSEL Threshold select for channel 2 See description for channel 0 0 3 CH3_THRSEL Threshold select for channel 3 See description for channel 0 0 4 CH4_THRSEL Threshold select for channel 4 See description for channel 0 0 5 CH5_THRSEL Threshold se...

Page 379: ...e FLAGS register and generate an ADC threshold compare interrupt DMA trigger Remark Overrun and threshold compare interrupts related to a particular channel will occur regardless of which sequence was in progress at the time the conversion was performed or what trigger caused the conversion Table 428 ADC Interrupt Enable register INTEN address offset 0x64 bit description Bit Symbol Value Descripti...

Page 380: ...t enable See description for channel 0 00 14 13 ADCMPINTEN5 Channel 5 threshold comparison interrupt enable See description for channel 0 00 16 15 ADCMPINTEN6 Channel 6 threshold comparison interrupt enable See description for channel 0 00 18 17 ADCMPINTEN7 Channel 7 threshold comparison interrupt enable See description for channel 0 00 20 19 ADCMPINTEN8 Channel 8 threshold comparison interrupt en...

Page 381: ... Channel 5 See description for channel 0 0 6 THCMP6 Threshold comparison event on Channel 6 See description for channel 0 0 7 THCMP7 Threshold comparison event on Channel 7 See description for channel 0 0 8 THCMP8 Threshold comparison event on Channel 8 See description for channel 0 0 9 THCMP9 Threshold comparison event on Channel 9 See description for channel 0 0 10 THCMP10 Threshold comparison e...

Page 382: ...n the SEQB_GDAT register is read If the MODE bit in the SEQB_CTRL register is 1 this flag will be set upon completion of an entire B sequence In this case it must be cleared by writing a 1 to this SEQB_INT bit This interrupt must be enabled in the INTEN register 0 30 THCMP_INT Threshold Comparison Interrupt This bit will be set if any of the THCMP flags in the lower bits of this register are set t...

Page 383: ...nch the dummy conversion cycle that is required if a calibration is not performed It will also reload the stored calibration value from a previous calibration unless the BYPASSCAL bit is set This bit should only be set AFTER the ADC_ENA bit is set and after the CALIREQD bit is tested to determine whether a calibration or an ADC dummy conversion cycle is required It should not be set during the sam...

Page 384: ...pecify the active edge for the selected trigger independently for each conversion sequence For each conversion sequence if a designated trigger event occurs one single cycle through that conversion sequence will be launched unless The BURST bit in the SEQn_CTRL register for this sequence is set to 1 The requested conversion sequence is already in progress A set of conversions for the alternate con...

Page 385: ...ated conversion sequence will be continuously and repetitively cycled through Any new software or hardware trigger on this sequence will be ignored If a bursting A sequence is allowed to be interrupted i e the LOWPRIO bit in its SEQA_CTRL register is set to 1 and a software or hardware trigger for the B sequence occurs then the burst will be immediately interrupted and a B sequence will be initiat...

Page 386: ...on complete mode This flag will be cleared when the OVERRUN bit that caused it is cleared via reading the register containing it Note that the OVERRUN bits in the individual data registers are cleared when data related to that channel is read from either of the global data registers as well as when the individual data registers themselves are read 25 7 5 Optional Operating Modes There are three op...

Page 387: ... has been manually disabled requires a specific start up procedure It is strongly recommended that the provided Enable ADC API routine be used to enable or re enable the ADC The API routine will perform the necessary steps including executing a calibration cycle if required Important The ADC clock must be running at its full operating frequency prior to calling the API routine to enable the ADC Th...

Page 388: ...C bit description 25 7 10 Sample time The analog input from the selected channel is sampled at the start of each new A D conversion The default and shortest duration of this sample period is 2 5 ADC clock cycles Under some conditions longer sample times may be required A variety of factors including operating conditions the ADC clock frequency the selected ADC resolution and the impedance of the a...

Page 389: ...ns 0 50 ns 2 0 2k to 0 5k ohms 31 ns 0 56 ns 2 0 5k to 1 0k ohms 47 ns 1 74 ns 3 1k to 5k ohms 75 ns 3 105 ns 6 10 bits under 0 05k ohms 15 ns 0 35 ns 1 0 05 to 0 1k ohms 18 ns 0 38 ns 1 0 1K to 0 2k ohms 20 ns 0 40 ns 1 0 2k to 0 5k ohms 24 ns 0 46 ns 1 0 5k to 1 0k ohms 38 ns 1 61 ns 2 1k to 5k ohms 62 ns 2 86 ns 4 8 bits under 0 05k ohms 12 ns 0 27 ns 0 0 05 to 0 1k ohms 13 ns 0 29 ns 0 0 1K to...

Page 390: ...enever the START bit is written to The ADC converts an analog input signal VIN on the ADC0_ 11 0 pins The VREFP and VREFN pins provide a positive and negative reference voltage input The result of the conversion is 4095 x VIN VREFP VREFN The result of an input voltage below VREFN is 0 and the result of an input voltage above VREFP is 4095 0xFFF To perform a single ADC conversion for ADC0 channel 1...

Page 391: ...0 see Chapter 10 for details 3 Configure the system clock to be 80 MHz and select a CLKDIV value of 0 for a sampling rate of 80 MHz using the ADC CTRL register 4 Select the synchronous mode in the CTRL register 5 Select ADC channels 0 to 3 to perform the conversion by setting the CHANNELS bits to 0xF in the SEQA_CTRL register 6 Select trigger PINT1 by writing 0x1 the TRIGGER bits in the SEQA_CTRL ...

Page 392: ... x7 x5 x4 x2 x 1 Bit order reverse and 1 s complement programmable setting for input data and CRC sum Programmable seed number setting Supports CPU PIO back to back transfer Accept any size of data width per write 8 16 or 32 bit 8 bit write 1 cycle operation 16 bit write 2 cycle operation 8 bit x 2 cycle 32 bit write 4 cycle operation 8 bit x 4 cycle 26 3 Basic configuration Set the CRC bit in the...

Page 393: ...ber 2016 394 of 464 NXP Semiconductors UM10850 Chapter 26 LPC5410x CRC engine 26 5 General description The Cyclic Redundancy Check CRC generator with programmable polynomial settings supports several CRC standards commonly used Fig 58 CRC block diagram 7 7 32 5 32 5 32 5 5 7 5 9 56 V 203 4 5 60 V 203 7 5 9 56 5 6 5 02 08 08 08 86 5 5 5 8 5 680 ...

Page 394: ...ription Reset value 1 0 CRC_POLY CRC polynom 1X CRC 32 polynomial 01 CRC 16 polynomial 00 CRC CCITT polynomial 00 2 BIT_RVS_WR Data bit order 1 Bit order reverse for CRC_WR_DATA per byte 0 No bit order reverse for CRC_WR_DATA per byte 0 3 CMPL_WR Data complement 1 1 s complement for CRC_WR_DATA 0 No 1 s complement for CRC_WR_DATA 0 4 BIT_RVS_SUM CRC sum bit order 1 Bit order reverse for CRC_SUM 0 ...

Page 395: ...C data register This register is a Write only register containing the data block for which the CRC sum will be calculated Table 437 CRC checksum register SUM address 0x1C01 0008 bit description Bit Symbol Description Reset value 31 0 CRC_SUM The most recent CRC sum can be read through this register with selected bit order and 1 s complement post processes 0x0000 FFFF Table 438 CRC data register WR...

Page 396: ...ment for data input NO Bit order reverse for CRC sum NO 1 s complement for CRC sum NO CRC_MODE 0x0000 0000 CRC_SEED 0x0000 FFFF 26 7 2 CRC 16 set up Polynomial x16 x15 x2 1 Seed Value 0x0000 Bit order reverse for data input YES 1 s complement for data input NO Bit order reverse for CRC sum YES 1 s complement for CRC sum NO CRC_MODE 0x0000 0015 CRC_SEED 0x0000 0000 26 7 3 CRC 32 set up Polynomial x...

Page 397: ...share resources and communicate with each other in a simple manner Each CPU can cause up to 32 user defined interrupts to its partner Each CPU can claim a shared resource if it is available 27 3 Basic configuration Set the MAILBOX bit in the AHBCLKCTRL0 register Table 51 to enable the clock to the Mailbox 27 4 Pin description The Mailbox has no configurable pins 27 5 General description The Mailbo...

Page 398: ...Table 439 Register overview Mailbox base address 0x1C02 C000 Name Access Address offset Description Reset value Reference IRQ0 R W 0x000 Interrupt request register for the Cortex M0 CPU 0 Table 440 IRQ0SET WO 0x004 Set bits in IRQ0 Table 441 IRQ0CLR WO 0x008 Clear bits in IRQ0 Table 442 IRQ1 R W 0x010 Interrupt request register for the Cortex M4 CPU 0 Table 443 IRQ1SET WO 0x014 Set bits in IRQ1 Ta...

Page 399: ... between 2 CPUs Whenever a CPU wishes to access a shared resource possibly a resource allocation table in memory it reads the MUTEX register If it sees a 1 it has control over the shared resource allocation When it has made any needed changes it write to the register causing it to become set again and making control of shared resource allocation available to another CPU If a CPU reads a 0 it must ...

Page 400: ...of flash memory A typical usage is to verify the flashed contents against a calculated signature e g during programming The signature generator can also be accessed via an IAP function call Section 31 6 11 or ISP command Section 31 5 17 The address range for generating a signature must be aligned on flash word boundaries i e 128 bit boundaries Once started signature generation completes independen...

Page 401: ...gister overview FMC base address 0x4002 4000 Name Access Offset Description Reset value Reference FMSSTART R W 0x020 Signature start address register 0 Table 448 FMSSTOP R W 0x024 Signature stop address register 0 Table 449 FMSW0 RO 0x02C Word 0 of 128 bit signature word Table 450 FMSW1 RO 0x030 Word 1 of 128 bit signature word Table 451 FMSW2 RO 0x034 Word 2 of 128 bit signature word Table 452 FM...

Page 402: ...tarting a signature generation operation otherwise the status might indicate completion of a previous operation 28 4 4 Signature status clear register The FMSTATCLR register is used to clear the signature generation completion flag Table 450 FMSW0 register bit description FMSW0 offset 0x02C Bit Symbol Description Reset value 31 0 SW0 31 0 Word 0 of 128 bit signature bits 31 to 0 Table 451 FMSW1 re...

Page 403: ...gnature generation is triggered via software the duration is in AHB clock cycles and tcy is the time in ns for one AHB clock The SIG_DONE bit in FMSTAT can be polled by software to determine when signature generation is complete After signature generation a 128 bit signature can be read from the FMSW0 to FMSW3 registers The 128 bit signature reflects the corrected data read from the flash The 128 ...

Page 404: ...ent includes 2 watchpoints Supports JTAG boundary scan Instrumentation Trace Macrocell allows additional software controlled trace for the Cortex M4 29 3 Basic configuration The serial wire debug pins are enabled by default The JTAG pins for boundary scan are selected by hardware after a reset 29 4 Pin description The tables below indicate the various pin functions related to debug Some of these f...

Page 405: ...tion Description TCK Input JTAG Test Clock This pin is the clock for JTAG boundary scan when the RESET pin is LOW TMS Input JTAG Test Mode Select The TMS pin selects the next state in the TAP state machine This pin includes an internal pull up and is used for JTAG boundary scan when the RESET pin is LOW TDI Input JTAG Test Data In This is the serial data input for the shift register This pin inclu...

Page 406: ...reduced power modes work internal to the CPU Therefore power measurements should not be made while debugging power consumption is higher than during normal operation During a debugging session the System Tick Timer is automatically stopped whenever the CPU is stopped Other peripherals are not affected 29 6 2 Debug connections for SWD For debugging purposes it is useful to provide access to the ISP...

Page 407: ...8 of 464 NXP Semiconductors UM10850 Chapter 29 LPC5410x Serial Wire Debug SWD Fig 59 Connecting the SWD pins to a standard SWD connector 5 6 7 6LJQDOV IURP 6 FRQQHFWRU 6 2 6 9 QG 975 6 2 6 Q6567 6 2 6 2 1 0 8 63 HQWU SLQV 63B 63B Fig 60 Serial Wire Debug internal connections 6HULDO LUH HEXJ FRQQHFWLRQ RUWH 0 3 38 RUWH 0 3 38 63 3 6 3 53 OHYHO EORFNV OLQN ...

Page 408: ...tached to a debugger 29 6 4 1 Resynchronization request Communication with the ISP AP is initiated by the debugger The debugger first sets the RESYNCH_REQ bit in the CSW register The debugger must then reset the device by either writing a 1 to the CHIP_RESET_REQ bit in the CSW or by driving the actual reset pin of the device if it is able to do so 29 6 4 2 Acknowledgement of resynchronization requ...

Page 409: ...e 462 Table 459 Command and Status Word register CSW offset 0x00 bit description Bit Symbol Description Reset value 0 RESYNCH_REQ The debugger sets this bit to requests a re synchronization 0 1 REQ_PENDING A request is pending for the debugger a value is waiting to be read from the REQUEST register 0 2 DBG_OR_ERR When 1 a debug overrun has occurred a REQUEST value has been overwritten by the debug...

Page 410: ...ility 29 7 2 Cortex M0 present on LPC54102 devices Four breakpoints Two data Watchpoints Table 462 Identification register ID offset 0xFC bit description Bit Symbol Description Reset value 31 0 ID Identification value 0x002A 0000 Table 463 Register overview ISP AP base address 0x1C04 0000 Name Command code Description Enter ISP AP 1 Cause the device to enter ISP AP command mode This must be done p...

Page 411: ...ral description PLL setup and control of device power consumption or entry to low power modes can be configured through simple calls to the power profile APIs exist to Set up the System PLL Set up on chip power based on the expected operating frequency Set up reduced power modes Set up special low frequency low power operation Remark Disable all interrupts before making calls to the power profile ...

Page 412: ... unsigned int desired_freq void power_mode_configure unsigned int mode unsigned int peripheral PWRD Fig 61 ROM power API pointer structure 3RLQWHU WR 520 GULYHU WDEOH 3RLQWHU WR GHYLFH WDEOH 3RLQWHU WR GHYLFH WDEOH 3RLQWHU WR GHYLFH WDEOH 3RLQWHU WR 3RZHU 3 WDEOH 3RLQWHU WR GHYLFH WDEOH Q 520 GULYHU WDEOH VHWBSOO VHWBYROWDJH SRZHUBPRGHBFRQILJXUH 3RZHU 3 IXQFWLRQ WDEOH Table 465 Power API ROM calls...

Page 413: ...urn code of zero indicates that the operation was successful Table 466 Power API calls in LPCOpen power library Function prototype API description Section uint32_t Chip_POWER_SetPLL uint32_t multiply_by uint32_t input_freq Power API PLL configuration routine This API sets up basic PLL operation 30 4 1 uint32_t Chip_POWER_SetVoltage 0 uint32_t desired_freq Power API internal voltage configuration r...

Page 414: ...p_POWER_EnterPowerMode API prepares the part then enters any of the low power modes Specifically for power down and deep sleep modes the API function configures which analog components remain running in those two modes so that an interrupt from one of the analog peripherals can wake up the part Table 469 Chip_POWER_SetVoltage routine Routine Chip_POWER_SetVoltage Prototype uint32_t Chip_POWER_SetV...

Page 415: ...4 3 2 Param1 peripheral If sleep mode is selected with the mode parameter the peripheral parameter is ignored The peripheral parameter defines which analog peripherals can wake up the chip from deep sleep power down or deep power down mode The selected peripherals remain running in deep sleep or power down modes For example the watchdog oscillator must be running if the WWDT is to remain active in...

Page 416: ...ral description 31 3 1 Boot loader For the boot loader operation and boot pin see Chapter 6 LPC5410x Boot process The boot loader version can be read by ISP IAP calls see Section 31 5 13 or Section 31 6 6 31 3 2 Memory map after any reset The boot ROM is 64 KB in size and is located in the memory region starting from the address 0x0300 0000 The boot loader is designed to run from this memory area ...

Page 417: ...ntries to be 0 The boot loader code checksums the first 8 locations in sector 0 of the flash If the result is 0 then execution control is transferred to the user code If the signature is not valid the auto baud routine synchronizes with the host via the serial port USART If the USART is selected the host should send a 0x3F as a synchronization character and wait for a response The host side serial...

Page 418: ... restricted When needed CRP is invoked by programming a specific pattern in flash location at 0x0000 02FC IAP commands are not affected by the code read protection Important any CRP change becomes effective only after the device has gone through a power cycle Table 473 Flash sectors and pages Sector number Sector size KB Page numbers Address range 0 32 0 127 0x0000 0000 0x0000 7FFF 1 32 128 255 0x...

Page 419: ...P2 0x8765 4321 Access to chip via the SWD pins is disabled The following ISP commands are disabled Read Memory Write to RAM Go Copy RAM to flash Compare When CRP2 is enabled the ISP erase command only allows erasure of all user sectors CRP3 0x4321 8765 Access to chip via the SWD pins is disabled ISP entry selected via the ISP entry pin is disabled if a valid user code is present in flash sector 0 ...

Page 420: ...fer any code protection 31 3 7 ISP interrupt and SRAM use 31 3 7 1 Interrupts during IAP The on chip flash memory is not accessible during erase write operations When the user application code starts executing the interrupt vectors from the user flash area are active Before making any IAP call either disable the interrupts or ensure that the user interrupt vectors are active in RAM and that the in...

Page 421: ...inated with Carriage Return CR and or Line Feed LF control characters Extra CR and LF characters are ignored All ISP responses are sent as CR LF terminated ASCII strings Data is sent and received in plain binary format 31 4 1 USART ISP command format Command Parameter_0 Parameter_1 Parameter_n CR LF Data Data only for Write commands 31 4 2 USART ISP response format Return_Code CR LF Response_0 CR ...

Page 422: ...able 477 Set Baud Rate B Baud Rate stop bit Table 478 Echo A setting Table 479 Write to RAM W start address number of bytes Table 480 Read Memory R address number of bytes Table 481 Prepare sectors for write operation P start sector number end sector number Table 482 Copy RAM to flash C Flash address RAM address number of bytes Table 483 Go G address Mode Table 484 Erase sector s E start sector nu...

Page 423: ...e Example B 57600 1 CR LF sets the serial port to baud rate 57600 bps and 1 stop bit Table 479 USART ISP Echo command Command A Input Setting ON 1 OFF 0 Return Code CMD_SUCCESS PARAM_ERROR Description The default setting for echo command is ON When ON the ISP command handler sends the received serial data back to the host Example A 0 CR LF turns echo off Table 480 USART ISP Write to RAM command Co...

Page 424: ...ration then erases the entire sector Table 481 USART ISP Read Memory command Command R Input Start Address Address from where data bytes are to be read This address should be a word boundary Number of Bytes Number of bytes to be read Count should be a multiple of 4 Return Code CMD_SUCCESS followed by actual data plain binary ADDR_ERROR Address not on word boundary ADDR_NOT_MAPPED COUNT_ERROR Byte ...

Page 425: ...RITE_OPERATION BUSY CMD_LOCKED PARAM_ERROR CODE_READ_PROTECTION_ENABLED Description This command is used to program the flash memory The Prepare Sector s for Write Operation command should precede this command The affected sectors are automatically protected again once the copy command is successfully executed This command is blocked when code read protection is enabled Also see Section 31 3 3 for...

Page 426: ...CMD_LOCKED PARAM_ERROR CODE_READ_PROTECTION_ENABLED Description This command is used to erase one or more sector s of on chip flash memory This command only allows erasure of all user sectors when the code read protection is enabled Example E 2 3 CR LF erases the flash sectors 2 and 3 Table 486 USART ISP Erase page command Command X Input Start Page Number End Page Number Should be greater than or...

Page 427: ...s enabled the blank check command returns 0 for the offset and value of sectors which are not blank Blank sectors are correctly reported irrespective of the CRP setting Example I 2 3 CR LF blank checks the flash sectors 2 and 3 Table 488 USART ISP Read Part Identification command Command J Input None Return Code CMD_SUCCESS followed by part identification number see Table 489 LPCA5410x device iden...

Page 428: ...ared This address should be a word boundary Number of Bytes Number of bytes to be compared should be a multiple of 4 Return Code CMD_SUCCESS Source and destination data are equal COMPARE_ERROR Followed by the offset of first mismatch COUNT_ERROR Byte count is not a multiple of 4 ADDR_ERROR ADDR_NOT_MAPPED PARAM_ERROR Description This command is used to compare the memory contents at two locations ...

Page 429: ...mory This command is blocked when code read protection is enabled Example S 33587200 4 CR LF reads the CRC checksum for 4 bytes of data from address 0x0200 8000 If checksum value is 0xCBF43926 then the host will receive 3421780262 CR LF Table 494 USART ISP Read flash signature command Command Z Input none Return Code CMD_SUCCESS followed by data in decimal format CODE_READ_PROTECTION_ENABLED Descr...

Page 430: ...umber 0x8 ERR_ISP_SECTOR_NOT_BLANK Sector is not blank 0x9 ERR_ISP_SECTOR_NOT_PREPARED_ FOR_WRITE_OPERATION Command to prepare sector for write operation was not executed 0xA ERR_ISP_COMPARE_ERROR Source and destination data not equal 0xB ERR_ISP_BUSY Flash programming hardware interface is busy 0xC ERR_ISP_PARAM_ERROR Insufficient number of parameters or invalid parameter 0xD ERR_ISP_ADDR_ERROR A...

Page 431: ...0000E ERR_ISP_ADDR_NOT_MAPPED 0x0000000F ERR_ISP_CMD_LOCKED Command is locked 0x00000010 ERR_ISP_INVALID_CODE Unlock code is invalid 0x00000011 ERR_ISP_INVALID_BAUD_RATE 0x00000012 ERR_ISP_INVALID_STOP_BIT 0x00000013 ERR_ISP_CODE_READ_PROTECTION_ENABLED 0x00000014 ERR_ISP_INVALID_FLASH_UNIT reserved 0x00000015 ERR_ISP_USER_CODE_CHECKSUM reserved 0x00000016 ERR_ISP_SETTING_ACTIVE_PARTITION reserved...

Page 432: ...dUID command The command handler sends the status code INVALID_COMMAND when an undefined command is received The IAP routine resides at 0x0300 0204 location and it is thumb code therefore called as 0x03000205 by the Cortex M4 to insure Thumb operation The IAP function could be called in the following way using C Define the IAP location entry point Since the least significant bit of the IAP locatio...

Page 433: ...ry is not accessible during a write or erase operation IAP commands which results in a flash write erase operation use 32 bytes of space in the top portion of the on chip RAM for execution The user program should not be use this space if IAP flash programming is permitted in the application Table 496 IAP Command Summary IAP Command Command code Reference Prepare sector s for write operation 50 dec...

Page 434: ...art and End sector numbers Table 498 IAP Copy RAM to flash command Command Copy RAM to flash Input Command code 51 decimal Param0 DST Destination flash address where data bytes are to be written This address should be a 256 byte boundary Param1 SRC Source RAM address from which data bytes are to be read This address should be a word boundary Param2 Number of bytes to be written Should be 256 512 1...

Page 435: ...e Start and End sector numbers Remark All user code must be written in such a way that no master accesses the flash while this command is executed and the flash is erased Table 500 IAP Blank check sector s command Command Blank check sector s Input Command code 53 decimal Param0 Start Sector Number Param1 End Sector Number should be greater than or equal to start sector number Status code CMD_SUCC...

Page 436: ...RAM address of data bytes to be compared should be a word boundary Param2 Number of bytes to be compared should be a multiple of 4 Status code CMD_SUCCESS COMPARE_ERROR COUNT_ERROR Byte count is not a multiple of 4 ADDR_ERROR ADDR_NOT_MAPPED Result Result0 Offset of the first mismatch if the status code is COMPARE_ERROR Description This command is used to compare the memory contents at two locatio...

Page 437: ...Param0 Start page number Param1 End page number should be greater than or equal to start page Param2 System Clock Frequency CCLK in kHz Status code CMD_SUCCESS BUSY SECTOR_NOT_PREPARED_FOR_WRITE_OPERATION INVALID_PAGE Result None Description This command is used to erase a page or multiple pages of on chip flash memory To erase a single page use the same start and end page numbers Remark All user ...

Page 438: ...tination address is not on a correct boundary 4 SRC_ADDR_NOT_MAPPED Source address is not mapped in the memory map Count value is taken in to consideration where applicable 5 DST_ADDR_NOT_MAPPED Destination address is not mapped in the memory map Count value is taken in to consideration where applicable 6 COUNT_ERROR Byte count is not multiple of 4 or is not a permitted value 7 INVALID_SECTOR Sect...

Page 439: ...n functionality in compliance with the ANSI IEEE Standard 754 2008 The FPU provides add subtract multiply divide multiply and accumulate and square root operations It also performs a variety of conversions between fixed point floating point and integer data formats 46 interrupts are implemented for the Cortex M4 Not all interrupts are available on all part numbers 3 interrupt priority bits are imp...

Page 440: ...he LPC5410x An MPU is not included for the Cortex M0 32 interrupts are implemented for the Cortex M0 Not all interrupts are available on all part numbers The vector table offset register is included The multiplier configuration is the low power 32 clock version Sleep mode power saving NXP microcontrollers extend the number of reduced power modes beyond what is directly supported by the Cortex M0 D...

Page 441: ...L Boundary Scan Description Language CRC Cyclic Redundancy Check DCC Debug Communication Channel DMA Direct Memory Access FIFO First In First Out FMC Flash Memory Controller GPIO General Purpose Input Output I2C Inter IC Control bus I2C or IIC Inter Integrated Circuit bus IAP In Application Programming IRC oscillator Internal Resistor Capacitor oscillator ISP In System Programming ISR Interrupt Se...

Page 442: ...ers NXP B V 2016 All rights reserved User manual Rev 2 4 13 September 2016 443 of 464 NXP Semiconductors UM10850 Chapter 33 Supplementary information 2 Cortex M0 TRM ARM Cortex M0 Processor Technical Reference Manual 3 AN11538 AN11538 application note and code bundle SCT cookbook ...

Page 443: ...ducts using NXP Semiconductors products and NXP Semiconductors accepts no liability for any assistance with applications or customer product design It is customer s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer s applications and products planned as well as for the planned application and use of customer s third party customer s Custom...

Page 444: ...Table 35 Peripheral reset control register 0 PRESETCTRL0 address 0x4000 0044 bit description 34 Table 36 Peripheral reset control register 1 PRESETCTRL1 address 0x4000 0048 bit description 35 Table 37 Peripheral reset control set register 0 PRESETCTRLSET0 address 0x4000 004C bit description 36 Table 38 Peripheral reset control set register 1 PRESETCTRLSET1 address 0x4000 0050 bit description 36 Ta...

Page 445: ...Stack register CPSTACK address 0x4000 0308 bit description 61 Table 84 Coprocessor Status register CPSTAT address 0x4000 030C bit description 61 Table 85 JTAG ID code register JTAGIDCODE address 0x4000 03F4 bit description 62 Table 86 Device ID0 register DEVICE_ID0 address 0x4000 03F8 bit description 62 Table 87 Device ID0 register values 62 Table 88 Device ID1 register DEVICE_ID1 address 0x4000 0...

Page 446: ...t 0x2100 0x2104 bit description 110 Table 145 Address map MPIN 0 1 registers 111 Table 146 GPIO masked port pin register MPIN 0 1 address offset 0x2180 0x2184 bit description 111 Table 147 Address map SET 0 1 registers 111 Table 148 GPIO set port register SET 0 1 address offset 0x2200 0x2204 bit description 111 Table 149 Address map CLR 0 1 registers 111 Table 150 GPIO clear port register CLR 0 1 ...

Page 447: ...8 Address map CFG 0 21 registers 160 Table 199 Channel configuration registers bit description 160 Table 200 Trigger setting summary 161 Table 201 Address map CTLSTAT 0 21 registers 162 Table 202 Channel control and status registers bit description 162 Table 203 Address map XFERCFG 0 21 registers 163 Table 204 Channel transfer configuration registers bit description 163 Table 205 SCT0 pin descript...

Page 448: ...able 257 Capture Control Register CCR address offset 0x028 bit description 213 Table 258 Address map CR 0 3 registers 214 Table 259 Timer capture registers CR 0 3 address offsets 0x02C 0x038 bit description 214 Table 260 Address map EMR register 214 Table 261 Timer external match registers EMR address offset 0x03C bit description 215 Table 262 Address map CTCR register 216 Table 263 Count Control ...

Page 449: ...ption 271 Table 315 USART Baud Rate Generator register BRG offset 0x20 bit description 272 Table 316 USART Interrupt Status register INTSTAT offset 0x24 bit description 273 Table 317 Oversample selection register OSR offset 0x28 bit description 273 Table 318 Address register ADDR offset 0x2C bit description 274 Table 319 SPI Pin Description 282 Table 320 Suggested SPI pin settings 282 Table 321 Re...

Page 450: ...on register for USARTn CFGUSART 0 3 address offset 0x1000 0x1300 bit description 344 Table 384 Address map STATUSART 0 3 registers 345 Table 385 Status register for USARTn STATUSART 0 3 address offset 0x1004 0x1304 bit description 345 Table 386 Address map INTSTATUSART 0 3 registers 346 Table 387 Interrupt status register for USARTn INTSTATUSART 0 3 address offset 0x1008 0x1308 bit description 346...

Page 451: ...bit description 399 Table 443 M4 interrupt IRQ1 address 0x1C02 C010 bit description 400 Table 444 M4 interrupt set register IRQ1SET address 0x1C02 C014 bit description 400 Table 445 M4 interrupt clear register IRQ1CLR address 0x1C02 C018 bit description 400 Table 446 Mutual Exclusion register MUTEX address 0x1C02 C0F8 bit description 400 Table 447 Register overview FMC base address 0x4002 4000 402...

Page 452: ...491 USART ISP Compare command 429 Table 492 USART ReadUID command 429 Table 493 USART ISP Read CRC checksum command430 Table 494 USART ISP Read flash signature command 430 Table 495 USART ISP Error codes 430 Table 496 IAP Command Summary 434 Table 497 IAP Prepare sector s for write operation command 435 Table 498 IAP Copy RAM to flash command 435 Table 499 IAP Erase Sector s command 436 Table 500 ...

Page 453: ...ation 197 Fig 28 SCT configuration example 202 Fig 29 32 bit counter timer block diagram 206 Fig 30 A timer cycle in which PR 2 MRx 6 and both interrupt and reset on match are enabled 218 Fig 31 A timer cycle in which PR 2 MRx 6 and both interrupt and stop on match are enabled 219 Fig 32 Sample PWM waveforms with a PWM cycle length of 100 selected by MR3 and MAT3 0 enabled as PWM outputs by the PW...

Page 454: ...21 Interrupt Priority Register 10 25 3 4 22 Software Trigger Interrupt Register 26 Chapter 4 LPC5410x System configuration SYSCON 4 1 Features 27 4 2 Basic configuration 27 4 2 1 Set up the PLL 27 4 2 2 Configure the main clock and system clock 27 4 2 3 Measure the frequency of a clock signal 28 4 3 Pin description 28 4 4 General description 28 4 4 1 Clock generation 28 4 5 Register description 30...

Page 455: ... generator register 66 4 5 61 BOD control register 67 4 6 Functional description 67 4 6 1 Reset 67 4 6 2 Start up behavior 68 4 6 3 Brown out detection 69 4 6 4 PLL functional description 69 4 6 4 1 PLL Features 70 4 6 4 2 PLL description 70 4 6 4 2 1 Lock detector 70 4 6 4 2 2 Power down 71 4 6 4 3 Operating modes 71 4 6 4 3 1 Normal modes 71 Normal mode with optional pre divide 72 Normal mode wi...

Page 456: ...ers 110 9 5 5 GPIO port pin registers 110 9 5 6 GPIO masked port pin registers 111 9 5 7 GPIO port set registers 111 9 5 8 GPIO port clear registers 111 9 5 9 GPIO port toggle registers 112 9 5 10 GPIO port direction set registers 112 9 5 11 GPIO port direction clear registers 112 9 5 12 GPIO port direction toggle registers 113 9 6 Functional description 114 9 6 1 Reading pin state 114 9 6 2 GPIO ...

Page 457: ...ional description 165 12 7 1 Trigger operation 165 Chapter 13 LPC5410x SCTimer PWM SCT0 13 1 How to read this chapter 166 13 2 Features 166 13 3 Basic configuration 167 13 4 Pin description 168 13 5 General description 169 13 6 Register description 171 13 6 1 Register functional grouping 174 13 6 1 1 Counter configuration and control registers 176 13 6 1 2 Event configuration registers 176 13 6 1 ...

Page 458: ... Match Register 214 14 7 11 Count Control Register 216 14 7 12 PWM Control Register 217 14 8 Functional description 218 14 8 1 Rules for single edge controlled PWM outputs 219 14 8 2 DMA operation 220 Chapter 15 LPC5410x Windowed Watchdog Timer WWDT 15 1 How to read this chapter 221 15 2 Features 221 15 3 Basic configuration 222 15 4 Pin description 222 15 5 General description 222 15 5 1 Block di...

Page 459: ... 1 How to read this chapter 254 20 2 Features 254 20 3 Basic configuration 254 20 4 General description 254 20 5 Register description 255 20 5 1 CTRL register 255 20 5 2 Status register 255 Chapter 21 LPC5410x USARTs USART0 1 2 3 21 1 How to read this chapter 256 21 2 Features 256 21 3 Basic configuration 257 21 3 1 Configure the USART clock and baud rate 257 21 3 2 Configure the USART for wake up...

Page 460: ...Sleep mode 307 23 4 3 2 Wake up from Deep sleep and Power down modes 308 23 5 General description 308 23 6 Register description 309 23 6 1 I2C Configuration register 311 23 6 2 I2C Status register 313 23 6 3 Interrupt Enable Set and read register 317 23 6 4 Interrupt Enable Clear register 318 23 6 5 Time out value register 319 23 6 6 Clock Divider register 320 23 6 7 Interrupt Status register 320 ...

Page 461: ...1 378 25 6 8 ADC Channel Threshold Select register 379 25 6 9 ADC Interrupt Enable Register 380 25 6 10 ADC Flags register 382 25 6 11 ADC Startup register 384 25 6 12 ADC Calibration register 384 25 7 Functional description 385 25 7 1 Conversion Sequences 385 25 7 2 Hardware triggered conversion 385 25 7 2 1 Avoiding spurious hardware triggers 386 25 7 3 Software triggered conversion 386 25 7 4 I...

Page 462: ...0x08 bit description 410 29 6 4 5 4 Identification register ID offset 0xFC bit description 411 29 6 4 6 ISP AP commands 411 29 6 4 7 ISP AP return codes 411 29 7 Debug configuration 411 29 7 1 Cortex M4 411 29 7 2 Cortex M0 present on LPC54102 devices 411 Chapter 30 LPC5410x Power profiles Power control API 30 1 How to read this chapter 412 30 2 Features 412 30 3 General description 412 30 4 API d...

Page 463: ...ad flash signature 430 31 5 18 ISP Error codes 430 31 6 IAP commands 433 31 6 1 Prepare sector s for write operation 435 31 6 2 Copy RAM to flash 435 31 6 3 Erase Sector s 436 31 6 4 Blank check sector s 436 31 6 5 Read Part Identification number 436 31 6 6 Read Boot code version number 437 31 6 7 Compare address1 address2 no of bytes 437 31 6 8 Reinvoke ISP 437 31 6 9 ReadUID 438 31 6 10 Erase pa...

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