M0A21/M0A23 Series
May 06, 2022
Page
626
of 746
Rev 1.02
M0
A21
/M
0
A
2
3
SE
RIES
TEC
H
NICAL
RE
FEREN
C
E
M
ANUAL
Example for Bit Timing at High Baud Rate
In this example, the frequency of APB_CLK is 10 MHz, BRP (CAN_BTIME[5:0]) is 0, and the bit rate is
1 MBit/s.
t
q
100 ns
= t
APB_CLK
delay of bus driver
50ns
delay of receiver circuit 30ns
delay of bus line (40m) 220ns
t
Prop
600ns
= 6 • t
q
t
SJW
100ns
= 1 • t
q
t
TSeg1
700ns
= t
Prop
+ t
SJW
t
TSeg2
200ns
= Information Processing Time + 1 • t
q
t
Sync-Seg
100ns
= 1 • t
q
bit time 1000ns
= t
Sync-Seg
+ t
TSeg1
+ t
TSeg2
tolerance for APB_CLK 0.39% =
))
2
(
13
2
)
2
,
1
(
PB
time
bit
PB
PB
Min
=
))
2
.
0
1
(
13
2
1
.
0
us
us
us
In this example, the concatenated bit time parameters are (2-1)
3
& (7-1)
4
& (1-1)
2
& (1-1)
6
, and the Bit
Timing Register is programmed to 0x1600.
Note:
PB1/2: indicate the phase buffer segment 1/2
The subscript of (2-1)
3
indicates the number of bits in the corresponding bit of Bit Timing Register.
CAN Interface Reset State
After the hardware reset, the C_CAN registers hold the reset values which are given in the register
description in 0.
Additionally the bus-off state is reset and the output CAN_TX is set to recessive (HIGH). The value
0x0001 (Init = ‘1’) in the CAN Control Register enables the software initialization. The C_CAN does not
influence the CAN bus until the application software resets the Init bit (CAN_CON[0]) to ‘0’.
The data stored in the Message RAM is not affected by a hardware reset. After powered on, the contents
of the Message RAM are undefined.
Example for Bit Timing at Low Baud Rate
In this example, the frequency of APB_CLK is 2 MHz, BRP (CAN_BTIME[5:0]) is 1, and the bit rate is
100 Kbit/s.
t
q
1
us
= 2 •t
APB_CLK
delay of bus driver
200ns
delay of receiver circuit 80ns
delay of bus line (40m) 220ns
t
Prop
1u
s = 1 • t
q
