M0A21/M0A23 Series
May 06, 2022
Page
187
of 746
Rev 1.02
M0
A21
/M
0
A
2
3
SE
RIES
TEC
H
NICAL
RE
FEREN
C
E
M
ANUAL
When entering Power-down mode, system clocks, some clock sources and some peripheral clocks are
disabled. Some clock sources and peripherals clock are still active in Power-down mode.
For theses clocks, which still keep active, are listed below:
Clock Generator
–
38.4 kHz internal low speed RC oscillator (LIRC) clock
–
32.768 kHz external low speed crystal oscillator (LXT) clock
Peripherals Clock (When the modules adopt LXT or LIRC as clock source)
6.3.6
Clock Output
This device is equipped with a power-of-2 frequency divider which is composed by16 chained divide-
by-2 shift registers. One of the 16 shift register outputs selected by a sixteen to one multiplexer is
reflected to CLKO function pin. Therefore there are 16 options of power-of-2 divided clocks with the
frequency from F
in
/2
1
to F
in
/2
16
where F
in
is input clock frequency to the clock divider.
The output formula is
F
out
= F
in
/2
(N+1)
,
where F
in
is the input clock frequency, F
out
is the clock divider
output frequency and N is the 4-bit value in FREQSEL (CLK_CLKOCTL[3:0]).
When writing 1 to CLKOEN (CLK_CLKOCTL[4]), the chained counter starts to count. When writing 0 to
CLKOEN (CLK_CLKOCTL[4]), the chained counter continuously runs till divided clock reaches low state
and stays in low state.
0000
0001
1110
1111
:
:
16 to 1
MUX
1/2
1/2
2
1/2
3
1/2
15
1/2
16
…...
FREQSEL
(CLK_CLKOCTL[3:0])
CLKO
16 chained
divide-by-2 counter
CLKOEN
(CLK_CLKOCTL[4])
Enable
divide-by-2 counter
0
1
DIV1EN
(CLK_CLKOCTL[5])
HCLK
LXT
HXT
CLKOSEL (CLK_CLKSEL1[6:4])
010
001
000
LIRC
100
LIRC
100
HIRC
101
Figure 6.3-6 Clock Output Block Diagram
