M0A21/M0A23 Series
May 06, 2022
Page
347
of 746
Rev 1.02
M0
A21
/M
0
A
2
3
SE
RIES
TEC
H
NICAL
RE
FEREN
C
E
M
ANUAL
DIRF
(PWM_CNTn[16])
0
1
2
3
4
3
1
2
0
1
2
3
4
3
1
2
0
5
6
7
6
4
5
1
2
3
4
PWM Period
PERIOD = 4
CMPDAT = 4
PERIOD = 7
CMPDAT = 5
PWM Period
Up-count compared
point event (CMPU)
Down-count compared
point event (CMPD)
PERIOD = 5
CMPDAT= 0
CNT
(PWM_CNTn[15:0])
Note1:
No CMPU event occurred when CMPDAT equals to PERIOD.
Note2:
n denotes channel 0,1..5
Figure 6.10-11 PWM Compared point Events in Up-Down Counter Type
6.10.5.7 PWM Double Buffering
The double buffering uses double buffers to separate software writing and hardware action operation
timing. There are three loading modes for loading values to buffer: period loading mode, immediately
loading mode, and center loading mode. After registers are modified through software, hardware will
load register value to the buffer register according to the loading mode timing. The hardware action is
based on the buffer value.
This can prevent asynchronously operation problem due to software and
hardware asynchronism.
The PWM provides PBUF (PWM_PBUFn[15:0]) as the active PERIOD buffer register, CMPBUF
(PWM_CMPBUFn[15:0]) as the active CMPDAT buffer register. The concept of double buffering is used
in loading modes, which are described in the following sections. For example, as shown Figure 6.10-12,
in period loading mode, writing PERIOD and CMPDAT through software, PWM will load new values to
their buffer PBUF (PWM_PBUFn[15:0]) and CMPBUF (PWM_CMPBUFn[15:0]) at start of the next
period without affecting the current period counter operation.
CMPDAT
PERIOD
S/W Write PERIOD
CNT
4
7
3
start
Initialize
PWM
2
S/W Write CMPDAT
0
1
2
3
4
3
1
2
0
1
2
3
4
3
1
2
0
5
6
7
6
4
5
1
2
3
4
Load from PERIOD to PBUF,
from CMPDAT to CMPBUF
Load from CMPDAT
to CMPBUF
PBUF
4
7
CMPBUF
3
2
CMPU
CMPD
