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Nuvoton NuMicro M0A21 Series, Technical Reference Manual

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Nuvoton NuMicro M0A21 Series Technical Reference Manual Download Page 435

            M0A21/M0A23 Series 

 

May 06, 2022 

Page 

435

 of 746 

Rev 1.02 

M0

A21

/M
0

A

2

3

 SE
RIES

 TEC

H

NICAL 

RE
FEREN

C

E 
M

ANUAL

 

SOUT

( from UART TX )

IR_ SOUT

( encoder output )

IR_SIN

( decorder input )

SIN

( to UART RX )

0

0

1

0

1

1

1

0

0

1

1

1

Bit cycle width

3/ 16 bit width

STOP BIT

START BIT

IrDA

TX Timing

IrDA

RX Timing

0

1

0

0

1

0

1

0

0

START BIT

STOP BIT

3/ 16 bit width

1

 

Figure 6.11-16 IrDA TX/RX Timing Diagram 

6.11.5.10 LIN Function Mode (Local Interconnection Network) 

The UART Controller supports LIN function. Setting FUNCSEL (UART_FUNCSEL[2:0]) to 

‘001’ to select 

LIN mode operation. The UART Controller supports LIN break/delimiter generation and break/delimiter 
detection in LIN master mode, and supports header detection and automatic resynchronization in LIN 
Slave mode. 

 Structure of LIN Frame 

According to the LIN protocol, all information transmitted is packed as frames; a frame consists of a 
header (provided by the master task) and a response (provided by a slave task). The header (provided 
by the master task) consists of a break field and a sync field followed by a frame identifier (frame ID). 
The frame identifier uniquely defines the purpose of the frame. The slave task is appointed for providing 
the response associated with the frame ID. The response consists of a data field and a checksum field. 
Figure 6.11-17 is the structure of LIN Frame. 

Data 1

Data 2

Data N

Check 

Sum

Protected 

Identifier

field

Header

Response 

space

Response

Inter-

frame 

space

Frame

Frame slot

Synch

field

Break

Field

 

Figure 6.11-17 Structure of LIN Frame 

 Structure of LIN Byte 

In LIN mode, each byte field is initiated by a START bit with value 0 (dominant), followed by 8 data bits 
and no parity bit, LSB is first and ended by 1 stop bit with value 1 (recessive) in accordance with the LIN 
standard. The structure of Byte is shown in Figure 6.11-18. 

Summary of Contents for NuMicro M0A21 Series

Page 1: ...lectual property of Nuvoton Technology Corporation and shall not be reproduced without permission from Nuvoton Nuvoton is providing this document only for reference purposes of NuMicro microcontroller and microprocessor based system design Nuvoton assumes no responsibility for errors or omissions All data and specifications are subject to change without notice For additional information or questio...

Page 2: ...2 1 M0A21 M0A23 Series Pin Description 44 4 2 2 M0A21 M0A23 Series Multi function Summary Table 62 4 2 3 M0A21 M0A23 Series Multi function Summary Table Sorted by GPIO 80 5 BLOCK DIAGRAM 98 6 FUNCTIONAL DESCRIPTION 99 6 1 Arm Cortex M0 Core 99 6 2 System Manager 101 6 2 1 Overview 101 6 2 2 System Reset 101 6 2 3 System Power Distribution 107 6 2 4 Power Modes and Wake up Sources 107 6 2 5 System ...

Page 3: ...r Description 228 6 5 General Purpose I O GPIO 237 6 5 1 Overview 237 6 5 2 Features 237 6 5 3 Block Diagram 238 6 5 4 Basic Configuration 238 6 5 5 Functional Description 238 6 5 6 Register Map 243 6 5 7 Register Description 245 6 6 PDMA Controller PDMA 259 6 6 1 Overview 259 6 6 2 Features 259 6 6 3 Block Diagram 259 6 6 4 Basic Configuration 259 6 6 5 Functional Description 260 6 6 6 Register M...

Page 4: ...WM 337 6 10 1Overview 337 6 10 2Features 337 6 10 3Block Diagram 338 6 10 4Basic Configuration 341 6 10 5Functional Description 343 6 10 6Register Map 365 6 10 7Register Description 368 6 11 UART Interface Controller UART 416 6 11 1Overview 416 6 11 2Features 416 6 11 3Block Diagram 417 6 11 4Basic Configuration 420 6 11 5Functional Description 421 6 11 6Register Map 446 6 11 7Register Description...

Page 5: ...r Repeated START Signal 569 6 15 6Register Map 587 6 15 7Register Description 588 6 16 Controller Area Network CAN 607 6 16 1Overview 607 6 16 2Features 607 6 16 3Block Diagram 607 6 16 4Basic Configuration 608 6 16 5Functional Description 609 6 16 6Test Mode 610 6 16 7CAN Communications 612 6 16 8Register Map 628 6 16 9Register Description 633 6 17 CRC Controller CRC 667 6 17 1Overview 667 6 17 2...

Page 6: ...09 6 20 5Functional Description 709 6 20 6Register Map 713 6 20 7Register Description 714 6 21 Analog Comparator Controller ACMP 721 6 21 1Overview 721 6 21 2Features 721 6 21 3Block Diagram 721 6 21 4Basic Configuration 722 6 21 5Functional Description 723 6 21 6Register Map 728 6 21 7Register Description 729 6 22 Peripherals Interconnection 736 6 22 1Overview 736 6 22 2Peripherals Interconnect M...

Page 7: ...M0A21 M0A23 Series May 06 2022 Page 7 of 746 Rev 1 02 M0A21 M0A23 SERIES TECHNICAL REFERENCE MANUAL 11 REVISION HISTORY 745 ...

Page 8: ...e 6 2 10 NuMicro M0A21 M0A23 Bus Matrix Diagram 114 Figure 6 3 1 Clock Generator Global View Diagram 183 Figure 6 3 2 Clock Generator Block Diagram 184 Figure 6 3 3 System Clock Block Diagram 185 Figure 6 3 4 HXT Stop Protect Procedure 186 Figure 6 3 5 SysTick Clock Control Block Diagram 186 Figure 6 3 6 Clock Output Block Diagram 187 Figure 6 4 116 32 KB Flash Memory Control Block Diagram 209 Fig...

Page 9: ...nuous Counting Mode 298 Figure 6 7 4 External Capture Mode 299 Figure 6 7 5 Reset Counter Mode 300 Figure 6 7 6 Internal Timer Trigger 301 Figure 6 7 7 Inter Timer Trigger Capture Timing 302 Figure 6 8 1 Watchdog Timer Block Diagram 317 Figure 6 8 2 Watchdog Timer Clock Control 318 Figure 6 8 3 Watchdog Timer Time out Interval and Reset Period Timing 319 Figure 6 9 1 WWDT Block Diagram 326 Figure ...

Page 10: ...gram for PWMx_CH0 and PWMx_CH1 Pair 356 Figure 6 10 26 Edge Detector Waveform for PWMx_CH0 and PWMx_CH1 Pair 357 Figure 6 10 27 Level Detector Waveform for PWMx_CH0 and PWMx_CH1 Pair 357 Figure 6 10 28 Brake Source Block Diagram 358 Figure 6 10 29 Brake System Fail Block Diagram 358 Figure 6 10 30 Initial State and Polarity Control with Rising Edge Dead Time Insertion 359 Figure 6 10 31 PWM_CH0 an...

Page 11: ...ng Level in Auto Direction Mode 443 Figure 6 11 25 RS 485 nRTS Driving Level with Software Control 444 Figure 6 11 26 Structure of RS 485 Frame 444 Figure 6 12 1 USCI Block Diagram 485 Figure 6 12 2 Input Conditioning for USCIx_DAT 1 0 and USCIx_CTL 1 0 486 Figure 6 12 3 Input Conditioning for USCIx_CLK 487 Figure 6 12 4 Block Diagram of Data Buffering 488 Figure 6 12 5 Data Access Structure 489 F...

Page 12: ... Half duplex SPI Master Mode 539 Figure 6 14 16 SPI Timing in Master Mode 540 Figure 6 14 17 SPI Timing in Master Mode Alternate Phase of Serial Bus Clock 541 Figure 6 14 18 SPI Timing in Slave Mode 541 Figure 6 14 19 SPI Timing in Slave Mode Alternate Phase of Serial Bus Clock 542 Figure 6 15 1 I2 C Bus Timing 567 Figure 6 15 2 USCI I C Mode Block Diagram 568 Figure 6 15 3 I2 C Protocol 569 Figur...

Page 13: ... 17 1 CRC Generator Block Diagram 667 Figure 6 17 2 CHECKSUM Bit Order Reverse Functional Block 668 Figure 6 17 3 Write Data Bit Order Reverse Functional Block 669 Figure 6 18 1 Hardware Divider Operation Flow 676 Figure 6 19 1 AD Controller Block Diagram 684 Figure 6 19 2 ADC Peripheral Clock Control 685 Figure 6 19 3 Single Mode Conversion Timing Diagram 686 Figure 6 19 4 Burst Mode Conversion T...

Page 14: ...722 Figure 6 21 2 Comparator Hysteresis Function of ACMP0 723 Figure 6 21 3 Window Latch Mode 724 Figure 6 21 4 Filter Function Example 724 Figure 6 21 5 Comparator Controller Interrupt 725 Figure 6 21 6 Comparator Reference Voltage Block Diagram 725 Figure 6 21 7 Example of Window Compare Mode 726 Figure 6 21 8 Example of Window Compare Mode 727 ...

Page 15: ...Prescaler Value Selection 327 Table 6 9 2 CMPDAT Setting Limitation 330 Table 6 10 1 PWM Clock Source Control Registers Setting Table 339 Table 6 10 2 PWM Pulse Generation Event Priority for Up Counter 351 Table 6 10 3 PWM Pulse Generation Event Priority for Down Counter 352 Table 6 10 4 PWM Pulse Generation Event Priority for Up Down Counter 352 Table 6 11 1 NuMicro M0A21 M0A23 Series UART Featur...

Page 16: ...figuration 533 Table 6 15 1 Relationship between I2 C Baud Rate and PCLK 584 Table 6 16 1 Initialization of a Transmit Object 615 Table 6 16 2 Initialization of a Receive Object 616 Table 6 16 3 CAN Bit Time Parameters 620 Table 6 16 4 CAN Register Map for Each Bit Function 632 Table 6 16 5 Last Error Code 636 Table 6 16 6 Source of Interrupts 639 Table 6 16 7 IF1 and IF2 Message Interface Registe...

Page 17: ...rich analog functions including 17 ch 12 bit 500 KSPS ADC 1 set of 5 bit DAC and 2 sets of ACMP in both SSOP20 and TSSOP28 package Moreover it provides low voltage reset LVR and brown out detector BOD to ensure the system safety The NuMicro M0A21 M0A23 series runs up to 48 MHz and supports hardware divider It provides 32 Kbytes Flash memory 4 Kbytes SRAM and 2 Kbytes LDROM for ISP In System Progra...

Page 18: ...e sensor 32 bit H W Divider HDIV Signed two s complement integer calculation 32 bit dividend with 16 bit divisor calculation capacity 32 bit quotient and 32 bit remainder outputs 16 bit remainder with sign extends to 32 bit 6 HCLK clocks taken for one cycle calculation Memories Boot Loader Nuvoton ISP In System Programming tool for firmware upgrade via UART ISP IAP libraries Flash Up to 32 KB appl...

Page 19: ... Uses DMA to write data with performing CRC operation Peripheral DMA PDMA Supports up to 5 independent configurable channels for automatic data transfer between memories and peripherals Basic and Scatter Gather transfer modes Each channel supports circular buffer management using Scatter Gather Transfer mode Stride function for rectangle image data movement Fixed priority and Round robin prioritie...

Page 20: ...al capture interrupt flag to trigger PWM ADC and PDMA PWM Three 16 bit counters with 12 bit prescale for six 48 MHz PWM output channels Supports independent mode for PWM output Capture input channel Supports complementary mode for 3 complementary paired PWM output channel Dead time insertion with 12 bit resolution Two compared values during one period Supports 16 bit resolution PWM counter Up down...

Page 21: ... bit resolution and 10 bit accuracy is guaranteed Up to 17 single end analog input channels or 8 differential analog input channels Maximum ADC peripheral clock frequency is 16 MHz Up to 500 KSPS sampling rate Four operation modes Single mode A D conversion is performed one time on a specified channel Burst mode A D converter samples and converts the specified single channel and sequentially store...

Page 22: ...us Supports software and timer0 3 trigger to start DAC conversion Supports PDMA mode Analog Comparator ACMP Analog input voltage range 0 AVDD voltage of VDD pin Up to two rail to rail analog comparators Supports hysteresis function Supports wake up function Selectable input sources of positive input and negative input ACMP0 supports 3 multiplexed I O pins at positive sources ACMP0_P0 Comparator Re...

Page 23: ...tection function Programmable transmitting data delay time between the last stop and the next start bit by setting DLY UART_TOUT 15 8 Supports Auto Baud Rate measurement and baud rate compensation function Supports break error frame error parity error and receive transmit buffer overflow detection function Fully programmable serial interface characteristics Programmable number of data bit 5 6 7 8 ...

Page 24: ...ports UART SPI and I2 C function Single byte TX and RX buffer mode UART One transmit buffer and two receive buffer for data payload Hardware auto flow control function and programmable flow control trigger level Programmable baud rate generator Supports 9 Bit Data Transfer Baud rate detection by built in capture event of baud rate generator Supports Wake up function Data and nCTS Wakeup Only Suppo...

Page 25: ...ports Bus monitor mode Power down wake up by data toggle or address match Multiple address recognition Device address flag Setup hold time programmable GPIO Four I O modes Quasi bidirectional mode Push Pull Output mode Open Drain Output mode Input only with high impendence mode Schmitt trigger input I O pin configured as interrupt source with edge level trigger setting Supports high drive and high...

Page 26: ...A23 Series May 06 2022 Page 26 of 746 Rev 1 02 M0A21 M0A23 SERIES TECHNICAL REFERENCE MANUAL 3 PARTS INFORMATION 3 1 Package Type SSOP20 TSSOP28 M0A21OB1AC M0A21OC1AC M0A23OC1AC M0A21EB1AC M0A21EC1AC M0A23EC1AC ...

Page 27: ... 2 18 4 6 5 2 2 2 1 1 2 17 ch SSOP20 M0A21OC1AC 32 4 2 18 4 6 5 2 2 2 1 1 2 17 ch SSOP20 M0A21EB1AC 16 4 2 26 4 6 5 2 2 2 1 1 2 17 ch TSSOP28 M0A21EC1AC 32 4 2 26 4 6 5 2 2 2 1 1 2 17 ch TSSOP28 USCI supports UART SPI or I2 C 3 2 2 NuMicro M0A23 Series Part Number Flash KB SRAM KB ISP ROM KB I O Timer PWM PDMA Connectivity DAC LXT ACMP ADC 12 Bit Package USCI UART LIN CAN M0A23OC1AC 32 4 2 18 4 6 ...

Page 28: ...SERIES TECHNICAL REFERENCE MANUAL 3 2 3 NuMicro M0A21 M0A23 Selection Code Core Series Package Flash Size SRAM Size Revision Temperature M0 A21 O C 1 A C Cortex M0 A21 without CAN A23 with CAN O SSOP20 5 3x7 2 mm E SSOP28 4 4x9 7 mm B 16 KB C 32 KB 1 4 KB C 40 C 125 C ...

Page 29: ...Tool PinConfigure contains all Nuvoton NuMicro Family chip series with all part number and helps configure GPIO multi function pins correctly and handily 4 1 Pin Configuration 4 1 1 M0A21 Series Pin Diagram SSOP20 Package Corresponding Part Number M0A21OB1AC M0A21OC1AC SSOP20 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 VDD PA 5 PA 4 PA 3 PC 5 PC 4 PC 3 PC 6 PC 7 PB 7 VSS PA 0 PA 1 PA 2 PC 0...

Page 30: ... CLKO PWM0_CH0 PWM0_CH2 PWM0_CH4 UART0_TXD UART0_RXD USCI0_CLK USCI0_DAT0 USCI0_DAT1 USCI0_CTL0 USCI0_CTL1 USCI1_CLK USCI1_DAT0 USCI1_DAT1 USCI1_CTL0 ACMP0_O ACMP1_O ADC0_ST TM0 TM2 TM0_EXT TM2_EXT UART1_TXD UART1_RXD ACMP0_WLAT 3 PA 4 ADC0_CH15 UART0_nRTS XT1_OUT CLKO PWM0_CH1 PWM0_CH3 PWM0_CH5 UART0_TXD UART0_RXD USCI0_CLK USCI0_DAT0 USCI0_DAT1 USCI0_CTL0 USCI1_CTL1 USCI1_CLK USCI1_DAT0 USCI1_DA...

Page 31: ...WM0_CH5 UART0_TXD UART0_RXD USCI0_CLK USCI0_DAT0 USCI0_DAT1 USCI0_CTL0 USCI0_CTL1 USCI1_CLK USCI1_DAT0 USCI1_DAT1 USCI1_CTL0 ACMP0_O ACMP1_O ADC0_ST TM1 TM3 TM1_EXT TM3_EXT UART1_TXD UART1_RXD ACMP1_WLAT 12 PB 5 ADC0_CH7 UART0_nRTS UART0_nCTS CLKO PWM0_CH0 PWM0_CH2 PWM0_CH4 UART0_TXD UART0_RXD USCI0_CLK USCI0_DAT0 USCI0_DAT1 USCI0_CTL0 USCI1_CTL1 USCI1_CLK USCI1_DAT0 USCI1_DAT1 USCI1_CTL0 ACMP0_O ...

Page 32: ...RESET UART0_nCTS PWM0_CH0 PWM0_CH2 PWM0_CH4 UART0_RXD USCI0_CLK USCI0_DAT0 USCI0_DAT1 USCI0_CTL0 USCI0_CTL1 USCI1_CLK USCI1_DAT0 USCI1_DAT1 USCI1_CTL0 ADC0_ST TM0 TM2 TM0_EXT TM2_EXT UART1_RXD INT0 5 PC 5 ADC0_CH14 X32_IN UART0_nCTS CLKO PWM0_CH1 PWM0_CH3 PWM0_CH5 UART0_TXD UART0_RXD USCI0_CLK USCI0_DAT0 USCI0_DAT1 USCI0_CTL0 USCI0_CTL1 USCI1_CLK USCI1_DAT0 USCI1_DAT1 USCI1_CTL0 ACMP0_O ACMP1_O AD...

Page 33: ... USCI1_CTL0 ACMP0_O ACMP1_O ADC0_ST TM0 TM2 TM0_EXT TM2_EXT UART1_TXD UART1_RXD UART1_nRTS 15 PC 1 ADC0_CH4 ACMP0_N1 ACMP1_N1 UART0_nRTS UART0_nCTS CLKO PWM0_CH1 PWM0_CH3 PWM0_CH5 UART0_TXD UART0_RXD USCI0_CLK USCI0_DAT0 USCI0_DAT1 USCI0_CTL0 USCI0_CTL1 USCI1_CLK USCI1_DAT0 USCI1_DAT1 USCI1_CTL0 ACMP0_O ACMP1_O ADC0_ST TM1 TM3 TM1_EXT TM3_EXT UART1_TXD UART1_RXD 16 PC 0 ADC0_CH3 ACMP1_P0 UART0_nRT...

Page 34: ...CH1 PWM0_CH3 PWM0_CH5 UART0_TXD UART0_RXD USCI0_CLK USCI0_DAT0 USCI0_DAT1 USCI0_CTL0 USCI0_CTL1 USCI1_CLK USCI1_DAT0 USCI1_DAT1 USCI1_CTL0 ACMP0_O ACMP1_O ADC0_ST TM1 TM3 TM1_EXT TM3_EXT UART1_TXD UART1_RXD INT3 8 PD 0 PWM0_CH4 UART0_TXD USCI1_CLK TM0 9 PD 1 PWM0_CH5 UART0_RXD USCI1_DAT0 TM1 10 PD 2 PWM0_CH0 USCI1_DAT1 TM2 UART1_nCTS 11 PD 3 PWM0_CH1 USCI1_CTL0 TM3 UART1_nRTS 12 PC 6 ADC0_CH11 UAR...

Page 35: ..._nCTS CLKO PWM0_CH0 PWM0_CH2 PWM0_CH4 UART0_TXD UART0_RXD USCI0_CLK USCI0_DAT0 USCI0_DAT1 USCI0_CTL0 USCI1_CTL1 USCI1_CLK USCI1_DAT0 USCI1_DAT1 USCI1_CTL0 ACMP0_O ACMP1_O ADC0_ST TM0 TM2 TM0_EXT TM2_EXT UART1_TXD UART1_RXD PWM0_BRAKE0 25 PA 2 ADC0_CH2 UART0_nRTS UART0_nCTS CLKO PWM0_CH1 PWM0_CH3 PWM0_CH5 UART0_TXD UART0_RXD USCI0_CLK USCI0_DAT0 USCI0_DAT1 USCI0_CTL0 USCI0_CTL1 USCI1_CLK USCI1_DAT0...

Page 36: ...WM0_CH4 UART0_TXD USCI1_CLK TM0 9 PD 1 PWM0_CH5 UART0_RXD USCI1_DAT0 TM1 10 PD 2 PWM0_CH0 USCI1_DAT1 TM2 UART1_nCTS 11 PD 3 PWM0_CH1 USCI1_CTL0 TM3 UART1_nRTS 12 PC 6 ADC0_CH11 UART0_nRTS UART0_nCTS CLKO PWM0_CH0 PWM0_CH2 PWM0_CH4 UART0_TXD UART0_RXD USCI0_CLK USCI0_DAT0 USCI0_DAT1 USCI0_CTL0 USCI1_CTL1 USCI1_CLK USCI1_DAT0 USCI1_DAT1 USCI1_CTL0 ACMP0_O ACMP1_O ADC0_ST TM0 TM2 TM0_EXT TM2_EXT UART...

Page 37: ...M3 TM1_EXT TM3_EXT UART1_TXD UART1_RXD 24 PC 0 ADC0_CH3 ACMP1_P0 UART0_nRTS UART0_nCTS CLKO PWM0_CH0 PWM0_CH2 PWM0_CH4 UART0_TXD UART0_RXD USCI0_CLK USCI0_DAT0 USCI0_DAT1 USCI0_CTL0 USCI1_CTL1 USCI1_CLK USCI1_DAT0 USCI1_DAT1 USCI1_CTL0 ACMP0_O ACMP1_O ADC0_ST TM0 TM2 TM0_EXT TM2_EXT UART1_TXD UART1_RXD PWM0_BRAKE0 25 PA 2 ADC0_CH2 UART0_nRTS UART0_nCTS CLKO PWM0_CH1 PWM0_CH3 PWM0_CH5 UART0_TXD UAR...

Page 38: ...E MANUAL 4 1 3 M0A23 Series Pin Diagram SSOP20 Package Corresponding Part Number M0A23OC1AC SSOP20 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 VDD PA 5 PA 4 PA 3 PC 5 PC 4 PC 3 PC 6 PC 7 PB 7 VSS PA 0 PA 1 PA 2 PC 0 PC 1 PC 2 PB 4 PB 5 PB 6 Figure 4 1 3 M0A23 Series SSOP 20 pin Diagram ...

Page 39: ...ackage Corresponding Part Number M0A23EC1AC TSSOP28 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VDD PA 5 PA 4 PA 3 PC 5 PC 4 PC 3 PD 0 PD 1 PD 2 PD 3 PC 6 PC 7 PB 7 VSS PA 0 PA 1 PA 2 PC 0 PC 1 PC 2 PB 4 PD 7 PD 6 PD 5 PD 4 PB 5 PB 6 Figure 4 1 4 M0A23 Series TSSOP 28 pin Diagram ...

Page 40: ...RXD ACMP0_O ACMP1_O ADC0_ST TM0 TM2 TM0_EXT TM2_EXT UART1_TXD UART1_RXD INT2 7 PC 3 ADC0_CH12 ACMP0_N3 ACMP1_N3 UART0_nRTS UART0_nCTS CLKO PWM0_CH1 PWM0_CH3 PWM0_CH5 UART0_TXD UART0_RXD USCI0_CLK USCI0_DAT0 USCI0_DAT1 USCI0_CTL0 USCI0_CTL1 USCI1_CLK USCI1_DAT0 USCI1_DAT1 USCI1_CTL0 CAN0_TXD CAN0_RXD ACMP0_O ACMP1_O ADC0_ST TM1 TM3 TM1_EXT TM3_EXT UART1_TXD UART1_RXD INT3 8 PC 6 ADC0_CH11 UART0_nRT...

Page 41: ...DC0_ST TM0 TM2 TM0_EXT TM2_EXT UART1_TXD UART1_RXD PWM0_BRAKE0 17 PA 2 ADC0_CH2 UART0_nRTS UART0_nCTS CLKO PWM0_CH1 PWM0_CH3 PWM0_CH5 UART0_TXD UART0_RXD USCI0_CLK USCI0_DAT0 USCI0_DAT1 USCI0_CTL0 USCI0_CTL1 USCI1_CLK USCI1_DAT0 USCI1_DAT1 USCI1_CTL0 CAN0_TXD CAN0_RXD ACMP0_O ACMP1_O ADC0_ST TM1 TM3 TM1_EXT TM3_EXT UART1_TXD UART1_RXD PWM0_BRAKE1 18 PA 1 ADC0_CH1 ACMP0_N0 ACMP1_N0 VREF ICE_CLK UAR...

Page 42: ...PD 2 PWM0_CH0 USCI1_DAT1 TM2 UART1_nCTS 11 PD 3 PWM0_CH1 USCI1_CTL0 TM3 UART1_nRTS 12 PC 6 ADC0_CH11 UART0_nRTS UART0_nCTS CLKO PWM0_CH0 PWM0_CH2 PWM0_CH4 UART0_TXD UART0_RXD USCI0_CLK USCI0_DAT0 USCI0_DAT1 USCI0_CTL0 USCI1_CTL1 USCI1_CLK USCI1_DAT0 USCI1_DAT1 USCI1_CTL0 CAN0_TXD CAN0_RXD ACMP0_O ACMP1_O ADC0_ST TM0 TM2 TM0_EXT TM2_EXT UART1_TXD UART1_RXD INT4 13 PC 7 ADC0_CH10 UART0_nRTS UART0_nC...

Page 43: ...T TM3_EXT UART1_TXD UART1_RXD 24 PC 0 ADC0_CH3 ACMP1_P0 UART0_nRTS UART0_nCTS CLKO PWM0_CH0 PWM0_CH2 PWM0_CH4 UART0_TXD UART0_RXD USCI0_CLK USCI0_DAT0 USCI0_DAT1 USCI0_CTL0 USCI1_CTL1 USCI1_CLK USCI1_DAT0 USCI1_DAT1 USCI1_CTL0 CAN0_TXD CAN0_RXD ACMP0_O ACMP1_O ADC0_ST TM0 TM2 TM0_EXT TM2_EXT UART1_TXD UART1_RXD PWM0_BRAKE0 25 PA 2 ADC0_CH2 UART0_nRTS UART0_nCTS CLKO PWM0_CH1 PWM0_CH3 PWM0_CH5 UART...

Page 44: ...4 I O MFP7 PWM0 channel 4 output capture input UART0_TXD O MFP8 UART0 data transmitter output pin UART0_RXD I MFP9 UART0 data receiver input pin USCI0_CLK I O MFP10 USCI0 clock pin USCI0_DAT0 I O MFP11 USCI0 data 0 pin USCI0_DAT1 I O MFP12 USCI0 data 1 pin USCI0_CTL0 I O MFP13 USCI0 control 0 pin USCI0_CTL1 I O MFP14 USCI0 control 1 pin USCI1_CLK I O MFP15 USCI1 clock pin USCI1_DAT0 I O MFP16 USCI...

Page 45: ...ut pin USCI0_CLK I O MFP10 USCI0 clock pin USCI0_DAT0 I O MFP11 USCI0 data 0 pin USCI0_DAT1 I O MFP12 USCI0 data 1 pin USCI0_CTL0 I O MFP13 USCI0 control 0 pin USCI1_CTL1 I O MFP14 USCI1 control 1 pin USCI1_CLK I O MFP15 USCI1 clock pin USCI1_DAT0 I O MFP16 USCI1 data 0 pin USCI1_DAT1 I O MFP17 USCI1 data 1 pin USCI1_CTL0 I O MFP18 USCI1 control 0 pin CAN0_TXD O MFP19 CAN0 bus transmitter output C...

Page 46: ...USCI0_CTL1 I O MFP14 USCI0 control 1 pin USCI1_CLK I O MFP15 USCI1 clock pin USCI1_DAT0 I O MFP16 USCI1 data 0 pin USCI1_DAT1 I O MFP17 USCI1 data 1 pin USCI1_CTL0 I O MFP18 USCI1 control 0 pin CAN0_RXD I MFP20 CAN0 bus receiver input ADC0_ST I MFP23 ADC0 external trigger input pin TM0 I O MFP24 Timer0 event counter input toggle output pin TM2 I O MFP25 Timer2 event counter input toggle output pin...

Page 47: ...ut pin ADC0_ST I MFP23 ADC0 external trigger input pin TM1 I O MFP24 Timer1 event counter input toggle output pin TM3 I O MFP25 Timer3 event counter input toggle output pin TM1_EXT I O MFP26 Timer1 external capture input toggle output pin TM3_EXT I O MFP27 Timer3 external capture input toggle output pin UART1_TXD O MFP28 UART1 data transmitter output pin UART1_RXD I MFP29 UART1 data receiver input...

Page 48: ...counter input toggle output pin TM0_EXT I O MFP26 Timer0 external capture input toggle output pin TM2_EXT I O MFP27 Timer2 external capture input toggle output pin UART1_TXD O MFP28 UART1 data transmitter output pin UART1_RXD I MFP29 UART1 data receiver input pin INT2 I MFP30 External interrupt 2 input pin 7 7 PC 3 I O MFP0 General purpose digital I O pin ADC0_CH12 A MFP1 ADC0 channel 12 analog in...

Page 49: ...er1 external capture input toggle output pin TM3_EXT I O MFP27 Timer3 external capture input toggle output pin UART1_TXD O MFP28 UART1 data transmitter output pin UART1_RXD I MFP29 UART1 data receiver input pin INT3 I MFP30 External interrupt 3 input pin 8 PD 0 I O MFP0 General purpose digital I O pin PWM0_CH4 I O MFP2 PWM0 channel 4 output capture input UART0_TXD O MFP3 UART0 data transmitter out...

Page 50: ...0_CH2 I O MFP6 PWM0 channel 2 output capture input PWM0_CH4 I O MFP7 PWM0 channel 4 output capture input UART0_TXD O MFP8 UART0 data transmitter output pin UART0_RXD I MFP9 UART0 data receiver input pin USCI0_CLK I O MFP10 USCI0 clock pin USCI0_DAT0 I O MFP11 USCI0 data 0 pin USCI0_DAT1 I O MFP12 USCI0 data 1 pin USCI0_CTL0 I O MFP13 USCI0 control 0 pin USCI1_CTL1 I O MFP14 USCI1 control 1 pin USC...

Page 51: ...put pin UART0_RXD I MFP9 UART0 data receiver input pin USCI0_CLK I O MFP10 USCI0 clock pin USCI0_DAT0 I O MFP11 USCI0 data 0 pin USCI0_DAT1 I O MFP12 USCI0 data 1 pin USCI0_CTL0 I O MFP13 USCI0 control 0 pin USCI0_CTL1 I O MFP14 USCI0 control 1 pin USCI1_CLK I O MFP15 USCI1 clock pin USCI1_DAT0 I O MFP16 USCI1 data 0 pin USCI1_DAT1 I O MFP17 USCI1 data 1 pin USCI1_CTL0 I O MFP18 USCI1 control 0 pi...

Page 52: ... pin USCI0_CTL0 I O MFP13 USCI0 control 0 pin USCI1_CTL1 I O MFP14 USCI1 control 1 pin USCI1_CLK I O MFP15 USCI1 clock pin USCI1_DAT0 I O MFP16 USCI1 data 0 pin USCI1_DAT1 I O MFP17 USCI1 data 1 pin USCI1_CTL0 I O MFP18 USCI1 control 0 pin CAN0_TXD O MFP19 CAN0 bus transmitter output CAN0_RXD I MFP20 CAN0 bus receiver input ACMP0_O O MFP21 Analog comparator 0 output pin ACMP1_O O MFP22 Analog comp...

Page 53: ...T0 I O MFP16 USCI1 data 0 pin USCI1_DAT1 I O MFP17 USCI1 data 1 pin USCI1_CTL0 I O MFP18 USCI1 control 0 pin CAN0_TXD O MFP19 CAN0 bus transmitter output CAN0_RXD I MFP20 CAN0 bus receiver input ACMP0_O O MFP21 Analog comparator 0 output pin ACMP1_O O MFP22 Analog comparator 1 output pin ADC0_ST I MFP23 ADC0 external trigger input pin TM1 I O MFP24 Timer1 event counter input toggle output pin TM3 ...

Page 54: ...itter output CAN0_RXD I MFP20 CAN0 bus receiver input ACMP0_O O MFP21 Analog comparator 0 output pin ACMP1_O O MFP22 Analog comparator 1 output pin ADC0_ST I MFP23 ADC0 external trigger input pin TM0 I O MFP24 Timer0 event counter input toggle output pin TM2 I O MFP25 Timer2 event counter input toggle output pin TM0_EXT I O MFP26 Timer0 external capture input toggle output pin TM2_EXT I O MFP27 Ti...

Page 55: ...er input toggle output pin UART1_nRTS O MFP6 UART1 request to Send output pin 13 21 PB 4 I O MFP0 General purpose digital I O pin ADC0_CH6 A MFP1 ADC0 channel 6 analog input UART0_nRTS O MFP2 UART0 request to Send output pin UART0_nCTS I MFP3 UART0 clear to Send input pin CLKO O MFP4 Clock Out PWM0_CH1 I O MFP5 PWM0 channel 1 output capture input PWM0_CH3 I O MFP6 PWM0 channel 3 output capture inp...

Page 56: ... pin ADC0_CH5 A MFP1 ADC0 channel 5 analog input ACMP0_N2 A MFP1 Analog comparator 0 negative input 2 pin ACMP1_N2 A MFP1 Analog comparator 1 negative input 2 pin UART0_nRTS O MFP2 UART0 request to Send output pin UART0_nCTS I MFP3 UART0 clear to Send input pin CLKO O MFP4 Clock Out PWM0_CH0 I O MFP5 PWM0 channel 0 output capture input PWM0_CH2 I O MFP6 PWM0 channel 2 output capture input PWM0_CH4...

Page 57: ...input ACMP0_N1 A MFP1 Analog comparator 0 negative input 1 pin ACMP1_N1 A MFP1 Analog comparator 1 negative input 1 pin UART0_nRTS O MFP2 UART0 request to Send output pin UART0_nCTS I MFP3 UART0 clear to Send input pin CLKO O MFP4 Clock Out PWM0_CH1 I O MFP5 PWM0 channel 1 output capture input PWM0_CH3 I O MFP6 PWM0 channel 3 output capture input PWM0_CH5 I O MFP7 PWM0 channel 5 output capture inp...

Page 58: ...Send output pin UART0_nCTS I MFP3 UART0 clear to Send input pin CLKO O MFP4 Clock Out PWM0_CH0 I O MFP5 PWM0 channel 0 output capture input PWM0_CH2 I O MFP6 PWM0 channel 2 output capture input PWM0_CH4 I O MFP7 PWM0 channel 4 output capture input UART0_TXD O MFP8 UART0 data transmitter output pin UART0_RXD I MFP9 UART0 data receiver input pin USCI0_CLK I O MFP10 USCI0 clock pin USCI0_DAT0 I O MFP...

Page 59: ... capture input PWM0_CH5 I O MFP7 PWM0 channel 5 output capture input UART0_TXD O MFP8 UART0 data transmitter output pin UART0_RXD I MFP9 UART0 data receiver input pin USCI0_CLK I O MFP10 USCI0 clock pin USCI0_DAT0 I O MFP11 USCI0 data 0 pin USCI0_DAT1 I O MFP12 USCI0 data 1 pin USCI0_CTL0 I O MFP13 USCI0 control 0 pin USCI0_CTL1 I O MFP14 USCI0 control 1 pin USCI1_CLK I O MFP15 USCI1 clock pin USC...

Page 60: ...MFP4 Clock Out PWM0_CH0 I O MFP5 PWM0 channel 0 output capture input PWM0_CH2 I O MFP6 PWM0 channel 2 output capture input PWM0_CH4 I O MFP7 PWM0 channel 4 output capture input UART0_TXD O MFP8 UART0 data transmitter output pin UART0_RXD I MFP9 UART0 data receiver input pin USCI0_CLK I O MFP10 USCI0 clock pin USCI0_DAT0 I O MFP11 USCI0 data 0 pin USCI0_DAT1 I O MFP12 USCI0 data 1 pin USCI0_CTL0 I ...

Page 61: ...pin CLKO O MFP4 Clock Out PWM0_CH1 I O MFP5 PWM0 channel 1 output capture input PWM0_CH3 I O MFP6 PWM0 channel 3 output capture input PWM0_CH5 I O MFP7 PWM0 channel 5 output capture input UART0_TXD O MFP8 UART0 data transmitter output pin UART0_RXD I MFP9 UART0 data receiver input pin USCI0_CLK I O MFP10 USCI0 clock pin USCI0_DAT0 I O MFP11 USCI0 data 0 pin USCI0_DAT1 I O MFP12 USCI0 data 1 pin US...

Page 62: ...og comparator 0 negative input 3 pin ACMP0_O PA 5 MFP21 O Analog comparator 0 output pin ACMP0_O PA 4 MFP21 O Analog comparator 0 output pin ACMP0_O PC 5 MFP21 O Analog comparator 0 output pin ACMP0_O PC 4 MFP21 O Analog comparator 0 output pin ACMP0_O PC 3 MFP21 O Analog comparator 0 output pin ACMP0_O PC 6 MFP21 O Analog comparator 0 output pin ACMP0_O PC 7 MFP21 O Analog comparator 0 output pin...

Page 63: ...FP22 O Analog comparator 1 output pin ACMP1_O PB 6 MFP22 O Analog comparator 1 output pin ACMP1_O PB 5 MFP22 O Analog comparator 1 output pin ACMP1_O PB 4 MFP22 O Analog comparator 1 output pin ACMP1_O PC 2 MFP22 O Analog comparator 1 output pin ACMP1_O PC 1 MFP22 O Analog comparator 1 output pin ACMP1_O PC 0 MFP22 O Analog comparator 1 output pin ACMP1_O PA 2 MFP22 O Analog comparator 1 output pi...

Page 64: ... trigger input pin ADC0_ST PC 3 MFP23 I ADC0 external trigger input pin ADC0_ST PC 6 MFP23 I ADC0 external trigger input pin ADC0_ST PC 7 MFP23 I ADC0 external trigger input pin ADC0_ST PB 7 MFP23 I ADC0 external trigger input pin ADC0_ST PB 6 MFP23 I ADC0 external trigger input pin ADC0_ST PB 5 MFP23 I ADC0 external trigger input pin ADC0_ST PB 4 MFP23 I ADC0 external trigger input pin ADC0_ST PC...

Page 65: ...ansmitter output CAN0_TXD PA 4 MFP19 O CAN0 bus transmitter output CAN0_TXD PC 5 MFP19 O CAN0 bus transmitter output CAN0_TXD PC 4 MFP19 O CAN0 bus transmitter output CAN0_TXD PC 3 MFP19 O CAN0 bus transmitter output CAN0_TXD PD 2 MFP3 O CAN0 bus transmitter output CAN0_TXD PC 6 MFP19 O CAN0 bus transmitter output CAN0_TXD PC 7 MFP19 O CAN0 bus transmitter output CAN0_TXD PB 7 MFP19 O CAN0 bus tra...

Page 66: ...l up resistor on ICE_CLK pin ICE_DAT PA 0 MFP2 I O Serial wired debugger data pin Note It is recommended to use 100 kΩ pull up resistor on ICE_DAT pin INT0 INT0 PA 3 MFP30 I External interrupt 0 input pin INT0 PB 5 MFP30 I External interrupt 0 input pin INT1 INT1 PC 5 MFP30 I External interrupt 1 input pin INT2 INT2 PC 4 MFP30 I External interrupt 2 input pin INT3 INT3 PC 3 MFP30 I External interr...

Page 67: ...CH1 PD 5 MFP2 I O PWM0 channel 1 output capture input PWM0_CH1 PB 4 MFP5 I O PWM0 channel 1 output capture input PWM0_CH1 PC 1 MFP5 I O PWM0 channel 1 output capture input PWM0_CH1 PA 2 MFP5 I O PWM0 channel 1 output capture input PWM0_CH1 PA 0 MFP5 I O PWM0 channel 1 output capture input PWM0_CH2 PA 5 MFP6 I O PWM0 channel 2 output capture input PWM0_CH2 PA 3 MFP6 I O PWM0 channel 2 output captur...

Page 68: ...channel 4 output capture input PWM0_CH5 PA 4 MFP7 I O PWM0 channel 5 output capture input PWM0_CH5 PC 5 MFP7 I O PWM0 channel 5 output capture input PWM0_CH5 PC 3 MFP7 I O PWM0 channel 5 output capture input PWM0_CH5 PD 1 MFP2 I O PWM0 channel 5 output capture input PWM0_CH5 PC 7 MFP7 I O PWM0 channel 5 output capture input PWM0_CH5 PB 6 MFP7 I O PWM0 channel 5 output capture input PWM0_CH5 PB 4 M...

Page 69: ...O Timer2 event counter input toggle output pin TM2 PC 4 MFP25 I O Timer2 event counter input toggle output pin TM2 PD 2 MFP5 I O Timer2 event counter input toggle output pin TM2 PC 6 MFP25 I O Timer2 event counter input toggle output pin TM2 PB 7 MFP25 I O Timer2 event counter input toggle output pin TM2 PB 5 MFP25 I O Timer2 event counter input toggle output pin TM2 PD 6 MFP5 I O Timer2 event cou...

Page 70: ...re input toggle output pin TM1_EXT PB 4 MFP26 I O Timer1 external capture input toggle output pin TM1_EXT PC 1 MFP26 I O Timer1 external capture input toggle output pin TM1_EXT PA 2 MFP26 I O Timer1 external capture input toggle output pin TM1_EXT PA 0 MFP26 I O Timer1 external capture input toggle output pin TM2 TM2_EXT PA 5 MFP27 I O Timer2 external capture input toggle output pin TM2_EXT PA 3 M...

Page 71: ...0 data receiver input pin UART0_RXD PB 5 MFP9 I UART0 data receiver input pin UART0_RXD PD 5 MFP3 I UART0 data receiver input pin UART0_RXD PB 4 MFP9 I UART0 data receiver input pin UART0_RXD PC 2 MFP9 I UART0 data receiver input pin UART0_RXD PC 1 MFP9 I UART0 data receiver input pin UART0_RXD PC 0 MFP9 I UART0 data receiver input pin UART0_RXD PA 2 MFP9 I UART0 data receiver input pin UART0_RXD ...

Page 72: ...input pin UART0_nCTS PB 7 MFP3 I UART0 clear to Send input pin UART0_nCTS PB 6 MFP3 I UART0 clear to Send input pin UART0_nCTS PB 5 MFP3 I UART0 clear to Send input pin UART0_nCTS PB 4 MFP3 I UART0 clear to Send input pin UART0_nCTS PC 2 MFP3 I UART0 clear to Send input pin UART0_nCTS PC 1 MFP3 I UART0 clear to Send input pin UART0_nCTS PC 0 MFP3 I UART0 clear to Send input pin UART0_nCTS PA 2 MFP...

Page 73: ..._RXD PB 4 MFP29 I UART1 data receiver input pin UART1_RXD PC 2 MFP29 I UART1 data receiver input pin UART1_RXD PC 1 MFP29 I UART1 data receiver input pin UART1_RXD PC 0 MFP29 I UART1 data receiver input pin UART1_RXD PA 2 MFP29 I UART1 data receiver input pin UART1_RXD PA 1 MFP29 I UART1 data receiver input pin UART1_RXD PA 0 MFP29 I UART1 data receiver input pin UART1_TXD PA 5 MFP28 O UART1 data ...

Page 74: ... PA 4 MFP10 I O USCI0 clock pin USCI0_CLK PA 3 MFP10 I O USCI0 clock pin USCI0_CLK PC 5 MFP10 I O USCI0 clock pin USCI0_CLK PC 4 MFP10 I O USCI0 clock pin USCI0_CLK PC 3 MFP10 I O USCI0 clock pin USCI0_CLK PC 6 MFP10 I O USCI0 clock pin USCI0_CLK PC 7 MFP10 I O USCI0 clock pin USCI0_CLK PB 7 MFP10 I O USCI0 clock pin USCI0_CLK PB 6 MFP10 I O USCI0 clock pin USCI0_CLK PB 5 MFP10 I O USCI0 clock pin...

Page 75: ...in USCI0_CTL0 PA 0 MFP13 I O USCI0 control 0 pin USCI0_CTL1 PA 5 MFP14 I O USCI0 control 1 pin USCI0_CTL1 PA 3 MFP14 I O USCI0 control 1 pin USCI0_CTL1 PC 5 MFP14 I O USCI0 control 1 pin USCI0_CTL1 PC 3 MFP14 I O USCI0 control 1 pin USCI0_CTL1 PC 7 MFP14 I O USCI0 control 1 pin USCI0_CTL1 PB 6 MFP14 I O USCI0 control 1 pin USCI0_CTL1 PB 4 MFP14 I O USCI0 control 1 pin USCI0_CTL1 PC 1 MFP14 I O USC...

Page 76: ...in USCI0_DAT1 PC 4 MFP12 I O USCI0 data 1 pin USCI0_DAT1 PC 3 MFP12 I O USCI0 data 1 pin USCI0_DAT1 PC 6 MFP12 I O USCI0 data 1 pin USCI0_DAT1 PC 7 MFP12 I O USCI0 data 1 pin USCI0_DAT1 PB 7 MFP12 I O USCI0 data 1 pin USCI0_DAT1 PB 6 MFP12 I O USCI0 data 1 pin USCI0_DAT1 PB 5 MFP12 I O USCI0 data 1 pin USCI0_DAT1 PD 6 MFP4 I O USCI0 data 1 pin USCI0_DAT1 PB 4 MFP12 I O USCI0 data 1 pin USCI0_DAT1 ...

Page 77: ...n USCI1_CTL0 PA 4 MFP18 I O USCI1 control 0 pin USCI1_CTL0 PA 3 MFP18 I O USCI1 control 0 pin USCI1_CTL0 PC 5 MFP18 I O USCI1 control 0 pin USCI1_CTL0 PC 4 MFP18 I O USCI1 control 0 pin USCI1_CTL0 PC 3 MFP18 I O USCI1 control 0 pin USCI1_CTL0 PD 3 MFP4 I O USCI1 control 0 pin USCI1_CTL0 PC 6 MFP18 I O USCI1 control 0 pin USCI1_CTL0 PC 7 MFP18 I O USCI1 control 0 pin USCI1_CTL0 PB 7 MFP18 I O USCI1...

Page 78: ...ta 0 pin USCI1_DAT0 PC 6 MFP16 I O USCI1 data 0 pin USCI1_DAT0 PC 7 MFP16 I O USCI1 data 0 pin USCI1_DAT0 PB 7 MFP16 I O USCI1 data 0 pin USCI1_DAT0 PB 6 MFP16 I O USCI1 data 0 pin USCI1_DAT0 PB 5 MFP16 I O USCI1 data 0 pin USCI1_DAT0 PB 4 MFP16 I O USCI1 data 0 pin USCI1_DAT0 PC 2 MFP16 I O USCI1 data 0 pin USCI1_DAT0 PC 1 MFP16 I O USCI1 data 0 pin USCI1_DAT0 PC 0 MFP16 I O USCI1 data 0 pin USCI...

Page 79: ...I1 data 1 pin USCI1_DAT1 PA 1 MFP17 I O USCI1 data 1 pin USCI1_DAT1 PA 0 MFP17 I O USCI1 data 1 pin VREF VREF PA 1 MFP1 A ADC reference voltage input Note This pin needs to be connected with a 1uF capacitor X32 X32_IN PC 5 MFP2 I External 32 768 kHz crystal input pin X32_OUT PC 4 MFP2 O External 32 768 kHz crystal output pin XT1 XT1_IN PA 5 MFP3 I External 4 24 MHz high speed crystal input pin XT1...

Page 80: ...r output pin UART0_RXD I MFP9 UART0 data receiver input pin USCI0_CLK I O MFP10 USCI0 clock pin USCI0_DAT0 I O MFP11 USCI0 data 0 pin USCI0_DAT1 I O MFP12 USCI0 data 1 pin USCI0_CTL0 I O MFP13 USCI0 control 0 pin USCI0_CTL1 I O MFP14 USCI0 control 1 pin USCI1_CLK I O MFP15 USCI1 clock pin USCI1_DAT0 I O MFP16 USCI1 data 0 pin USCI1_DAT1 I O MFP17 USCI1 data 1 pin USCI1_CTL0 I O MFP18 USCI1 control...

Page 81: ...PWM0_CH4 I O MFP7 PWM0 channel 4 output capture input UART0_TXD O MFP8 UART0 data transmitter output pin UART0_RXD I MFP9 UART0 data receiver input pin USCI0_CLK I O MFP10 USCI0 clock pin USCI0_DAT0 I O MFP11 USCI0 data 0 pin USCI0_DAT1 I O MFP12 USCI0 data 1 pin USCI0_CTL0 I O MFP13 USCI0 control 0 pin USCI1_CTL1 I O MFP14 USCI1 control 1 pin USCI1_CLK I O MFP15 USCI1 clock pin USCI1_DAT0 I O MFP...

Page 82: ...K I O MFP10 USCI0 clock pin USCI0_DAT0 I O MFP11 USCI0 data 0 pin USCI0_DAT1 I O MFP12 USCI0 data 1 pin USCI0_CTL0 I O MFP13 USCI0 control 0 pin USCI0_CTL1 I O MFP14 USCI0 control 1 pin USCI1_CLK I O MFP15 USCI1 clock pin USCI1_DAT0 I O MFP16 USCI1 data 0 pin USCI1_DAT1 I O MFP17 USCI1 data 1 pin USCI1_CTL0 I O MFP18 USCI1 control 0 pin CAN0_TXD O MFP19 CAN0 bus transmitter output CAN0_RXD I MFP20...

Page 83: ...n USCI1_CLK I O MFP15 USCI1 clock pin USCI1_DAT0 I O MFP16 USCI1 data 0 pin USCI1_DAT1 I O MFP17 USCI1 data 1 pin USCI1_CTL0 I O MFP18 USCI1 control 0 pin CAN0_RXD I MFP20 CAN0 bus receiver input ADC0_ST I MFP23 ADC0 external trigger input pin TM0 I O MFP24 Timer0 event counter input toggle output pin TM2 I O MFP25 Timer2 event counter input toggle output pin TM0_EXT I O MFP26 Timer0 external capt...

Page 84: ...24 Timer1 event counter input toggle output pin TM3 I O MFP25 Timer3 event counter input toggle output pin TM1_EXT I O MFP26 Timer1 external capture input toggle output pin TM3_EXT I O MFP27 Timer3 external capture input toggle output pin UART1_TXD O MFP28 UART1 data transmitter output pin UART1_RXD I MFP29 UART1 data receiver input pin ACMP1_WLAT I MFP30 Analog comparator 1 window latch input pin...

Page 85: ...T I O MFP26 Timer0 external capture input toggle output pin TM2_EXT I O MFP27 Timer2 external capture input toggle output pin UART1_TXD O MFP28 UART1 data transmitter output pin UART1_RXD I MFP29 UART1 data receiver input pin ACMP0_WLAT I MFP30 Analog comparator 0 window latch input pin PB 4 PB 4 I O MFP0 General purpose digital I O pin ADC0_CH6 A MFP1 ADC0 channel 6 analog input UART0_nRTS O MFP2...

Page 86: ...oggle output pin UART1_TXD O MFP28 UART1 data transmitter output pin UART1_RXD I MFP29 UART1 data receiver input pin UART1_nCTS I MFP30 UART1 clear to Send input pin PB 5 PB 5 I O MFP0 General purpose digital I O pin ADC0_CH7 A MFP1 ADC0 channel 7 analog input UART0_nRTS O MFP2 UART0 request to Send output pin UART0_nCTS I MFP3 UART0 clear to Send input pin CLKO O MFP4 Clock Out PWM0_CH0 I O MFP5 ...

Page 87: ...INT0 I MFP30 External interrupt 0 input pin PB 6 PB 6 I O MFP0 General purpose digital I O pin ADC0_CH8 A MFP1 ADC0 channel 8 analog input UART0_nRTS O MFP2 UART0 request to Send output pin UART0_nCTS I MFP3 UART0 clear to Send input pin CLKO O MFP4 Clock Out PWM0_CH1 I O MFP5 PWM0 channel 1 output capture input PWM0_CH3 I O MFP6 PWM0 channel 3 output capture input PWM0_CH5 I O MFP7 PWM0 channel 5...

Page 88: ...analog input UART0_nRTS O MFP2 UART0 request to Send output pin UART0_nCTS I MFP3 UART0 clear to Send input pin CLKO O MFP4 Clock Out PWM0_CH0 I O MFP5 PWM0 channel 0 output capture input PWM0_CH2 I O MFP6 PWM0 channel 2 output capture input PWM0_CH4 I O MFP7 PWM0 channel 4 output capture input UART0_TXD O MFP8 UART0 data transmitter output pin UART0_RXD I MFP9 UART0 data receiver input pin USCI0_...

Page 89: ... input pin CLKO O MFP4 Clock Out PWM0_CH0 I O MFP5 PWM0 channel 0 output capture input PWM0_CH2 I O MFP6 PWM0 channel 2 output capture input PWM0_CH4 I O MFP7 PWM0 channel 4 output capture input UART0_TXD O MFP8 UART0 data transmitter output pin UART0_RXD I MFP9 UART0 data receiver input pin USCI0_CLK I O MFP10 USCI0 clock pin USCI0_DAT0 I O MFP11 USCI0 data 0 pin USCI0_DAT1 I O MFP12 USCI0 data 1...

Page 90: ...capture input PWM0_CH3 I O MFP6 PWM0 channel 3 output capture input PWM0_CH5 I O MFP7 PWM0 channel 5 output capture input UART0_TXD O MFP8 UART0 data transmitter output pin UART0_RXD I MFP9 UART0 data receiver input pin USCI0_CLK I O MFP10 USCI0 clock pin USCI0_DAT0 I O MFP11 USCI0 data 0 pin USCI0_DAT1 I O MFP12 USCI0 data 1 pin USCI0_CTL0 I O MFP13 USCI0 control 0 pin USCI0_CTL1 I O MFP14 USCI0 ...

Page 91: ...e input UART0_TXD O MFP8 UART0 data transmitter output pin UART0_RXD I MFP9 UART0 data receiver input pin USCI0_CLK I O MFP10 USCI0 clock pin USCI0_DAT0 I O MFP11 USCI0 data 0 pin USCI0_DAT1 I O MFP12 USCI0 data 1 pin USCI0_CTL0 I O MFP13 USCI0 control 0 pin USCI1_CTL1 I O MFP14 USCI1 control 1 pin USCI1_CLK I O MFP15 USCI1 clock pin USCI1_DAT0 I O MFP16 USCI1 data 0 pin USCI1_DAT1 I O MFP17 USCI1...

Page 92: ...in UART0_RXD I MFP9 UART0 data receiver input pin USCI0_CLK I O MFP10 USCI0 clock pin USCI0_DAT0 I O MFP11 USCI0 data 0 pin USCI0_DAT1 I O MFP12 USCI0 data 1 pin USCI0_CTL0 I O MFP13 USCI0 control 0 pin USCI0_CTL1 I O MFP14 USCI0 control 1 pin USCI1_CLK I O MFP15 USCI1 clock pin USCI1_DAT0 I O MFP16 USCI1 data 0 pin USCI1_DAT1 I O MFP17 USCI1 data 1 pin USCI1_CTL0 I O MFP18 USCI1 control 0 pin CAN...

Page 93: ...a 1 pin USCI0_CTL0 I O MFP13 USCI0 control 0 pin USCI1_CTL1 I O MFP14 USCI1 control 1 pin USCI1_CLK I O MFP15 USCI1 clock pin USCI1_DAT0 I O MFP16 USCI1 data 0 pin USCI1_DAT1 I O MFP17 USCI1 data 1 pin USCI1_CTL0 I O MFP18 USCI1 control 0 pin CAN0_TXD O MFP19 CAN0 bus transmitter output CAN0_RXD I MFP20 CAN0 bus receiver input ACMP0_O O MFP21 Analog comparator 0 output pin ACMP1_O O MFP22 Analog c...

Page 94: ...DAT0 I O MFP16 USCI1 data 0 pin USCI1_DAT1 I O MFP17 USCI1 data 1 pin USCI1_CTL0 I O MFP18 USCI1 control 0 pin CAN0_TXD O MFP19 CAN0 bus transmitter output CAN0_RXD I MFP20 CAN0 bus receiver input ACMP0_O O MFP21 Analog comparator 0 output pin ACMP1_O O MFP22 Analog comparator 1 output pin ADC0_ST I MFP23 ADC0 external trigger input pin TM1 I O MFP24 Timer1 event counter input toggle output pin TM...

Page 95: ...mitter output CAN0_RXD I MFP20 CAN0 bus receiver input ACMP0_O O MFP21 Analog comparator 0 output pin ACMP1_O O MFP22 Analog comparator 1 output pin ADC0_ST I MFP23 ADC0 external trigger input pin TM0 I O MFP24 Timer0 event counter input toggle output pin TM2 I O MFP25 Timer2 event counter input toggle output pin TM0_EXT I O MFP26 Timer0 external capture input toggle output pin TM2_EXT I O MFP27 T...

Page 96: ... ADC0 external trigger input pin TM1 I O MFP24 Timer1 event counter input toggle output pin TM3 I O MFP25 Timer3 event counter input toggle output pin TM1_EXT I O MFP26 Timer1 external capture input toggle output pin TM3_EXT I O MFP27 Timer3 external capture input toggle output pin UART1_TXD O MFP28 UART1 data transmitter output pin UART1_RXD I MFP29 UART1 data receiver input pin INT5 I MFP30 Exte...

Page 97: ...RT0_TXD O MFP3 UART0 data transmitter output pin USCI0_CLK I O MFP4 USCI0 clock pin TM0 I O MFP5 Timer0 event counter input toggle output pin PD 5 PD 5 I O MFP0 General purpose digital I O pin PWM0_CH1 I O MFP2 PWM0 channel 1 output capture input UART0_RXD I MFP3 UART0 data receiver input pin USCI0_DAT0 I O MFP4 USCI0 data 0 pin TM1 I O MFP5 Timer1 event counter input toggle output pin PD 6 PD 6 I...

Page 98: ...M0A21 M0A23 Series May 06 2022 Page 98 of 746 Rev 1 02 M0A21 M0A23 SERIES TECHNICAL REFERENCE MANUAL 5 BLOCK DIAGRAM Figure 4 2 1 NuMicro M0A21 M0A23 Block Diagram ...

Page 99: ...terface Bus matrix Debug Access Port DAP Debug Cortex M0 Processor Cortex M0 Components Wakeup Interrupt Controller WIC Interrupts Serial Wire or JTAG debug port AHB Lite interface Figure 6 1 1 Functional Block Diagram The implemented device provides A low gate count processor Arm 6 M Thumb instruction set Thumb 2 technology Arm 6 M compliant 24 bit SysTick timer A 32 bit hardware multiplier Syste...

Page 100: ... Interrupt Controller WIC and providing Ultra low Power Sleep mode Debug support Four hardware breakpoints Two watchpoints Program Counter Sampling Register PCSR for non intrusive code profiling Single step and vector catch capabilities Bus interfaces Single 32 bit AMBA 3 AHB Lite system interface that provides simple integration to all system peripherals and memory Single 32 bit slave port that s...

Page 101: ...STSTS register to determine the reset source Hardware reset sources are from peripheral signals Software reset can trigger reset through setting control registers Hardware Reset Sources Power on Reset Low level on the nRESET pin Watchdog Time out Reset and Window Watchdog Reset WDT WWDT Reset Low Voltage Reset LVR Brown out Detector Reset BOD Reset CPU Lockup Reset Software Reset Sources CHIP Rese...

Page 102: ...ily In general CPU reset is used to reset Cortex M0 only the other reset sources will reset Cortex M0 and all peripherals However there are small differences between each reset source and they are listed in Table 6 2 1 Reset Sources Register POR NRESET WDT LVR BOD Lockup CHIP MCU CPU SYS_RSTSTS Bit 0 1 Bit 1 1 Bit 2 1 Bit 3 1 Bit 4 1 Bit 8 1 Bit 0 1 Bit 5 1 Bit 7 1 CHIPRST SYS_IPRST0 0 0x0 BODEN S...

Page 103: ...0x0000 0x0000 0x0000 0x0000 0x0000 WWDT_CTL 0x3F0800 0x3F0800 0x3F0800 0x3F0800 0x3F0800 0x3F0800 WWDT_STATUS 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 WWDT_CNT 0x3F 0x3F 0x3F 0x3F 0x3F 0x3F BS FMC_ISPCTL 1 Reload from CONFIG0 Reload from CONFIG0 Reload from CONFIG0 Reload from CONFIG0 Reload from CONFIG0 Reload from CONFIG0 FMC_DFBA Reload from CONFIG1 Reload from CONFIG1 Reload from CONFIG1 Relo...

Page 104: ...T Reset Waveform The special mode can enable nRESET pin function when system select other function for GPA 3 user can input special control signal for GPA 3 make system force enable nRESET pin Figure 6 2 3 shows the method of entry special mode 0 1 0 1 0 1 0x69C3 1 0 t1 t2 t3 t3 t3 t3 t3 t3 t3 x 16 t3 GPA 3 Reset signal t1 50ms min t2 120ms min t3 10ms 2 Figure 6 2 3 nRESET Reset Mode Enable Contr...

Page 105: ...eset will control the chip in reset state until the AVDD voltage rises above VLVR and the state keeps longer than De glitch time set by LVRDGSEL SYS_BODCTL 14 12 The default setting of Low Voltage Reset is enabled without De glitch function Figure 6 2 5 shows the Low Voltage Reset waveform AVDD VLVR Low Voltage Reset T1 LVRDGSEL T2 LVRDGSEL T3 LVRDGSEL LVREN 200 us Delay for LVR stable Figure 6 2 ...

Page 106: ...bility The watchdog timer WDT is widely used to check if the system works fine If the MCU is crashed or out of control it may cause the watchdog time out User may decide to enable system reset during watchdog time out to recover the system and take action for the system crash out of control after reset Software can check if the reset is caused by watchdog time out to indicate the previous reset is...

Page 107: ... power to the internal regulator which provides a fixed 1 8V power for digital operation and I O pins The outputs of internal voltage regulators LDO and VDD require an external capacitor which should be located close to the corresponding pin Figure 6 2 7 shows the NuMicro M0A21 M0A23 power distribution V DD V SS 38 4 kHz LIRC Oscillator SRAM IO Cell VDD to 1 8V LDO POR50 POR18 4 24 MHz crystal osc...

Page 108: ...LK_PWRCTL 7 CPU Run WFI Instruction Normal mode 0 0 NO Idle mode CPU enter Sleep mode 0 0 YES Power down mode CPU enters Deep Sleep mode 1 1 YES Table 6 2 3 Power Mode Difference Table There are several wake up sources in Idle mode and Power down mode Table 6 2 4 lists the available clocks for each power mode Power Mode Normal Mode Idle Mode Power Down Mode Definition CPU is in active state CPU is...

Page 109: ...T HIRC LXT LIRC HCLK PCLK ON Flash Halt 1 SLEEPDEEP SCS_SCR 2 1 2 PDEN CLK_PWRCTL 7 1 and PDWKIF CLK_PWRCTL 6 1 3 CPU executes WFI Wake up events occur LXT LIRC ON Figure 6 2 8 Power Mode State Machine 1 LXT 32768 Hz XTL ON or OFF depends on SW setting in normal mode 2 LIRC 38 4 kHz OSC ON or OFF depends on S W setting in normal mode 3 If TIMER clock source is selected as LIRC LXT and LIRC LXT is ...

Page 110: ...mer UART USCI BOD GPIO CAN and ACMP After chip enters power down the following wake up sources can wake chip up to normal mode Table 6 2 5 lists the condition about how to enter Power down mode again for each peripheral User needs to wait this condition before setting PDEN CLK_PWRCTL 7 and execute WFI to enter Power down mode Wake Up Source Wake Up Condition System Can Enter Power Down Mode Again ...

Page 111: ...ipheral The M0A21 M0A23 series only supports little endian data format Address Space Token Controllers Flash and SRAM Memory Space 0x0000_0000 0x0000_7FFF FLASH_BA FLASH Memory Space 32 Kbytes 0x2000_0000 0x2000_0FFF SRAM0_BA SRAM Memory Space 4 Kbytes Peripheral Controllers Space 0x4000_0000 0x400F_FFFF 0x4000_0000 0x4000_01FF SYS_BA System Control Registers 0x4000_0200 0x4000_02FF CLK_BA Clock C...

Page 112: ...BA CAN0 Control Registers 0x400D_0000 0x400D_0FFF USCI0_BA USCI0 Control Registers 0x400D_1000 0x400D_1FFF USCI1_BA USCI1 Control Registers System Controllers Space 0xE000_E000 0xE000_EFFF 0xE000_E010 0xE000_E0FF SCS_BA System Timer Control Registers 0xE000_E100 0xE000_ECFF SCS_BA External Interrupt Controller Control Registers 0xE000_ED00 0xE000_ED8F SCS_BA System Control Registers Table 6 2 7 Ad...

Page 113: ...al 4 Kbytes SRAM Supports byte half word word write Supports oversize response error Table 6 2 9 shows the SRAM organization of M0A21 M0A23 The address between 0x2000_1000 to 0x3FFF_FFFF is illegal memory space and chip will enter hardfault if CPU accesses these illegal memory addresses 512MB 0x2000_0000 0x3FFF_FFFF 0x2000_1000 4K byte SRAM bank0 Reserved 4K byte device Figure 6 2 9 SRAM Memory Or...

Page 114: ...nction the HIRC trim 48 MHz RC oscillator according to the accurate external 32 768 kHz crystal oscillator automatically gets accurate output frequency 0 25 deviation within all temperature ranges In HIRC case the system needs an accurate 48 MHz clock In such case if not soldering 32 768 kHz crystal or 12 MHz crystal in system user has to set REFCKSEL SYS_HIRCTRIMCTL 10 reference clock selection t...

Page 115: ...e different sequence or any other write to other address during these three data writing will abort the whole sequence All proteced control registers are noted Write Protect and add an note Note This bit is write protected Refer to the SYS_REGLCTL register in register description field 6 2 10 UART0_TXD USCI0_DAT0 Modulation with PWM This chip supports UART0_TXD USCI_DAT0 to modulate with PWM chann...

Page 116: ... SYS_BA 0x44 R W GPIOB Multiple Function Control Register 1 0x0000_0000 SYS_GPC_MFP0 SYS_BA 0x50 R W GPIOC Multiple Function Control Register 0 0x0000_0000 SYS_GPC_MFP1 SYS_BA 0x54 R W GPIOC Multiple Function Control Register 1 0x0000_0000 SYS_GPD_MFP0 SYS_BA 0x60 R W GPIOD Multiple Function Control Register 0 0x0000_0000 SYS_GPD_MFP1 SYS_BA 0x64 R W GPIOD Multiple Function Control Register 1 0x00...

Page 117: ...M0A21 M0A23 Series May 06 2022 Page 117 of 746 Rev 1 02 M0A21 M0A23 SERIES TECHNICAL REFERENCE MANUAL SYS_PORDISAN SYS_BA 0x1EC R W Analog POR Disable Control Register 0x0000_0000 ...

Page 118: ...lue SYS_PDID SYS_BA 0x00 R Part Device Identification Number Register 0xXXXX_XXXX 1 Every part number has a unique default reset value 31 30 29 28 27 26 25 24 PDID 23 22 21 20 19 18 17 16 PDID 15 14 13 12 11 10 9 8 PDID 7 6 5 4 3 2 1 0 PDID Bits Description 31 0 PDID Part Device Identification Number Read Only This register reflects device part number code Software can read this register to identi...

Page 119: ...and chip is reset Note Write 1 to clear this bit to 0 Note 2 When CPU lockup happened under ICE is connected This flag will set to 1 but chip will not reset 7 CPURF CPU Reset Flag The CPU reset flag is set by hardware if software writes CPURST SYS_IPRST0 1 1 to reset Cortex M0 Core and Flash Memory Controller FMC 0 No reset from CPU 1 The Cortex M0 Core and FMC are reset by software setting CPURST...

Page 120: ...No reset from watchdog timer or window watchdog timer 1 The watchdog timer or window watchdog timer had issued the reset signal to reset the system Note 1 Write 1 to clear this bit to 0 Note 2 Watchdog Timer register RSTF WDT_CTL 2 bit is set if the system has been reset by WDT time out reset Window Watchdog Timer register WWDTRF WWDT_STATUS 1 bit is set if the system has been reset by WWDT time o...

Page 121: ...L register 6 5 Reserved Reserved 4 HDIV_RST HDIV Controller Reset Write Protect Set this bit to 1 will generate a reset signal to the hardware divider User need to set this bit to 0 to release from the reset state 0 Hardware divider controller normal operation 1 Hardware divider controller reset Note This bit is write protected Refer to the SYS_REGLCTL register 3 Reserved Reserved 2 PDMARST PDMA C...

Page 122: ...erals and this bit will automatically return to 0 after the 2 clock cycles The CHIPRST is same as the POR reset all the chip controllers is reset and the chip setting from Flash are also reload About the difference between CHIPRST and SYSRESETREQ AIRCR 2 please refer to section 6 2 2 0 Chip normal operation 1 Chip one shot reset Note 1 This bit is write protected Refer to the SYS_REGLCTL register ...

Page 123: ...1 0 ACMP01RST Reserved TMR3RST TMR2RST TMR1RST TMR0RST GPIORST Reserved Bits Description 31 29 Reserved Reserved 28 ADCRST ADC Controller Reset 0 ADC controller normal operation 1 ADC controller reset 27 25 Reserved Reserved 24 CAN0RST CAN0 Controller Reset 0 CAN0 controller normal operation 1 CAN0 controller reset 23 18 Reserved Reserved 17 UART1RST UART1 Controller Reset 0 UART1 controller norma...

Page 124: ...ller normal operation 1 Timer2 controller reset 3 TMR1RST Timer1 Controller Reset 0 Timer1 controller normal operation 1 Timer1 controller reset 2 TMR0RST Timer0 Controller Reset 0 Timer0 controller normal operation 1 Timer0 controller reset 1 GPIORST GPIO Controller Reset 0 GPIO controller normal operation 1 GPIO controller reset 0 Reserved Reserved ...

Page 125: ...000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved PWM0RST 15 14 13 12 11 10 9 8 Reserved DAC0RST Reserved USCI1RST USCI0RST 7 6 5 4 3 2 1 0 Reserved Bits Description 31 17 Reserved Reserved 16 PWM0RST PWM0 Controller Reset 0 PWM0 controller normal operation 1 PWM0 controller reset 15 13 Reserved Reserved 12 DAC0RST DAC0 Controller Reset 0 DAC0 controller normal operation 1...

Page 126: ...17 16 BODVL Brown out Detector Threshold Voltage Selection Write Protect The default value is set by Flash controller user configuration register CBOV CONFIG0 22 21 00 Brown Out Detector threshold voltage is 2 3V 01 Brown Out Detector threshold voltage is 2 7V 10 Brown Out Detector threshold voltage is 3 7V 11 Brown Out Detector threshold voltage is 4 4V Note This bit is write protected Refer to t...

Page 127: ...EGLCTL register 6 BODOUT Brown out Detector Output Status 0 Brown out Detector output status is 0 It means the detected voltage is higher than BODVL setting or BODEN is 0 1 Brown out Detector output status is 1 It means the detected voltage is lower than BODVL setting If the BODEN is 0 BOD function disabled this bit always responds 0000 5 BODLPM Brown out Detector Low Power Mode Write Protect 0 BO...

Page 128: ...BODOUT high While the BOD function is enabled BODEN high and BOD interrupt function is enabled BODRSTEN low BOD will assert an interrupt if BODOUT is high BOD interrupt will keep till to the BODEN set to 0 BOD interrupt can be blocked by disabling the NVIC BOD interrupt or disabling BOD function set BODEN low Note 2 This bit is write protected Refer to the SYS_REGLCTL register Note 3 Reset by powr...

Page 129: ... 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 Reserved VTEMPEN Bits Description 31 2 Reserved Reserved 0 VTEMPEN Temperature Sensor Enable Bit This bit is used to enable disable temperature sensor function 0 Temperature sensor function Disabled default 1 Temperature sensor function Enabled Note After this bit is set to 1 the value of temperature senso...

Page 130: ...rved Reserved 15 0 POROFF Power on Reset Enable Bit Write Protect When powered on the POR circuit generates a reset signal to reset the whole chip function but noise on the power may cause the POR active again User can disable internal POR circuit to avoid unpredictable noise to cause chip reset by writing 0x5AA5 to this field The POR function will be active again when this field is set to another...

Page 131: ...oad time is 310us for 1uF Capacitor Note These bits is write protected Refer to the SYS_REGLCTL register 5 Reserved Reserved 4 ADCPRESEL ADC Voltage Reference 0 ADC positive reference voltage comes from AVDD voltage of VDD pin 1 ADC positive reference voltage comes from internal or external VREF Note These bits is write protected Refer to the SYS_REGLCTL register 3 0 VREFCTL VREF Control Bits Writ...

Page 132: ...S_GPA_MFP0 SYS_BA 0x30 R W GPIOA Multiple Function Control Register 0 0x0000_0202 31 30 29 28 27 26 25 24 GPA3MFP 23 22 21 20 19 18 17 16 GPA2MFP 15 14 13 12 11 10 9 8 GPA1MFP 7 6 5 4 3 2 1 0 GPA0MFP Bits Description 31 24 GPA3MFP PA 3 Multi function Pin Selection 23 16 GPA2MFP PA 2 Multi function Pin Selection 15 8 GPA1MFP PA 1 Multi function Pin Selection 7 0 GPA0MFP PA 0 Multi function Pin Sele...

Page 133: ...fset R W Description Reset Value SYS_GPA_MFP1 SYS_BA 0x34 R W GPIOA Multiple Function Control Register 1 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 GPA5MFP 7 6 5 4 3 2 1 0 GPA4MFP Bits Description 30 16 Reserved Reserved 15 8 GPA5MFP PA 5 Multi function Pin Selection 7 0 GPA4MFP PA 4 Multi function Pin Selection ...

Page 134: ...S_GPB_MFP1 SYS_BA 0x44 R W GPIOB Multiple Function Control Register 1 0x0000_0000 31 30 29 28 27 26 25 24 GPB7MFP 23 22 21 20 19 18 17 16 GPB6MFP 15 14 13 12 11 10 9 8 GPB5MFP 7 6 5 4 3 2 1 0 GPB4MFP Bits Description 31 24 GPB7MFP PB 7 Multi function Pin Selection 23 16 GPB6MFP PB 6 Multi function Pin Selection 15 8 GPB5MFP PB 5 Multi function Pin Selection 7 0 GPB4MFP PB 4 Multi function Pin Sele...

Page 135: ...YS_GPC_MFP0 SYS_BA 0x50 R W GPIOC Multiple Function Control Register 0 0x0000_0000 31 30 29 28 27 26 25 24 GPC3MFP 23 22 21 20 19 18 17 16 GPC2MFP 15 14 13 12 11 10 9 8 GPC1MFP 7 6 5 4 3 2 1 0 GPC0MFP Bits Description 31 24 GPC3MFP PC3 Multi function Pin Selection 23 16 GPC2MFP PC 2 Multi function Pin Selection 15 8 GPC1MFP PC 1 Multi function Pin Selection 7 0 GPC0MFP PC 0 Multi function Pin Sele...

Page 136: ...YS_GPC_MFP1 SYS_BA 0x54 R W GPIOC Multiple Function Control Register 1 0x0000_0000 31 30 29 28 27 26 25 24 GPC7MFP 23 22 21 20 19 18 17 16 GPC6MFP 15 14 13 12 11 10 9 8 GPC5MFP 7 6 5 4 3 2 1 0 GPC4MFP Bits Description 31 24 GPC7MFP PC 7Multi function Pin Selection 23 16 GPC6MFP PC 6 Multi function Pin Selection 15 8 GPC5MFP PC 5 Multi function Pin Selection 7 0 GPC4MFP PC 4 Multi function Pin Sele...

Page 137: ...YS_GPD_MFP0 SYS_BA 0x60 R W GPIOD Multiple Function Control Register 0 0x0000_0000 31 30 29 28 27 26 25 24 GPD3MFP 23 22 21 20 19 18 17 16 GPD2MFP 15 14 13 12 11 10 9 8 GPD1MFP 7 6 5 4 3 2 1 0 GPD0MFP Bits Description 31 24 GPD3MFP PD3 Multi function Pin Selection 23 16 GPD2MFP PD 2 Multi function Pin Selection 15 8 GPD1MFP PD 1 Multi function Pin Selection 7 0 GPD0MFP PD 0 Multi function Pin Sele...

Page 138: ...YS_GPD_MFP1 SYS_BA 0x64 R W GPIOD Multiple Function Control Register 1 0x0000_0000 31 30 29 28 27 26 25 24 GPD7MFP 23 22 21 20 19 18 17 16 GPD6MFP 15 14 13 12 11 10 9 8 GPD5MFP 7 6 5 4 3 2 1 0 GPD4MFP Bits Description 31 24 GPD7MFP PD 7Multi function Pin Selection 23 16 GPD6MFP PD 6 Multi function Pin Selection 15 8 GPD5MFP PD 5 Multi function Pin Selection 7 0 GPD4MFP PD 4 Multi function Pin Sele...

Page 139: ...S_GPD_MFOS SYS_BA 0xBC R W GPIOD Multiple Function Output Select Register 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 MFOS 7 6 5 4 3 2 1 0 MFOS Bits Description 31 16 Reserved Reserved n n 0 1 15 MFOS GPIOA h Pin n Multiple Function Pin Output Mode Select This bit used to select multiple function pin output mode type for Px n pin 0 Multiple f...

Page 140: ...SRAM BIST Test Control Register 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 PDMABIST Reserved Bits Description 31 8 Reserved Reserved 7 PDMABIST PDMA BIST Enable Bit Write Protect This bit enables BIST test for PDMA RAM 0 system PDMA BIST Disabled 1 system PDMA BIST Enabled Note This bit is write protected Refer to th...

Page 141: ... BIST Test Status Register 0x00xx_00xx 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 PDMAEND Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 PDMABISTF Reserved Bits Description 31 24 Reserved Reserved 23 PDMAEND PDMA SRAM BIST Test Finish 0 PDMA SRAM BIST is active 1 PDMA SRAM BIST test finished 22 8 Reserved Reserved 7 PDMABISTF PDMA SRAM BIST Failed Flag 0 PDMA SRAM BIST pass ...

Page 142: ...nnel 3 modulete with UART0_TXD 0100 PWM0 Channel 4 modulete with UART0_TXD 0101 PWM0 Channel 5 modulete with UART0_TXD 0110 Reserved 0111 Reserved 1000 PWM0 Channel 0 modulate with USCI0_DAT0 1001 PWM0 Channel 1 modulate with USCI0_DAT0 1010 PWM0 Channel 2 modulate with USCI0_DAT0 1011 PWM0 Channel 3 modulete with USCI0_DAT0 1100 PWM0 Channel 4 modulete with USCI0_DAT0 1101 PWM0 Channel 5 modulete...

Page 143: ...M0A21 M0A23 Series May 06 2022 Page 143 of 746 Rev 1 02 M0A21 M0A23 SERIES TECHNICAL REFERENCE MANUAL 0 Modulation Function Disabled 1 Modulation Function Enabled ...

Page 144: ... is no reference clock LXT when the rc_trim is enabled CLKERIF SYS_HIRCTRIMCTL 2 will be set to 1 9 BOUNDEN Boundary Enable Bit 0 Boundary function Disabled 1 Boundary function Enabled 8 CESTOPEN Clock Error Stop Enable Bit 0 The trim operation is keep going if clock is inaccuracy 1 The trim operation is stopped if clock is inaccuracy 7 6 RETRYCNT Trim Value Update Limitation Count This field defi...

Page 145: ...lculation is based on average difference in 32 clocks of reference clock Note For example if LOOPSEL is set as 00 auto trim circuit will calculate trim value based on the average frequency difference in 4 clocks of reference clock 3 2 Reserved Reserved 1 0 FREQSEL Trim Frequency Selection This field indicates the target frequency of 48 MHz internal high speed RC oscillator HIRC auto trim During au...

Page 146: ...RIMSTS 2 is set during auto trim operation an interrupt will be triggered to notify the clock frequency is inaccuracy 0 Disable CLKERRIF SYS_HIRCTRIMSTS 2 status to trigger an interrupt to CPU 1 Enable CLKERRIF SYS_HIRCTRIMSTS 2 status to trigger an interrupt to CPU 1 TFALIEN Trim Failure Interrupt Enable Bit This bit controls if an interrupt will be triggered while HIRC trim value update limitati...

Page 147: ...s set to 1 the auto trim operation stopped and FREQSEL SYS_HIRCTRIMCTL 1 0 will be cleared to 00 by hardware automatically if CESTOPEN SYS_HIRCTRIMCTL 8 is set to 1 If this bit is set and CLKEIEN SYS_HIRCTIEN 2 is high an interrupt will be triggered to notify the clock frequency is inaccuracy Write 1 to clear this to 0 0 Clock frequency is accuracy 1 Clock frequency is inaccuracy Note reset by pow...

Page 148: ...RENCE MANUAL Write 1 to clear this to 0 This bit will be set automatically if the frequecy is lock and the RC_TRIM is enabled 0 The internal high speed oscillator frequency doesn t lock at 48 MHz yet 1 The internal high speed oscillator frequency locked at 48 MHz Note Reset by powr on reset ...

Page 149: ...on disable and 0 is protection enable Then user can update the target protected register value and then write any data to the address 0x4000_0100 to enable register protection This register is writen to disable enable register protection and read for the REGLCTL status Register Offset R W Description Reset Value SYS_REGLCTL SYS_BA 0x100 R W Register Lock Control Register 0x0000_0000 31 30 29 28 27...

Page 150: ... 13 12 11 10 9 8 POROFFAN 7 6 5 4 3 2 1 0 POROFFAN Bits Description 31 16 Reserved Reserved 15 0 POROFFAN Power on Reset Enable Bit Write Protect After powered on User can turn off internal analog POR circuit to save power by writing 0x5AA5 to this field The analog POR circuit will be active again when this field is set to another value or chip is reset by other reset source including nRESET Watch...

Page 151: ...alue Register SYST_LOAD on the next clock cycle and then decrement on subsequent clocks When the counter transitions to zero the COUNTFLAG status bit is set The COUNTFLAG bit clears on reads The SYST_VAL value is UNKNOWN on reset Software should write to the register to clear it to zero before enabling the feature This ensures the timer will count from the SYST_LOAD value rather than an arbitrary ...

Page 152: ... read only W write only R W both read and write Register Offset R W Description Reset Value SYST Base Address SCS_BA 0xE000_E000 SYST_CTRL SCS_BA 0x10 R W SysTick Control and Status Register 0x0000_0000 SYST_LOAD SCS_BA 0x14 R W SysTick Reload Value Register 0xXXXX_XXXX SYST_VAL SCS_BA 0x18 R W SysTick Current Value Register 0xXXXX_XXXX ...

Page 153: ...nce last time this register was read COUNTFLAG is set by a count transition from 1 to 0 COUNTFLAG is cleared on read or by a write to the Current Value register 15 3 Reserved Reserved 2 CLKSRC System Tick Clock Source Selection 0 Clock source is the optional external reference clock 1 Core clock used for SysTick 1 TICKINT System Tick Interrupt Enabled 0 Counting down to 0 does not cause the SysTic...

Page 154: ... Description Reset Value SYST_LOAD SCS_BA 0x14 R W SysTick Reload Value Register 0xXXXX_XXXX 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 RELOAD 15 14 13 12 11 10 9 8 RELOAD 7 6 5 4 3 2 1 0 RELOAD Bits Description 31 24 Reserved Reserved 23 0 RELOAD System Tick Reload Value The value to load into the Current Value register when the counter reaches 0 ...

Page 155: ...ter 0xXXXX_XXXX 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 CURRENT 15 14 13 12 11 10 9 8 CURRENT 7 6 5 4 3 2 1 0 CURRENT Bits Description 31 24 Reserved Reserved 23 0 CURRENT System Tick Current Value Current counter value This is the value of the counter at the time it is sampled The counter does not provide read modify write protection The register is write clear A software write o...

Page 156: ...the registers PC PSR LR R0 R3 R12 to the stack At the end of the ISR the NVIC will restore the mentioned registers from stack and resume the normal execution Thus it will take less and deterministic time to process the interrupt request The NVIC supports Tail Chaining which handles back to back interrupts efficiently without the overhead of states saving and restoration and therefore reduces delay...

Page 157: ...5 20 4 GPAB_INT External interrupt from PA PB pin 21 5 GPCD_INT External interrupt from PC PD pin 22 6 PWM0_INT PWM0 interrupt 23 7 Reserved Reserved 24 8 TMR0_INT Timer 0 interrupt 25 9 TMR1_INT Timer 1 interrupt 26 10 TMR2_INT Timer 2 interrupt 27 11 TMR3_INT Timer 3 interrupt 28 12 UART0_INT UART0 interrupt 29 13 UART1_INT UART1 interrupt 30 14 Reserved Reserved 31 15 CAN0_INT CAN0 interrupt 32...

Page 158: ...d disabled by writing to their corresponding Interrupt Set Enable or Interrupt Clear Enable register bit field The registers use a write 1 to enable and write 1 to clear policy both registers reading back the current enabled state of the corresponding interrupts When an interrupt is disabled interrupt assertion will cause the interrupt to become Pending however the interrupt will not be activated ...

Page 159: ...le Control Register 0x0000_0000 NVIC_ICER0 NVIC_BA 0x080 R W IRQ0 IRQ31 Clear enable Control Register 0x0000_0000 NVIC_ISPR0 NVIC_BA 0x100 R W IRQ0 IRQ31 Set pending Control Register 0x0000_0000 NVIC_ICPR0 NVIC_BA 0x180 R W IRQ0 IRQ31 Clear pending Control Register 0x0000_0000 NVIC_IABR0 NVIC_BA 0x200 R W IRQ0 IRQ31 Active Bit Register 0x0000_0000 NVIC_IPRn n 0 1 7 0xE000E400 0x4 n R W IRQ0 IRQ31 ...

Page 160: ...A 0x000 R W IRQ0 IRQ31 Set enable Control Register 0x0000_0000 31 30 29 28 27 26 25 24 SETENA 23 22 21 20 19 18 17 16 SETENA 15 14 13 12 11 10 9 8 SETENA 7 6 5 4 3 2 1 0 SETENA Bits Description 31 0 SETENA Interrupt Set Enable Bit The NVIC_ISER0 registers enable interrupts and show which interrupts are enabled Write Operation 0 No effect 1 Interrupt Enabled Read Operation 0 Interrupt Disabled 1 In...

Page 161: ...0x080 R W IRQ0 IRQ31 Clear enable Control Register 0x0000_0000 31 30 29 28 27 26 25 24 CALENA 23 22 21 20 19 18 17 16 CALENA 15 14 13 12 11 10 9 8 CALENA 7 6 5 4 3 2 1 0 CALENA Bits Description 31 0 CALENA Interrupt Clear Enable Bit The NVIC_ICER0 registers disable interrupts and show which interrupts are enabled Write Operation 0 No effect 1 Interrupt Disabled Read Operation 0 Interrupt Disabled ...

Page 162: ...t pending Control Register 0x0000_0000 31 30 29 28 27 26 25 24 SETPEND 23 22 21 20 19 18 17 16 SETPEND 15 14 13 12 11 10 9 8 SETPEND 7 6 5 4 3 2 1 0 SETPEND Bits Description 31 0 SETPEND Interrupt Set pending The NVIC_ISPR0 registers force interrupts into the pending state and show which interrupts are pending Write Operation 0 No effect 1 Changes interrupt state to pending Read Operation 0 Interr...

Page 163: ...r pending Control Register 0x0000_0000 31 30 29 28 27 26 25 24 CALPEND 23 22 21 20 19 18 17 16 CALPEND 15 14 13 12 11 10 9 8 CALPEND 7 6 5 4 3 2 1 0 CALPEND Bits Description 31 0 CALPEND Interrupt Clear pending The NVIC_ICPR0 registers remove the pending state from interrupts and show which interrupts are pending Write Operation 0 No effect 1 Removes pending state an interrupt Read Operation 0 Int...

Page 164: ...Description Reset Value NVIC_IABR0 NVIC_BA 0x200 R W IRQ0 IRQ31 Active Bit Register 0x0000_0000 31 30 29 28 27 26 25 24 ACTIVE 23 22 21 20 19 18 17 16 ACTIVE 15 14 13 12 11 10 9 8 ACTIVE 7 6 5 4 3 2 1 0 ACTIVE Bits Description 31 0 ACTIVE Interrupt Active Flags The NVIC_IABR0 registers indicate which interrupts are active 0 interrupt not active 1 interrupt active ...

Page 165: ... 12 11 10 9 8 PRI_4n_1 Reserved 7 6 5 4 3 2 1 0 PRI_4n_0 Reserved Bits Description 31 30 PRI_4n_3 Priority of IRQ_4n 3 0 denotes the highest priority and 3 denotes the lowest priority 29 24 Reserved Reserved 23 22 PRI_4n_2 Priority of IRQ_4n 2 0 denotes the highest priority and 3 denotes the lowest priority 21 16 Reserved Reserved 15 14 PRI_4n_1 Priority of IRQ_4n 1 0 denotes the highest priority ...

Page 166: ...0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved INTID 7 6 5 4 3 2 1 0 INTID Bits Description 31 9 Reserved Reserved 8 0 INTID Interrupt ID Write to the STIR To Generate An Interrupt from Software When the USERSETMPEND bit in the SCR is set to 1 unprivileged software can access the STIR Interrupt ID of the interrupt to trigger in the range 0 31 ...

Page 167: ...ANUAL NMI Control Registers R read only W write only R W both read and write Register Offset R W Description Reset Value NMI Base Address NMI_BA 0x4000_0300 NMIEN NMI_BA 0x00 R W NMI Source Interrupt Enable Register 0x0000_0000 NMISTS NMI_BA 0x04 R NMI Source Interrupt Status Register 0x0000_0000 ...

Page 168: ...T5 External Interrupt From PC 7 Pin NMI Source Enable Write Protect 0 External interrupt from PC 7 pin NMI source Disabled 1 External interrupt from PC 7 pin NMI source Enabled Note This bit is write protected Refer to the SYS_REGLCTL register 12 EINT4 External Interrupt From PC 6 Pin NMI Source Enable Write Protect 0 External interrupt from PC 6 pin NMI source Disabled 1 External interrupt from P...

Page 169: ...upt NMI Source Enable Write Protect 0 Clock fail detected and IRC Auto Trim interrupt NMI source Disabled 1 Clock fail detected and IRC Auto Trim interrupt NMI source Enabled Note This bit is write protected Refer to the SYS_REGLCTL register 3 Reserved Reserved 2 PWRWU_INT Power down Mode Wake up NMI Source Enable Write Protect 0 Power down mode wake up NMI source Disabled 1 Power down mode wake u...

Page 170: ...upt from PC 7 interrupt is deasserted 1 External Interrupt from PC 7 interrupt is asserted 12 EINT4 External Interrupt From PC 6 Pin Interrupt Flag Read Only 0 External Interrupt from PC 6 interrupt is deasserted 1 External Interrupt from PC 6 interrupt is asserted 11 EINT3 External Interrupt From PC 3 Pin Interrupt Flag Read Only 0 External Interrupt from PC 3 interrupt is deasserted 1 External I...

Page 171: ...ck fail detected or IRC Auto Trim interrupt is asserted 3 Reserved Reserved 2 PWRWU_INT Power down Mode Wake up Interrupt Flag Read Only 0 Power down mode wake up interrupt is deasserted 1 Power down mode wake up interrupt is asserted 1 IRC_INT IRC TRIM Interrupt Flag Read Only 0 HIRC TRIM interrupt is deasserted 1 HIRC TRIM interrupt is asserted 0 BODOUT BOD Interrupt Flag Read Only 0 BOD interru...

Page 172: ...rm v6 M Architecture Reference Manual R read only W write only R W both read and write Register Offset R W Description Reset Value SCR Base Address SCS_BA 0xE000_E000 ICSR SCS_BA 0xD04 R W Interrupt Control and State Register 0x0000_0000 VTOR SCS_BA 0xD08 R W Vector Table Offset Register 0x0000_0000 AIRCR SCS_BA 0xD0C R W Application Interrupt and Reset Control Register 0xFA05_0000 SCR SCS_BA 0xD1...

Page 173: ...ote Because NMI is the highest priority exception normally the processor enters the NMI exception handler as soon as it detects a write of 1 to this bit Entering the handler then clears this bit to 0 This means a read of this bit by the NMI exception handler returns 1 only if the NMI signal is reasserted while the processor is executing that handler 30 29 Reserved Reserved 28 PENDSVSET PendSV Set ...

Page 174: ...ENDING Interrupt Pending Flag Excluding NMI and Faults Read Only 0 Interrupt not pending 1 Interrupt pending 21 18 Reserved Reserved 17 12 VECTPENDING Number of the Highest Pended Exception Indicate the Exception Number of the Highest Priority Pending Enabled Exception 0 no pending exceptions Nonzero the exception number of the highest priority pending enabled exception The value indicated by this...

Page 175: ...Offset R W Description Reset Value VTOR SCS_BA 0xD08 R W Vector Table Offset Register 0x0000_0000 31 30 29 28 27 26 25 24 TBLOFF 23 22 21 20 19 18 17 16 TBLOFF 15 14 13 12 11 10 9 8 TBLOFF 7 6 5 4 3 2 1 0 TBLOFF Reserved Bits Description 31 7 TBLOFF Table Offset Bits The vector table address for the selected Security state 6 0 Reserved Reserved ...

Page 176: ...sed to prevent accidental write to this register from resetting the system or clearing of the exception status 15 ENDIANNESS Data Endianness 0 Little endian 1 Big endian 14 11 Reserved Reserved 10 8 PRIGROUP Interrupt Priority Grouping This field determines the Split Of Group priority from subpriority 7 3 Reserved Reserved 2 SYSRESETREQ System Reset Request Writing This Bit to 1 Will Cause A Reset...

Page 177: ...ty Bits Subpriority Bits Number Of Group Priorities Subpriorities 0b000 bxxxxxxx y 7 1 0 128 2 0b001 bxxxxxx yy 7 2 1 0 64 4 0b010 bxxxxx yyy 7 3 2 0 32 8 0b011 bxxxx yyyy 7 4 3 0 16 16 0b100 bxxx yyyyy 7 5 4 0 8 32 0b101 bxx yyyyyy 7 6 5 0 4 64 0b110 bx yyyyyyy 7 6 0 2 128 0b111 b yyyyyyyy None 7 0 1 256 Table 6 2 10 Priority Grouping ...

Page 178: ... can wake up the processor When an event or interrupt enters pending state the event signal wakes up the processor from WFE If the processor is not waiting for an event the event is registered and affects the next WFE The processor also wakes up on execution of an SEV instruction or an external event 3 Reserved Reserved 2 SLEEPDEEP Processor Deep Sleep and Sleep Mode Selection Control Whether the ...

Page 179: ...t Value SHPR1 SCS_BA 0xD18 R W System Handler Priority Register 1 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 PRI_6 15 14 13 12 11 10 9 8 PRI_5 7 6 5 4 3 2 1 0 PRI_4 Bits Description 31 24 Reserved Reserved 23 16 PRI_6 Priority of system handler 6 UsageFault 15 8 PRI_5 Priority of system handler 5 BusFault 7 0 PRI_4 Priority of system handler 4 MemManage ...

Page 180: ...ption Reset Value SHPR2 SCS_BA 0xD1C R W System Handler Priority Register 2 0x0000_0000 31 30 29 28 27 26 25 24 PRI_11 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 Reserved Bits Description 31 30 PRI_11 Priority of System Handler 11 SVCall 0 denotes the highest priority and 3 denotes the lowest priority 29 0 Reserved Reserved ...

Page 181: ...ty Register 3 0x0000_0000 31 30 29 28 27 26 25 24 PRI_15 Reserved 23 22 21 20 19 18 17 16 PRI_14 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 Reserved Bits Description 31 30 PRI_15 Priority of System Handler 15 SysTick 0 denotes the highest priority and 3 denotes the lowest priority 29 24 Reserved Reserved 23 22 PRI_14 Priority of System Handler 14 PendSV 0 denotes the highest priority ...

Page 182: ... selection and a clock divider The chip will not enter Power down mode until CPU sets the Power down enable bit PDEN CLK_PWRCTL 7 and Cortex M0 core executes the WFI instruction After that chip enters Power down mode and wait for wake up interrupt source triggered to leave Power down mode In Power down mode the clock controller turns off the 4 24 MHz external high speed crystal HXT and 48 MHz inte...

Page 183: ... HCLK LIRC HIRC ADC HXT HIRC 1 ADCDIV 1 PCLK1 CLKSEL2 21 20 11 10 00 HDIV USCI0 WDT UART0 HXT CLK_CLKSEL1 26 24 1 UART0DIV 1 000 010 011 100 101 LXT HIRC PCLK0 PCLK1 LIRC PCLK0 GPIO 111 010 001 000 PCLK0 LXT HXT HIRC CLK_CLKSEL1 10 8 CLK_CLKSEL1 14 12 101 LIRC 011 TM0 TM1 TMR0 TMR1 111 010 001 000 PCLK1 LXT HXT HIRC 101 LIRC 011 TM2 TM3 TMR2 TMR3 CLK_CLKSEL1 18 16 CLK_CLKSEL1 22 20 CKO UART1 1 UAR...

Page 184: ...UAL XT1_OUT External 4 24 MHz Crystal HXT HXTEN CLK_PWRCTL 0 XT1_IN Internal 48 MHz Oscillator HIRC HIRCEN CLK_PWRCTL 2 X32_OUT External 32 768 kHz Crystal LXT LXT LXTEN CLK_PWRCTL 1 X32_IN Internal 38 4 kHz Oscillator LIRC LIRCEN CLK_PWRCTL 3 HXT HIRC LIRC Figure 6 3 2 Clock Generator Block Diagram ...

Page 185: ...individual enable and interrupt control When HXT detector is enabled the HIRC clock is enabled automatically When LXT detector is enabled the LIRC clock is enabled automatically When HXT clock detector is enabled the system clock will auto switch to HIRC if HXT clock stop being detected on the following condition system clock source comes from HXT If HXT clock stop condition is detected the HXTFIF...

Page 186: ... SYST_CTRL 2 If using external clock the SysTick clock STCLK has 5 clock sources The clock source switch depends on the setting of the register STCLKSEL CLK_CLKSEL0 5 3 The block diagram is shown in Figure 6 3 5 111 011 010 001 HXT LXT HXT HCLK STCLKSEL CLK_CLKSEL0 5 3 STCLK HIRC 000 1 2 1 2 1 2 Figure 6 3 5 SysTick Clock Control Block Diagram 6 3 4 Peripherals Clock The peripherals clock has diff...

Page 187: ...cted by a sixteen to one multiplexer is reflected to CLKO function pin Therefore there are 16 options of power of 2 divided clocks with the frequency from Fin 21 to Fin 216 where Fin is input clock frequency to the clock divider The output formula is Fout Fin 2 N 1 where Fin is the input clock frequency Fout is the clock divider output frequency and N is the 4 bit value in FREQSEL CLK_CLKOCTL 3 0 ...

Page 188: ...3F CLK_CLKSEL1 CLK_BA 0x14 R W Clock Source Select Control Register 1 0x4477_773B CLK_CLKSEL2 CLK_BA 0x18 R W Clock Source Select Control Register 2 0x0020_032B CLK_CLKDIV0 CLK_BA 0x20 R W Clock Divider Number Register 0 0x0000_0000 CLK_PCLKDIV CLK_BA 0x34 R W APB Clock Divider Register 0x0000_0000 CLK_STATUS CLK_BA 0x50 R Clock Status Monitor Register 0x0000_00XX CLK_CLKOCTL CLK_BA 0x60 R W Clock...

Page 189: ...ic Note This bit is write protected Refer to the SYS_REGLCTL register 27 LXTSELXT LXT Crystal Mode Selection 0 LXT works as external clock mode PC 5 is configured as external clock input pin 1 LXT works as crystal mode PC 4 and PC 5 are configured as low speed crystal LXT pins Note 1 When LXTSELXT 0 PC 4 MFP should be set as GPIO mode The DC characteristic of X32_OUT is the same as GPIO Note 2 Thi...

Page 190: ...Y Enable the Wake up Delay Counter Write Protect When the chip wakes up from Power down mode the clock control will delay certain clock cycles to wait system clock stable The delayed clock cycle is 4096 clock cycles when chip works at external high speed crystal oscillator HXT and 512 clock cycles when chip works at internal high speed RC oscillator HIRC 0 Clock cycles delay Disabled 1 Clock cycle...

Page 191: ...rved 7 6 5 4 3 2 1 0 CRCCKEN Reserved HDIV_EN Reserved ISPCKEN PDMACKEN Reserved Bits Description 31 8 Reserved Reserved 7 CRCCKEN CRC Generator Controller Clock Enable Bit 0 CRC peripheral clock Disabled 1 CRC peripheral clock Enabled 6 5 Reserved Reserved 4 HDIV_EN Divider Controller Clock Enable Control 0 Divider controller peripheral clock Disabled 1 Divider controller peripheral clock Enabled...

Page 192: ...MR3CKEN TMR2CKEN TMR1CKEN TMR0CKEN Reserved WDTCKEN Bits Description 31 29 Reserved Reserved 28 ADCCKEN Analog digital converter Clock Enable Bit 0 ADC clock Disabled 1 ADC clock Enabled 27 25 Reserved Reserved 24 CAN0CKEN CAN0 Clock Enable Bit 0 CAN0 clock Disabled 1 CAN0 clock Enabled 23 18 Reserved Reserved 17 UART1CKEN UART1 Clock Enable Bit 0 UART1 clock Disabled 1 UART1 clock Enabled 16 UART...

Page 193: ...k Enable Bit 0 Timer1 clock Disabled 1 Timer1 clock Enabled 2 TMR0CKEN Timer0 Clock Enable Bit 0 Timer0 clock Disabled 1 Timer0 clock Enabled 1 Reserved Reserved 0 WDTCKEN Watchdog Timer Clock Enable Bit Write Protect 0 Watchdog timer clock Disabled 1 Watchdog timer clock Enabled Note 1 This bit is write protected Refer to the SYS_REGLCTL register Note 2 This bit is reset by power on reset Watchdo...

Page 194: ...0 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved PWM0CKEN 15 14 13 12 11 10 9 8 Reserved DACCKEN Reserved USCI1CKEN USCI0CKEN 7 6 5 4 3 2 1 0 Reserved Bits Description 31 17 Reserved Reserved 16 PWM0CKEN PWM0 Clock Enable Bit 0 PWM0 clock Disabled 1 PWM0 clock Enabled 15 13 Reserved Reserved 12 DACCKEN DAC Clock Enable Bit 0 DAC clock Disabled 1 DAC clock Enabled 11 10 Reserved Reserv...

Page 195: ...k uses listed clock source below 000 Clock source from HXT 001 Clock source from LXT 010 Clock source from HXT 2 011 Clock source from HCLK 2 111 Clock source from HIRC 2 Other Reserved Note 1 If SysTick clock source is not from HCLK i e SYST_CTRL 2 0 SysTick clock source must less than or equal to HCLK 2 Note 2 This bit is write protected Refer to the SYS_REGLCTL register 2 0 HCLKSEL HCLK Clock S...

Page 196: ... external low speed crystal oscillator LXT 011 Clock source from internal high speed RC oscillator HIRC 100 Clock source from PCLK1 101 Clock source from internal low speed RC oscillator LIRC Other Reserved 27 Reserved Reserved 26 24 UART0SEL UART0 Clock Source Selection 000 Clock source from external high speed crystal oscillator HXT 010 Clock source from external low speed crystal oscillator LXT...

Page 197: ...eed crystal oscillator HXT 001 Clock source from external low speed crystal oscillator LXT 010 Clock source from PCLK0 011 Clock source from external clock T0 pin 101 Clock source from internal low speed RC oscillator LIRC 111 Clock source from internal high speed RC oscillator HIRC Others Reserved 7 Reserved Reserved 6 4 CLKOSEL Clock Divider Clock Source Selection 000 Clock source from external ...

Page 198: ...K_CLKSEL2 CLK_BA 0x18 R W Clock Source Select Control Register 2 0x0020_032B 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved ADCSEL Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 Reserved Bits Description 31 22 Reserved Reserved 21 20 ADCSEL ADC Clock Source Selection 00 Clock source from external high speed crystal oscillator HXT clock 01 Reserved 10 Clock source from P...

Page 199: ... 3 2 1 0 Reserved HCLKDIV Bits Description 31 24 Reserved Reserved 23 16 ADCDIV ADC Clock Divide Number From ADC Clock Source ADC clock frequency ADC clock source frequency ADCDIV 1 15 12 UART1DIV UART1 Clock Divide Number From UART1 Clock Source UART1 clock frequency UART1 clock source frequency UART1DIV 1 11 8 UART0DIV UART0 Clock Divide Number From UART0 Clock Source UART0 clock frequency UART0...

Page 200: ...17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 Reserved APB1DIV Reserved APB0DIV Bits Description 31 7 Reserved Reserved 6 4 APB1DIV APB1 Clock DIvider APB1 clock can be divided from HCLK 000 PCLK1 HCLK 001 PCLK1 1 2 HCLK 010 PCLK1 1 4 HCLK 011 PCLK1 1 8 HCLK 100 PCLK1 1 16 HCLK Others Reserved 3 Reserved Reserved 2 0 APB0DIV APB0 Clock DIvider APB0 clock can be divided from HCLK 00...

Page 201: ...switch target clock is not stable this bit will be set to 1 0 Clock switching success 1 Clock switching failure Note Write 1 to clear the bit to 0 6 5 Reserved Reserved 4 HIRCSTB HIRC Clock Source Stable Flag Read Only 0 Internal high speed RC oscillator HIRC clock is not stable or disabled 1 Internal high speed RC oscillator HIRC clock is stable and enabled 3 LIRCSTB LIRC Clock Source Stable Flag...

Page 202: ... 4 3 2 1 0 Reserved DIV1EN CLKOEN FREQSEL Bits Description 31 6 Reserved Reserved 5 DIV1EN Clock Output Divide One Enable Bit 0 Clock Output will output clock with source frequency divided by FREQSEL 1 Clock Output will output clock with source frequency 4 CLKOEN Clock Output Enable Bit 0 Clock Output function Disabled 1 Clock Output function Enabled 3 0 FREQSEL Clock Output Frequency Selection Th...

Page 203: ...nable Bit 0 External high speed crystal oscillator HXT clock frequency range detector Disabled 1 External high speed crystal oscillator HXT clock frequency range detector Enabled 15 14 Reserved Reserved 13 LXTFIEN LXT Clock Fail Interrupt Enable Bit 0 External low speed crystal oscillator LXT clock fail interrupt Disabled 1 External low speed crystal oscillator LXT clock fail interrupt Enabled 12 ...

Page 204: ...XT Clock Frequency Range Detector Interrupt Flag Write Protect 0 External high speed crystal oscillator HXT clock frequency is normal 1 External high speed crystal oscillator HXT clock frequency is abnormal Note Write 1 to clear the bit to 0 7 2 Reserved Reserved 1 LXTFIF LXT Clock Fail Interrupt Flag Write Protect 0 External low speed crystal oscillator LXT clock is normal 1 External low speed cr...

Page 205: ...per Boundary Register 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved UPERBD 7 6 5 4 3 2 1 0 UPERBD Bits Description 31 10 Reserved Reserved 9 0 UPERBD HXT Clock Frequency Range Detector Upper Boundary Value The bits define the maximum value of frequency range detector window When HXT frequency is higher than this maximum frequency value...

Page 206: ...rved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved LOWERBD 7 6 5 4 3 2 1 0 LOWERBD Bits Description 31 10 Reserved Reserved 9 0 LOWERBD HXT Clock Frequency Range Detector Lower Boundary Value The bits define the minimum value of frequency range detector window When HXT frequency is lower than this minimum frequency value the HXT Clock Frequency Range Detector Interrupt Flag will ...

Page 207: ...EL CLK_BA 0xB4 R W HXT Filter Select Control Register 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 Reserved HXTFSEL Bits Description 31 1 Reserved Reserved 0 HXTFSEL HXT Filter Select 0 HXT frequency is greater than12 MHz 1 HXT frequency is less than or equal to 12 MHz Note This bit should not be changed during HXT run...

Page 208: ...Supports 16 32 Kbytes application ROM APROM Supports 512 bytes page size for 16 32 Kbytes Flash Supports 2 Kbytes loader ROM LDROM Supports configurable Data Flash size to share with APROM Supports 12 bytes User Configuration block to control system initialization Supports 512 bytes page erase for all embedded Flash Supports CRC 32 checksum calculation function Supports In System Programming ISP I...

Page 209: ...ry controller for Cortex M0 to perform the instruction data fetch and ISP control registers Flash Control Registers All of ISP control and status registers are in the Flash control registers Refer to the Register Description section for the detailed register description Flash Initialization Controller When the chip is powered on or active from reset the Flash initialization controller will start t...

Page 210: ...dded Flash memory is programmable and includes APROM LDROM Data Flash and the User Configuration block The address map includes Flash memory map and four system address maps LDROM with IAP LDROM without IAP APROM with IAP and APROM without IAP functions LDROM APROM and Data Flash LDROM is designed for a loader to implement In System Programming ISP function by user LDROM is a 2 KB embedded Flash m...

Page 211: ...or power on setting It is loaded from Flash memory to its corresponding control registers during chip power on User can set these bits according to different application requirements User Configuration block can be updated by ISP function and its address located at 0x0030_0000 with three 32 bits words CONFIG0 CONFIG1 and CONFIG2 Any change on User Configuration block will take effect after system ...

Page 212: ...DTPDEN is 1 Please refer to bit field description of CWDTPDEN 111 WDT hardware enable function is inactive WDT clock source only can be changed in this case Others WDT hardware enable function is active WDT clock is always on 30 CWDTPDEN Watchdog Clock Power down Enable Bit This bit should be used with CWDTEN When WDT enabled by CWDTEN user can use this bit to control WDT wakeup when system is in ...

Page 213: ...set as input tri state mode after powered on or active from reset pin 9 RSTEXT Chip Reset Time Extend 0 Extend reset time to 26 6 ms if chip release from power on reset LVR BOD nReset pin reset happened 1 Extend reset time to 3 2 ms if chip release from power on reset LVR BOD nReset pin reset happened 8 RSTWSEL RST Pin Width Selection 0 nReset pin debounce width is 2 us 1 nReset pin debounce width...

Page 214: ...ty Lock Control 0 Flash memory content is locked 1 Flash memory content is unlocked if ALOCK CONFIG2 7 0 is also equal to 0x5A 0 DFEN Data Flash Enable Bit The Data Flash is shared with APROM and the base address of Data Flash is decided by DFBA CONFIG1 19 0 when DFEN is 0 0 Data Flash Enabled 1 Data Flash Disabled ...

Page 215: ...17 16 Reserved DFBA 15 14 13 12 11 10 9 8 DFBA 7 6 5 4 3 2 1 0 DFBA Bits Description 31 20 Reserved Reserved 19 0 DFBA Data Flash Base Address This register works only when DFEN CONFIG0 0 is set to 0 If DFEN CONFIG0 0 is set to 0 the Data Flash base address is defined by user Since on chip Flash erase unit is 512 bytes it is mandatory to keep bit 8 0 or bit 10 0 respectively as 0 ...

Page 216: ...P ICP whole chip erase Flash Memory Map In the M0A21 M0A23 the Flash memory map is different from system memory map The system memory map is used by CPU fetch code or data from FMC memory The Flash memory map is used for ISP function to read program or erase FMC memory Figure 6 4 3 shows the Flash memory map Reserved Reserved 0x0000_0000 0x0010_0000 Loader ROM LDROM 2 KB 0x0010_07FF APROM 16 KB De...

Page 217: ... 0x0000_0200 DFBA 1 is APROM region for Cortex M0 instruction access The address from 0x0000_0000 to 0x0000_01FF is called system memory vector APROM and LDROM can map to the system memory vector for CPU start up There are two kinds of system memory map with IAP mode when chip booting 1 LDROM with IAP and 2 APROM with IAP 0x0000_0000 0x0010_0000 ApplicationROM APROM Loader ROM LDROM 2 KB Reserved ...

Page 218: ...User can write the target remap address to FMC_ISPADDR register and then trigger ISP procedure with the Vector Page Remap command 0x2E In VECMAP FMC_ISPSTS 23 9 shows the finial system memory vector mapping address System Memory Map without IAP Mode In system memory map without IAP mode the system memory vector mapping is not supported There are two kinds of system memory map without IAP mode when...

Page 219: ... Flash DFBA Loader ROM LDROM Reserved Reserved LDROM without IAP mode 0x0000_7FFF 0x0000_3FFF 0x0000_07FF Figure 6 4 7 16 32 Kbytes Flash System Memory Map without IAP Mode Boot Selection The M0A21 M0A23 provides four booting modes for application field They are LDROM with IAP LDROM without IAP APROM with IAP and APROM without IAP The booting modes and system memory map are setting by CBS CONFIG0 ...

Page 220: ...hip boot selection bits in CBS CONFIG0 7 6 as 10 or 00 When chip boots with IAP function enabled any executable code align to 512 bytes is allowed to map to the system memory vector 0x0000_0000 0x0000_01FF any time User can change the remap address to FMC_ISPADDR and then trigger ISP procedure with the Vector Page Remap command In System Programming ISP The M0A21 M0A23 supports In System Programmi...

Page 221: ...que ID 0x04 0x0000_0000 FMC_ISPDAT Unique ID Word 0 0x0000_0004 FMC_ISPDAT Unique ID Word 1 0x0000_0008 FMC_ISPDAT Unique ID Word 2 0x0000_0070 FMC_ISPDAT 11 0 Built in VBG ADC conversion result Vector Remap 0x2E Valid address in APROM or LDROM It must be 512 bytes alignment N A Table 6 4 2 ISP Command List ISP Procedure The FMC controller provides embedded Flash memory read erase and program oper...

Page 222: ...SP operation if it is set to 1 When the ISPGO FMC_ISPTRG 0 bit is set CPU will wait for ISP operation to finish during this period the peripheral still keeps working as usual If any interrupt request occurs CPU will not service it till ISP operation is finished When ISP operation is finished the ISPGO bit will be cleared by hardware automatically User can check whether ISP operation is finished or...

Page 223: ...ong time to erase pages To avoid this situation user needs to avoid CPU access Flash memory when page erasing The easiest way is to execute code in SRAM and use VECMAP to map all exceptions to SRAM By executing code in SRAM CPU will not access Flash to get instructions By mapping all exceptions to SRAM all interrupts will not need to get exception handler from Flash memory Embedded Flash Memory Pr...

Page 224: ...Write FMC_ISPCMD Write FMC_ISPDAT Add ISB instruction Check ISPGO 0 NO YES Start Stop Figure 6 4 11 ISP 32 bit Programming Procedure CRC32 Checksum Calculation The M0A21 M0A23 supports the Cyclic Redundancy Check CRC 32 checksum calculation function to help user quickly check the memory content includes APROM and LDROM The CRC 32 polynomial is as below CRC 32 X32 X26 X23 X22 X16 X12 X11 X10 X8 X7 ...

Page 225: ...UM 31 Figure 6 4 12 CRC 32 Checksum Calculation The following three steps complete the CRC 32 checksum calculation 1 Perform ISP Run Memory Checksum operation user has to set the memory starting address FMC_ISPADDR and size FMC_ISPDAT to calculate Both address and size have to be 512 bytes alignment the size must be multiples of 512 bytes and the starting address includes APROM and LDROM 2 Perform...

Page 226: ...N Set ISPGO 1 Write FMC_ISPADDR Write FMC_ISPDAT Write FMC_ISPCMD 0x2D Add ISB instruction Check ISPGO 0 NO YES Checksum Calculation Start END Set ISPGO 1 Write FMC_ISPCMD 0x0D Add ISB instruction Check ISPGO 0 NO YES Read Checksum from FMC_ISPDAT Step 1 Step 2 Step 3 Figure 6 4 13 CRC 32 Checksum Calculation Flow ...

Page 227: ...A 0x4000_C000 FMC_ISPCTL FMC_BA 0x00 R W ISP Control Register 0x0000_000X FMC_ISPADDR FMC_BA 0x04 R W ISP Address Register 0x0000_0000 FMC_ISPDAT FMC_BA 0x08 R W ISP Data Register 0x0000_0000 FMC_ISPCMD FMC_BA 0x0C R W ISP Command Register 0x0000_0000 FMC_ISPTRG FMC_BA 0x10 R W ISP Trigger Control Register 0x0000_0000 FMC_DFBA FMC_BA 0x14 R Data Flash Base Address 0xXXXX_XXXX FMC_ISPSTS FMC_BA 0x4...

Page 228: ... if CFGUEN is set to 0 Page Erase command at LOCK mode with ICE connection Erase or Program command at brown out detected Destination address is illegal such as over an available range Invalid ISP commands This bit needs to be cleared by writing 1 to it Note This bit is write protected Refer to the SYS_REGLCTL register 5 LDUEN LDROM Update Enable Bit Write Protect LDROM update enable bit 0 LDROM c...

Page 229: ...h can be used to check where chip booted from This bit is initiated with the inversed value of CBS 1 CONFIG0 7 after any reset is happened except CPU reset RSTS_CPU is 1 or system reset RSTS_SYS is happened 0 Booting from APROM 1 Booting from LDROM Note This bit is write protected Refer to the SYS_REGLCTL register 0 ISPEN ISP Enable Bit Write Protect 0 ISP function Disabled 1 ISP function Enabled ...

Page 230: ...22 21 20 19 18 17 16 ISPADDR 15 14 13 12 11 10 9 8 ISPADDR 7 6 5 4 3 2 1 0 ISPADDR Bits Description 31 0 ISPADDR ISP Address The M0A21 M0A23 is equipped with embedded Flash ISPADDR 1 0 must be kept 00 for ISP 32 bit operation For CRC32 Checksum Calculation command this field is the Flash starting address for checksum calculation 512 bytes alignment is necessary for checksum calculation 16 32 Kbyte...

Page 231: ...PDAT 15 14 13 12 11 10 9 8 ISPDAT 7 6 5 4 3 2 1 0 ISPDAT Bits Description 31 0 ISPDAT ISP Data Write data to this register before ISP program operation Read data from this register after ISP read operation For Run Checksum Calculation command ISPDAT is the memory size byte and 512 bytes alignment For Read Checksum command ISPDAT is the checksum result If ISPDAT 0x0000_0000 it means that 1 the chec...

Page 232: ...30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 Reserved CMD Bits Description 31 7 Reserved Reserved 6 0 CMD ISP CMD ISP command table is shown below 0x00 Flash 32 bit Read 0x04 Read Unique ID 0x0B Read Company ID 0x0D Read CRC32 Checksum 0x21 Flash 32 bit Program 0x22 Flash Page Erase 0x2D Run CRC32 Checksum Calculation 0x2E Vector Rem...

Page 233: ..._0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 Reserved ISPGO Bits Description 31 1 Reserved Reserved 0 ISPGO ISP Start Trigger Write Protect Write 1 to start ISP operation and this bit will be cleared to 0 by hardware automatically when ISP operation is finished 0 ISP operation is finished 1 ISP is progressed Note This bit is...

Page 234: ...x14 R Data Flash Base Address 0xXXXX_XXXX 31 30 29 28 27 26 25 24 DFBA 23 22 21 20 19 18 17 16 DFBA 15 14 13 12 11 10 9 8 DFBA 7 6 5 4 3 2 1 0 DFBA Bits Description 31 0 DFBA Data Flash Base Address This register indicates Data Flash start address It is a read only register The Data Flash is shared with APROM the content of this register is loaded from CONFIG1 This register is valid when DFEN CONF...

Page 235: ... to SRAM memory VECMAP 18 12 should be 0 8 7 Reserved Reserved 6 ISPFF ISP Fail Flag Write Protect This bit is the mirror of ISPFF FMC_ISPCTL 6 it needs to be cleared by writing 1 to FMC_ISPCTL 6 or FMC_ISPSTS 6 This bit is set by hardware when a triggered ISP meets any of the following conditions APROM writes to itself if APUEN is set to 0 LDROM writes to itself if LDUEN is set to 0 CONFIG is era...

Page 236: ...M0A21 M0A23 Series May 06 2022 Page 236 of 746 Rev 1 02 M0A21 M0A23 SERIES TECHNICAL REFERENCE MANUAL 0 ISPBUSY ISP BUSY Read Only 0 ISP operation is finished 1 ISP operation is busy ...

Page 237: ...asi bidirectional mode After the chip is reset the I O mode of all pins are depending on CIOINI CONFIG0 10 Each I O pin has a very weakly individual pull up resistor which is about 50 k Please refer to the M0A21 M0A23 Datasheet for detailed pin operation voltage information about VDD electrical characteristics 6 5 2 Features Four I O modes Quasi bidirectional mode Push Pull Output mode Open Drain ...

Page 238: ...B 0 PB 3 PB 8 PB 15 PC 8 PC 15 PD 8 PD 15 pin are ignored Figure 6 5 1 GPIO Controller Block Diagram Note The PA 6 PA 15 PB 0 PB 3 PB 8 PB 15 PC 8 PC 15 PD 8 PD 15 pins are not avaliable 6 5 4 Basic Configuration Reset configuration Reset GPIO in GPIORST SYS_IPRST1 1 Pin configuration 6 5 5 Functional Description Input Mode Set MODEn Px_MODE 2n 1 2n to 00 as the Px n pin is in Input mode and the I...

Page 239: ... The bit value in the corresponding DOUT Px_DOUT n is driven on the pin Port Pin Port Pin N N P P VDD VDD Port Latch Data Port Latch Data Input Data Input Data Figure 6 5 3 Push Pull Output Open drain Mode Figure 6 5 4 shows the diagram of Open drain Mode Set MODEn Px_MODE 2n 1 2n to 10 the Px n pin is in Open drain mode and the digital output function of I O pin supports only sink current capabil...

Page 240: ...w output on the pin If the bit value in the corresponding DOUT Px_DOUT n bit is 1 the pin will check the pin value If pin value is high no action takes If pin state is low the pin will drive strong high with 2 clock cycles on the pin and then disable the strong output drive Meanwhile the pin status is controlled by internal pull up resistor Note that the source current capability in quasi bidirect...

Page 241: ...ing GPIO pin The de bounce clock source can be HCLK or LIRC 38 4 kHz by setting DBCLKSRC GPIO_DBCTL 4 register And DBCLKSEL GPIO_DBCTL 3 0 register can control sampling cycle period Figure 6 5 6 shows GPIO rising edge trigger interrupt The interval of time between the two valid sample signal is determined by DBCLKSRC GPIO_DBCTL 4 and DBCLKSEL GPIO_DBCTL 3 0 Each valid data from GPIO pin need to be...

Page 242: ...l User can disable GPIO digital input path by setting DINOFF Px_DINOFF n 16 When GPIO digital input path is disabled the digital input pin value PIN Px_PIN n is tied to low By the way the GPIO digital input path is force disabled by hardware and DINOFF control is useless when I O function configure as ADC ACMP ext XTL GPIO Group Clock On Off Control User can disable GPIO group clock by setting GPI...

Page 243: ...000 PA_PUSEL GPIO_BA 0x030 R W PA Pull up Selection Register 0x0000_0000 PB_MODE GPIO_BA 0x040 R W PB I O Mode Control 0xXXXX_XXXX PB_DINOFF GPIO_BA 0x044 R W PB Digital Input Path Disable Control 0x0000_0000 PB_DOUT GPIO_BA 0x048 R W PB Data Output Value 0x0000_00F0 PB_DATMSK GPIO_BA 0x04C R W PB Data Output Write Mask 0x0000_0000 PB_PIN GPIO_BA 0x050 R PB Pin Value 0x0000_XXXX PB_DBEN GPIO_BA 0x...

Page 244: ...PIN GPIO_BA 0x0D0 R PD Pin Value 0x0000_XXXX PD_DBEN GPIO_BA 0x0D4 R W PD De bounce Enable Control Register 0x0000_0000 PD_INTTYPE GPIO_BA 0x0D8 R W PD Interrupt Trigger Type Control 0x0000_0000 PD_INTEN GPIO_BA 0x0DC R W PD Interrupt Enable Control Register 0x0000_0000 PD_INTSRC GPIO_BA 0x0E0 R W PD Interrupt Source Flag 0x0000_XXXX PD_SMTEN GPIO_BA 0x0E4 R W PD Input Schmitt Trigger Enable Regis...

Page 245: ...DE6 MODE5 MODE4 7 6 5 4 3 2 1 0 MODE3 MODE2 MODE1 MODE0 Bits Description 2n 1 2n n 0 1 15 MODE Port A D I O Pin n Mode Control Determine each I O mode of Px n pins 00 Px n is in Input mode 01 Px n is in Push pull Output mode 10 Px n is in Open drain Output mode 11 Px n is in Quasi bidirectional mode Note 1 The initial value of this field is defined by CIOINI CONFIG0 10 If CIOINI is set to 0 the de...

Page 246: ...x0C4 R W PD Digital Input Path Disable Control 0x0000_0000 31 30 29 28 27 26 25 24 DINOFF 23 22 21 20 19 18 17 16 DINOFF 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 Reserved Bits Description n 16 n 0 1 15 DINOFF Port A D Pin n Digital Input Path Disable Bit Each of these bits is used to control if the digital input path of corresponding Px n pin is disabled If input is analog signal users can d...

Page 247: ...rved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 DOUT 7 6 5 4 3 2 1 0 DOUT Bits Description 31 16 Reserved Reserved n n 0 1 15 DOUT Port A D Pin n Output Value Each of these bits controls the status of a Px n pin when the Px n is configured as Push pull output Open drain output or Quasi bidirectional mode 0 Px n will drive Low if the Px n pin is configured as Push pull output Open drain...

Page 248: ...7 16 Reserved 15 14 13 12 11 10 9 8 DATMSK 7 6 5 4 3 2 1 0 DATMSK Bits Description 31 16 Reserved Reserved n n 0 1 15 DATMSK Port A D Pin n Data Output Write Mask These bits are used to protect the corresponding DOUT Px_DOUT n bit When the DATMSK Px_DATMSK n bit is set to 1 the corresponding DOUT Px_DOUT n bit is protected If the write signal is masked writing data to the protect bit is ineffectiv...

Page 249: ... Pin Value 0x0000_XXXX PD_PIN GPIO_BA 0x0D0 R PD Pin Value 0x0000_XXXX 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 PIN 7 6 5 4 3 2 1 0 PIN Bits Description 31 16 Reserved Reserved n n 0 1 15 PIN Port A D Pin n Pin Value Each bit of the register reflects the actual status of the respective Px n pin 0 The corresponding pin status is low 1 The corresponding...

Page 250: ...BEN Bits Description 31 16 Reserved Reserved n n 0 1 15 DBEN Port A D Pin n Input Signal De bounce Enable Bit The DBEN n bit is used to enable the de bounce function for each corresponding bit If the input signal pulse width cannot be sampled by continuous two de bounce sample cycle the input signal transition is seen as the signal bounce and will not trigger the interrupt The de bounce clock sour...

Page 251: ...A D Pin n Edge or Level Detection Interrupt Trigger Type Control TYPE Px_INTTYPE n bit is used to control the triggered interrupt is by level trigger or by edge trigger If the interrupt is by edge trigger the trigger source can be controlled by de bounce If the interrupt is by level trigger the input source is sampled by one HCLK clock and generates the interrupt 0 Edge trigger interrupt 1 Level t...

Page 252: ...e input Px n pin will generate the interrupt while this pin state is at high level If the interrupt is edge trigger TYPE Px_INTTYPE n bit is set to 0 the input Px n pin will generate the interrupt while this pin state changed from low to high 0 Px n level high or low to high interrupt Disabled 1 Px n level high or low to high interrupt Enabled Note The PA 6 PA 15 PB 0 PB 3 PB 8 PB 15 PC 8 15 PD 8 ...

Page 253: ...0A0 R W PC Interrupt Source Flag 0x0000_XXXX PD_INTSRC GPIO_BA 0x0E0 R W PD Interrupt Source Flag 0x0000_XXXX 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 INTSRC 7 6 5 4 3 2 1 0 INTSRC Bits Description 31 16 Reserved Reserved n n 0 1 15 INTSRC Port A D Pin n Interrupt Source Flag Write Operation 0 No action 1 Clear the corresponding pending interrupt Read...

Page 254: ...0_0000 PC_SMTEN GPIO_BA 0x0A4 R W PC Input Schmitt Trigger Enable Register 0x0000_0000 PD_SMTEN GPIO_BA 0x0E4 R W PD Input Schmitt Trigger Enable Register 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 SMTEN 7 6 5 4 3 2 1 0 SMTEN Bits Description 31 16 Reserved Reserved n n 0 1 15 SMTEN Port A D Pin n Input Schmitt Trigger Enable Bit 0 Px n inpu...

Page 255: ...0000 PD_PUSEL GPIO_BA 0x0F0 R W PD Pull up Selection Register 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 PUSEL 7 6 5 4 3 2 1 0 PUSEL Bits Description n n 0 1 15 PUSEL Port A D Pin n Pull up Enable Register Determine each I O Pull up of Px n pins 0 Px n pull up disable 1 Px n pull up enable Note 1 The independent pull up control register only...

Page 256: ...PIO group 15 5 Reserved Reserved 4 DBCLKSRC De bounce Counter Clock Source Selection 0 De bounce counter clock source is the HCLK 1 De bounce counter clock source is the 38 4 kHz internal low speed RC oscillator LIRC 3 0 DBCLKSEL De bounce Sampling Cycle Selection 0000 Sample interrupt input once per 1 clocks 0001 Sample interrupt input once per 2 clocks 0010 Sample interrupt input once per 4 cloc...

Page 257: ...ved 7 6 5 4 3 2 1 0 Reserved GPDOn GPCOn GPBOn GPAOn Bits Description 31 4 Reserved Reserved 3 0 GPxOn GPIO Group Clock On off The GPIO port clock can be disabled to reduce power consumption by setting GPIO_CLKON if the GPIO port isn t used When GPxOn is set to 0 to diable GPIO port clock the GPIO register pin control and PDIO function are not workable Only GPIO_CLKON and GPIO_DBCTL register can b...

Page 258: ...ata Input Output Register 0x0000_000X 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 Reserved PDIO Bits Description 31 1 Reserved Reserved 0 PDIO GPIO Px n Pin Data Input Output Writing this bit can control one GPIO pin output value 0 Corresponding GPIO pin set to low 1 Corresponding GPIO pin set to high Read this register to get GP...

Page 259: ...ansfer data width of 8 16 and 32 bits Supports source and destination address increment size can be byte half word word or no increment Supports software and UART USCI ADC PWM DAC and TIMER request Supports Scatter Gather mode to perform sophisticated transfer through the use of the descriptor link list table Supports single and burst transfer type Supports time out function on channel 0 and chann...

Page 260: ...gram of descriptor table DSCT data structure Descriptor Table DSCT4 DSCT_DA DSCT_NEXT Descriptor Table Entry Structure 0x0C 0x08 0x04 DSCT_SA DSCT_CTL 0x00 0x40 DSCT3 DSCT0 DSCT1 DSCT2 0x00 0x10 0x20 0x30 Figure 6 6 2 Descriptor Table Entry Structure The PDMA controller also supports single and burst transfer type and the request source can be from software or peripheral request transfer between m...

Page 261: ...ze BURSIZE PDMA_DSCTn_CTL 6 4 and transfer type TXTYPE PDMA_DSCTn_CTL 2 then the PDMA controller will perform transfer operation in transfer state after receiving request signal Finishing this task will generate an interrupt to CPU if corresponding PDMA interrupt bit INTENn PDMA_INTEN 4 0 is enabled and the operation mode will be updated to idle state as shown in Figure 6 6 3 If software configure...

Page 262: ...address is 0x0000_0100 only LSB 16bits without last two bits 1 0 valid in PDMA_DSCTn_NEXT and then the next DSCT entry start address is 0x2000_0100 DSCT4 DSCT3 DSCT_CTL 0 1 LSB 16 bits without 1 0 MSB 16 bits SRAM Load the information to the channel 4 descriptor table Current DSCT Entry Next DSCT Entry DSCT1 DSCT0 DSCT_NEXT DSCT_DA DSCT_SA DSCT_NEXT DSCT_DA DSCT_SA DSCT_CTL PDMA_SCATBA Descriptor ...

Page 263: ...DMA controller to do burst transfer between memory and memory User must use single request type for memory to peripheral and peripheral to memory transfers Figure 6 6 6 shows an example about single and burst transfer type in basic mode In this example channel 1 uses single transfer type and TXCNT PDMA_DSCTn_CTL 31 16 127 Channel 0 uses burst transfer type BURSIZE PDMA_DSCTn_CTL 6 4 128 and TXCNT ...

Page 264: ...annel s TOUTPSCn PDMA_TOUTPSC 2 4n 4n n 0 1 If time out counter counts up from 0 to corresponding channel s TOCn PDMA_TOC0_1 16 n 1 1 16n n 0 1 the PDMA controller will generate interrupt signal when corresponding TOUTIENn PDMA_TOUTIEN n n 0 1 is enabled When time out occurred corresponding channel s REQTOFn PDMA_INTSTS n 8 n 0 1 will be set to indicate channel time out is happened Time out counte...

Page 265: ...CHNICAL REFERENCE MANUAL Time out counter TOC0 PDMA_TOC0_1 15 0 TOUTEN0 PDMA_TOUTEN 0 1 2 3 4 5 0 1 2 3 0 5 0 1 2 3 0 x Peripheral request REQTOF0 PDMA_INTSTS 8 Time out clock HCLK 2 8 TOUTPSC0 PDMA_TOUTPSC 2 0 0 Figure 6 6 7 Example of PDMA Channel 0 Time out Counter Operation ...

Page 266: ...egister 0x0000_0000 PDMA_PRISET PDMA_BA 0x410 R W PDMA Fixed Priority Setting Register 0x0000_0000 PDMA_PRICLR PDMA_BA 0x414 W PDMA Fixed Priority Clear Register 0x0000_0000 PDMA_INTEN PDMA_BA 0x418 R W PDMA Interrupt Enable Register 0x0000_0000 PDMA_INTSTS PDMA_BA 0x41C R W PDMA Interrupt Status Register 0x0000_0000 PDMA_ABTSTS PDMA_BA 0x420 R W PDMA Channel Read Write Target Abort Flag Register ...

Page 267: ...sfer width 00 One byte 8 bit is transferred for every operation 01 One half word 16 bit is transferred for every operation 10 One word 32 bit is transferred for every operation 11 Reserved Note The PDMA transfer source address PDMA_DSCT_SA and PDMA transfer destination address PDMA_DSCT_DA should be alignment under the TXWIDTH selection 11 10 DAINC Destination Address Increment This field is used ...

Page 268: ...ransfer type 1 Single transfer type 1 0 OPMODE PDMA Operation Mode Selection 00 Idle state Channel is stopped or this table is complete when PDMA finish channel table task OPMODE will be cleared to idle state automatically 01 Basic mode The descriptor table only has one task When this task is finished the PDMA_INTSTS 1 will be asserted 10 Scatter Gather mode When operating in this mode user must g...

Page 269: ...ister Offset R W Description Reset Value PDMA_DSCTn_SA PDMA_BA 0x0004 0x10 n R W Source Address Register of PDMA Channel n 0xXXXX_XXXX 31 30 29 28 27 26 25 24 SA 23 22 21 20 19 18 17 16 SA 15 14 13 12 11 10 9 8 SA 7 6 5 4 3 2 1 0 SA Bits Description 31 0 SA PDMA Transfer Source Address This field indicates a 32 bit source address of PDMA controller ...

Page 270: ...fset R W Description Reset Value PDMA_DSCTn_DA PDMA_BA 0x0008 0x10 n R W Destination Address Register of PDMA Channel n 0xXXXX_XXXX 31 30 29 28 27 26 25 24 DA 23 22 21 20 19 18 17 16 DA 15 14 13 12 11 10 9 8 DA 7 6 5 4 3 2 1 0 DA Bits Description 31 0 DA PDMA Transfer Destination Address This field indicates a 32 bit destination address of PDMA controller ...

Page 271: ... of next descriptor table address of current execution descriptor table in system memory Note Write operation is useless in this field 15 0 NEXT PDMA Next Descriptor Table Offset This field indicates the offset of the next descriptor table address in system memory Write Operation If the system memory based address is 0x2000_0000 PDMA_SCATBA and the next descriptor table is start from 0x2000_0100 t...

Page 272: ...er gather Descriptor Table Address of PDMA Channel n 0xXXXX_XXXX 31 30 29 28 27 26 25 24 CURADDR 23 22 21 20 19 18 17 16 CURADDR 15 14 13 12 11 10 9 8 CURADDR 7 6 5 4 3 2 1 0 CURADDR Bits Description 31 0 CURADDR PDMA Current Description Address Read Only This field indicates a 32 bit current external description address of PDMA controller Note This field is read only and used for Scatter Gather m...

Page 273: ... 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 Reserved CHEN4 CHEN3 CHEN2 CHEN1 CHEN0 Bits Description 31 5 Reserved Reserved n n 0 1 4 CHENn PDMA Channel Enable Bits Set this bit to 1 to enable PDMAn operation Channel cannot be active if it is not set as enabled 0 PDMA channel n Disabled 1 PDMA channel n Enabled Note Setting the corresponding...

Page 274: ...9 8 Reserved 7 6 5 4 3 2 1 0 Reserved PAUSE4 PAUSE3 PAUSE2 PAUSE1 PAUSE0 Bits Description 31 5 Reserved Reserved n n 0 1 4 PAUSEn PDMA Channel n Transfer Pause Control Write Only User can set PAUSEn bit field to pause the PDMA transfer When user sets PAUSEn bit the PDMA controller will pause the on going transfer then clear the channel enable bit CHEN PDMA_CHCTL n n 0 1 4 and clear request active ...

Page 275: ... 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 Reserved SWREQ4 SWREQ3 SWREQ2 SWREQ1 SWREQ0 Bits Description 31 5 Reserved Reserved n n 0 1 4 SWREQn PDMA Software Request Write Only Set this bit to 1 to generate a software request to PDMA n 0 No effect 1 Generate a software request Note 1 User can read PDMA_TRGSTS register to know which channel is on active Active flag may be triggered by software...

Page 276: ...0 Reserved REQSTS4 REQSTS3 REQSTS2 REQSTS1 REQSTS0 Bits Description 31 5 Reserved Reserved n n 0 1 4 REQSTSn PDMA Channel Request Status Read Only This flag indicates whether channel n have a request or not no matter request from software or peripheral When PDMA controller finishes channel transfer this bit will be cleared automatically 0 PDMA Channel n has no request 1 PDMA Channel n has a reques...

Page 277: ... Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 Reserved FPRISET4 FPRISET3 FPRISET2 FPRISET1 FPRISET0 Bits Description 31 5 Reserved Reserved n n 0 1 4 FPRISETn PDMA Fixed Priority Setting Set this bit to 1 to enable fixed priority level Write Operation 0 No effect 1 Set PDMA channel n to fixed priority channel Read Operation 0 Corresponding PDMA channel is round robin priority 1 Correspo...

Page 278: ... 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 Reserved FPRICLR4 FPRICLR3 FPRICLR2 FPRICLR1 FPRICLR0 Bits Description 31 5 Reserved Reserved n n 0 1 4 FPRICLRn PDMA Fixed Priority Clear Bits Write Only Set this bit to 1 to clear fixed priority level 0 No effect 1 Clear PDMA channel n fixed priority setting Note User can...

Page 279: ...er 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 Reserved INTEN4 INTEN3 INTEN2 INTEN1 INTEN0 Bits Description 31 5 Reserved Reserved n n 0 1 4 INTENn PDMA Interrupt Enable Bits This field is used to enable PDMA channel n interrupt 0 PDMA channel n interrupt Disabled 1 PDMA channel n interrupt Enabled Note The interrupt ...

Page 280: ...indicates that PDMA controller has waited peripheral request for a period defined by PDMA_TOC0 user can write 1 to clear these bits 0 No request time out 1 Peripheral request time out Note Please disable time out function before clearing this bit 7 3 Reserved Reserved 2 ALIGNF Transfer Alignment Interrupt Flag Read Only 0 PDMA channel source address and destination address both follow transfer wid...

Page 281: ...0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 Reserved ABTIF4 ABTIF3 ABTIF2 ABTIF1 ABTIF0 Bits Description 31 5 Reserved Reserved n n 0 1 4 ABTIFn PDMA Read Write Target Abort Interrupt Status Flag This bit indicates which PDMA controller has target abort error User can write 1 to clear these bits 0 No AHB bus ERROR respo...

Page 282: ...Flag Register 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 Reserved TDIF4 TDIF3 TDIF2 TDIF1 TDIF0 Bits Description 31 5 Reserved Reserved n n 0 1 4 TDIFn Transfer Done Flag This bit indicates whether PDMA controller channel transfer has been finished or not user can write 1 to clear these bits 0 PDMA channel transfer h...

Page 283: ...23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 Reserved ALIGN4 ALIGN3 ALIGN2 ALIGN1 ALIGN0 Bits Description 31 5 Reserved Reserved n n 0 1 4 ALIGNn Transfer Alignment Flag This bit indicates whether source and destination address both follow transfer width setting user can write 1 to clear these bits 0 PDMA channel source address and destination address both follow...

Page 284: ...BA 0x42C R PDMA Transfer Active Flag Register 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 Reserved TXACTF4 TXACTF3 TXACTF2 TXACTF1 TXACTF0 Bits Description 31 5 Reserved Reserved n n 0 1 4 TXACTFn Transfer on Active Flag Read Only This bit indicates which PDMA channel is in active 0 PDMA channel is finished 1 PDMA cha...

Page 285: ...9 010 PDMA channel 1 time out clock source is HCLK 210 011 PDMA channel 1 time out clock source is HCLK 211 100 PDMA channel 1 time out clock source is HCLK 212 101 PDMA channel 1 time out clock source is HCLK 213 110 PDMA channel 1 time out clock source is HCLK 214 111 PDMA channel 1 time out clock source is HCLK 215 3 Reserved Reserved 2 0 TOUTPSC0 PDMA Channel 0 Time out Clock Source Prescaler ...

Page 286: ...Value PDMA_TOUTEN PDMA_BA 0x434 R W PDMA Time out Enable Register 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 Reserved TOUTEN1 TOUTEN0 Bits Description 31 2 Reserved Reserved n n 0 1 TOUTENn PDMA Time out Enable Bits 0 PDMA Channel n time out function Disabled 1 PDMA Channel n time out function Enabled ...

Page 287: ...MA_TOUTIEN PDMA_BA 0x438 R W PDMA Time out Interrupt Enable Register 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 Reserved TOUTIEN1 TOUTIEN0 Bits Description 31 2 Reserved Reserved n n 0 1 TOUTIENn PDMA Time out Interrupt Enable Bits 0 PDMA Channel n time out interrupt Disabled 1 PDMA Channel n time out interrupt Enabl...

Page 288: ...riptor Table Base Address Register 0x2000_0000 31 30 29 28 27 26 25 24 SCATBA 23 22 21 20 19 18 17 16 SCATBA 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 Reserved Bits Description 31 16 SCATBA PDMA Scatter gather Descriptor Table Address In Scatter Gather mode this is the base address for calculating the next link list address The next link address equation is Next Link Address PDMA_SCATBA PDMA_...

Page 289: ...17 16 TOC1 15 14 13 12 11 10 9 8 TOC0 7 6 5 4 3 2 1 0 TOC0 Bits Description 31 16 TOC1 Time out Counter for Channel 1 This controls the period of time out function for channel 1 The calculation unit is based on TOUTPSC1 PDMA_TOUTPSC 6 4 clock For the example of time out period refer to TOC0 bit description 15 0 TOC0 Time out Counter for Channel 0 This controls the period of time out function for c...

Page 290: ...set Value PDMA_CHRST PDMA_BA 0x460 R W PDMA Channel Reset Register 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 Reserved CH4RST CH3RST CH2RST CH1RST CH0RST Bits Description 31 5 Reserved Reserved 4 0 CHnRST Channel n Reset 0 corresponding channel n is not reset 1 corresponding channel n is reset ...

Page 291: ...served Reserved 21 16 REQSRC2 Channel 2 Request Source Selection This filed defines which peripheral is connected to PDMA channel 2 User can configure the peripheral setting by REQSRC2 Note The channel configuration is the same as REQSRC0 field Please refer to the explanation of REQSRC0 15 14 Reserved Reserved 13 8 REQSRC1 Channel 1 Request Source Selection This filed defines which peripheral is c...

Page 292: ...8 Reserved 19 Reserved 20 Channel connects to ADC_RX 21 Channel connects to PWM0_P1_RX 22 Channel connects to PWM0_P2_RX 23 Channel connects to PWM0_P3_RX 24 Reserved 25 Reserved 26 Reserved 27 Reserved 28 Reserved 29 Reserved 30 Reserved 31 Reserved 32 Channel connects to TMR0 33 Channel connects to TMR1 34 Channel connects to TMR2 35 Channel connects to TMR3 Others Reserved Note 1 A peripheral c...

Page 293: ...ister 1 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 Reserved REQSRC4 Bits Description 31 6 Reserved Reserved 5 0 REQSRC4 Channel 4 Request Source Selection This filed defines which peripheral is connected to PDMA channel 4 User can configure the peripheral setting by REQSRC4 Note The channel configuration is the same ...

Page 294: ...er and one 8 bit prescale counter Independent clock source for each timer Provides one shot periodic toggle output and continuous counting operation modes 24 bit up counter value is readable through CNT TIMERx_CNT 23 0 Supports event counting function 24 bit capture value is readable through CAPDAT TIMERx_CAP 23 0 Supports external capture pin event for interval measurement Supports external captu...

Page 295: ...escale 24 bit up counter 24 bit CMPDAT TIMERx_CMP 23 0 WKEN TIMERx_CTL 23 TWKF TIMERx_INTSTS 1 TIF TIMERx_INTSTS 0 CAPIEN TIMERx_EXTCTL 5 INTEN TIMERx_CTL 29 24 bit CAPDAT TIMERx_CAP 23 0 24 bit CNT TIMERx_CNT 23 0 CAPIF TIMERx_ EINTSTS 0 CAPFUNCS TIMERx_EXTCTL 4 1 Timer Wakeup Reset counter CAPSRC TIMERx_CTL 16 T0_EXT T3_EXT 0 1 0 1 INTERCAPSEL TIMERx_EXTCTL 10 8 0 1 ACMP0_O ACMP1_O Debounce Circ...

Page 296: ...ow Speed Internal clock signal LXT Low Speed External clock signal PCLK0 48 MHz HIRC 4 24 MHz HXT 32 768 kHz LXT T0 T1 TMR0CKEN CLK_APBCLK0 2 TMR1CKEN CLK_APBCLK0 3 TMR0_CLK TMR1_CLK TMR0SEL CLK_CLKSEL1 10 8 TMR1SEL CLK_CLKSEL1 14 12 111 010 001 000 011 101 111 010 001 PCLK1 000 011 101 Legend HIRC High Speed Internal clock signal 48 MHz HIRC 4 24 MHz HXT 32 768 kHz LXT T2 T3 TMR2CKEN CLK_APBCLK0 ...

Page 297: ...ture source The TWKF TIMERx_INTSTS 1 bit indicates the interrupt wake up flag status of timer Set WKEN TIMERx_CTL 23 to 1 to use wake up function Timer Counting Mode The timer controller provides four timer counting modes one shot periodic toggle output and continuous counting operation modes One Shot Mode If the timer controller is configured in one shot mode TIMERx_CTL 28 27 is 00 and CNTEN TIME...

Page 298: ... and CNT value keeps up counting In the meantime if the INTEN TIMERx_CTL 29 is set the timer interrupt signal is generated and sent to NVIC to inform CPU User can change different CMPDAT value immediately without disabling timer counting and restarting timer counting in this mode For example the CMPDAT value is set as 80 first The TIF will be set to 1 when the CNT value is equal to 80 the timer co...

Page 299: ... de bounce circuit by setting CAPDBEN TIMERx_EXTCTL 6 The transition frequency of TMx_EXT pin should be less than 1 3 PCLK if TMx_EXT pin de bounce disabled or less than 1 8 PCLK if TMx_EXT pin de bounce enabled to assure the capture function can be work normally and user can also select edge transition detection of TMx_EXT pin by setting CAPEDGE TIMERx_EXTCTL 14 12 In event capture mode if user d...

Page 300: ...PWM DAC ADC and PDMA If TRGSSEL TIMERx_CTL 18 is 1 capture interrupt signal is used to trigger PWM DAC ADC and PDMA When the TRGPWM TIMERx_CTL 19 is set if the timer interrupt signal is generated the timer controller will generate a trigger pulse as PWM external clock source When the TRGDAC TIMERx_CTL 20 is set if the timer interrupt signal is generated the timer controller will trigger DAC to sta...

Page 301: ...status When setting Timer0 Inter timer Trigger Capture enabled trigger counting capture function is forced on Timer1 Setting Timer2 Inter timer Trigger Capture enabled trigger counting capture function is forced on Timer3 Start Trigger While INTRGEN TIMERx_CTL 10 in Timer0 2 is set the Timer0 2 will make a rising edge transition of INTR_TMR_TRG while Timer0 2 24 bit counter value CNT is counting f...

Page 302: ...if user wants to use the second inter timer trigger function Capture Single Measure Mode When user sets CAPEN TIMERx_EXTCTL 3 1 and CASIGMEN TIMERx_EXTCTL 20 1 Timer will enter Single Meaure Mode User can use timer to measure full period or half period When user writes one to SIGST TIMERx_EXTCTL 21 timer will start to measure TMx_EXT When timer detects edge finish SIGST will be auto cleared by har...

Page 303: ...ICAL REFERENCE MANUAL TMx_EXT GASIGMEN CAPEDGE CAPIF 1 SIGST Software write one to start Detect done hardware auto clear CAPDAT 66 Software write one to start Detect done hardware auto clear 0 90 Software clear Software clear 90 tclk 66 tclk Figure 6 7 8 Capture Single Measure Mode ...

Page 304: ... Status Register 0x0000_0000 TIMER1_CNT TMR01_BA 0x2C R Timer1 Data Register 0x0000_0000 TIMER1_CAP TMR01_BA 0x30 R Timer1 Capture Data Register 0x0000_0000 TIMER1_EXTCTL TMR01_BA 0x34 R W Timer1 External Control Register 0x0000_0000 TIMER1_EINTSTS TMR01_BA 0x38 R W Timer1 External Interrupt Status Register 0x0000_0000 TIMER2_CTL TMR23_BA 0x00 R W Timer2 Control Register 0x0000_0005 TIMER2_CMP TMR...

Page 305: ...age 305 of 746 Rev 1 02 M0A21 M0A23 SERIES TECHNICAL REFERENCE MANUAL TIMER3_EXTCTL TMR23_BA 0x34 R W Timer3 External Control Register 0x0000_0000 TIMER3_EINTSTS TMR23_BA 0x38 R W Timer3 External Interrupt Status Register 0x0000_0000 ...

Page 306: ...ile CPU is held by ICE 1 ICE debug mode acknowledgement Disabled TIMER counter will keep going no matter CPU is held by ICE or not Note This bit is write protected Refer to the SYS_REGLCTL register 30 CNTEN Timer Counting Enable Bit 0 Stops Suspends counting 1 Starts counting Note 1 In stop status and then setting CNTEN to 1 will enable the 24 bit up counter to keep counting from the last stop cou...

Page 307: ...ke up Function Enable Bit If this bit is set to 1 while timer interrupt flag TIF TIMERx_INTSTS 0 is 1 and INTEN TIMERx_CTL 29 is enabled the timer interrupt signal will generate a wake up trigger event to CPU 0 Wake up function Disabled if timer interrupt signal generated 1 Wake up function Enabled if timer interrupt signal generated 22 TGLPINSEL Toggle output Pin Select 0 Toggle mode output to Tx...

Page 308: ...ble Bit Setting this bit will enable the inter timer trigger capture function The Timer0 2 will be in event counter mode and counting with external clock source or event Also Timer1 3 will be in trigger counting mode of capture function 0 Inter Timer Trigger mode Disabled 1 Inter Timer Trigger mode Enabled Note For Timer1 3 this bit is ignored and the read back value is always 0 9 Reserved Reserve...

Page 309: ...T Bits Description 31 24 Reserved Reserved 23 0 CMPDAT Timer Comparator Value CMPDAT is a 24 bit compared value register When the internal 24 bit up counter value is equal to CMPDAT value the TIF TIMERx_INTSTS 0 Timer Interrupt Flag will set to 1 Time out period Period of timer clock input 8 bit PSC 1 24 bit CMPDAT Note 1 Never write 0x0 or 0x1 in CMPDAT field or the core will run into unknown sta...

Page 310: ...0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 Reserved TWKF TIF Bits Description 31 2 Reserved Reserved 1 TWKF Timer Wake up Flag This bit indicates the interrupt wake up flag status of timer 0 Timer does not cause CPU wake up 1 CPU wake up from Idle or Power down mode if timer time out interrupt signal generated Note This bit...

Page 311: ...R Timer2 Data Register 0x0000_0000 TIMER3_CNT TMR23_BA 0x2C R Timer3 Data Register 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 CNT 15 14 13 12 11 10 9 8 CNT 7 6 5 4 3 2 1 0 CNT Bits Description 31 24 Reserved Reserved 23 0 CNT Timer Data Register Read this register to get CNT value For example If EXTCNTEN TIMERx_CTL 24 is 0 user can read CNT value for getting current 24 bi...

Page 312: ...2 Capture Data Register 0x0000_0000 TIMER3_CAP TMR23_BA 0x30 R Timer3 Capture Data Register 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 CAPDAT 15 14 13 12 11 10 9 8 CAPDAT 7 6 5 4 3 2 1 0 CAPDAT Bits Description 31 24 Reserved Reserved 23 0 CAPDAT Timer Capture Data Register When CAPEN TIMERx_EXTCTL 3 bit is set and a transition on TMx_EXT pin matched the CAPEDGE TIMERx_EX...

Page 313: ...start measure TMx_EXT pin When capture measure event finishes this bit will auto clear by hardware 20 CASIGMEN Capture Single Measure Mode Enable Bit Enable Single Pulse Mode function user can write one to SIGST that can start measure full period or half period on TMx_EXT x 0 3 0 Single Measure Mode Disabled 1 Single Measure Mode Enabled Note these bits only available when CAPEN TIMERx_EXTCTL 3 is...

Page 314: ... 3 pin de bounce Disabled 1 TMx x 0 3 pin de bounce Enabled Note If this bit is enabled the edge detection of TMx pin is detected with de bounce circuit 6 CAPDBEN Timer External Capture Pin De bounce Enable Bit 0 TMx_EXT x 0 3 pin de bounce or ACMP output de bounce Disabled 1 TMx_EXT x 0 3 pin de bounce or ACMP output de bounce Enabled Note If this bit is enabled the edge detection of TMx_EXT pin ...

Page 315: ...TMR3 CAPEN will be forced to 1 when TMR0 TMR2 INTRGEN is enabled 2 1 Reserved Reserved 0 CNTPHASE Timer External Count Phase This bit indicates the detection phase of external counting pin TMx x 0 3 0 A falling edge of external counting pin will be counted 1 A rising edge of external counting pin will be counted ...

Page 316: ... 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 Reserved CAPIF Bits Description 31 1 Reserved Reserved 0 CAPIF Timer External Capture Interrupt Flag This bit indicates the timer external capture interrupt flag status 0 TMx_EXT x 0 3 pin interrupt did not occur 1 TMx_EXT x 0 3 pin interrupt occurred Note 1 This bit is cleared by writing 1 to it Not...

Page 317: ...me out wake up function only if WDT clock source is selected as LIRC or LXT 6 8 3 Block Diagram 20 bit WDT Counter 0 17 4 18 19 0000 0001 0111 1000 WDT_CLK Note 2 Time Out Interval Period select Reset Delay Period Select Note 3 Watchdog Interrupt Watchdog Reset Note 1 RSTCNT WDT_RSTCTL 31 0 Reset WDT Counter WDTEN WDT_CTL 7 Wakeup CPU from Power down mode TOUTSEL WDT_CTL 11 8 IF WDT_CTL 3 INTEN WD...

Page 318: ...er reaches the TOUTSEL WDT_CTL 11 8 settings WDT time out interrupt will occur then WDT time out interrupt flag IF WDT_CTL 3 will be set to 1 immediately If INTEN WDT_CTL 6 is enabled WDT time out interrupt will inform CPU 6 8 5 2 WDT Reset Delay Period and Reset System There is a specified TRSTD reset delay period follows the IF WDT_CTL 3 is setting to 1 User should set WDT_RSTCNT to reset the 20...

Page 319: ...lay Period Selectable 3 18 130 1026 TWDT delay period controlled by RSTDSEL WDT_ALTCTL 1 0 TRST Watchdog Reset Period 63 TWDT WDT_CLK IF 1 RSTF 1 if RSTEN 1 IF WDT_CTL 3 RSTF WDT_CTL 2 RSTEN WDT_CTL 1 Figure 6 8 3 Watchdog Timer Time out Interval and Reset Period Timing 6 8 5 3 WDT Wake up If WDT clock source is selected to LIRC or LXT system can be woken up from Power down mode while WDT time out...

Page 320: ...E MANUAL 6 8 5 4 WDT ICE Debug When ICE is connected to MCU WDT counter is counting or not by ICEDEBUG WDT_CTL 31 The default value of ICEDEBUG is 0 WDT counter will stop counting when CPU is held by ICE If ICEDEBUG is set to 1 WDT counter will keep counting no matter CPU is held by ICE or not ...

Page 321: ... R read only W write only R W both read and write Register Offset R W Description Reset Value WDT Base Address WDT_BA 0x4004_0000 WDT_CTL WDT_BA 0x00 R W WDT Control Register 0x0000_0800 WDT_ALTCTL WDT_BA 0x04 R W WDT Alternative Control Register 0x0000_0000 WDT_RSTCNT WDT_BA 0x08 W WDT Reset Counter Register 0x0000_0000 ...

Page 322: ...unter will keep going no matter CPU is held by ICE or not Note This bit is write protected Refer to the SYS_REGLCTL register 30 SYNC WDT Enable Control SYNC Flag Indicator Read Only If user executes enable disable WDTEN WDT_CTL 7 this flag can be indicated enable disable WDTEN function is completed or not 0 Set WDTEN bit is completed 1 Set WDTEN bit is synchronizing and not become active yet Note ...

Page 323: ...erated to 1 and interrupt enable bit INTEN WDT_CTL 6 is enabled the WDT time out interrupt signal will generate a wake up trigger event to chip 0 Wake up trigger event Disabled if WDT time out interrupt signal generated 1 Wake up trigger event Enabled if WDT time out interrupt signal generated Note 1 This bit is write protected Refer to the SYS_REGLCTL register Note 2 Chip can be woken up by WDT t...

Page 324: ...Reserved 1 0 RSTDSEL WDT Reset Delay Selection Write Protect When WDT time out happened user has a time named WDT Reset Delay Period to clear WDT counter by writing 0x00005aa5 to RSTCNT WDT_RSTCNT 31 0 to prevent WDT time out reset happened User can select a suitable setting of RSTDSEL for different WDT Reset Delay Period 00 WDT Reset Delay Period is 1026 WDT_CLK 01 WDT Reset Delay Period is 130 W...

Page 325: ...T WDT_BA 0x08 W WDT Reset Counter Register 0x0000_0000 31 30 29 28 27 26 25 24 RSTCNT 23 22 21 20 19 18 17 16 RSTCNT 15 14 13 12 11 10 9 8 RSTCNT 7 6 5 4 3 2 1 0 RSTCNT Bits Description 31 0 RSTCNT WDT Reset Counter Register Writing 0x00005AA5 to this field will reset the internal 20 bit WDT up counter value to 0 Note Performing RSTCNT to reset counter needs 2 WDT_CLK period to become active ...

Page 326: ...DT counter suspends in Idle Power down mode 6 9 3 Block Diagram 6 bit down counter 11 bit Prescale 6 bit compare value CMPDAT WWDT_CLK 0x3F Write RLDCNT 0x00005AA5 comparator CNTDAT CMPDAT WWDTIF STATUS 0 CNTDAT CMPDAT INTEN WWDT_CTL 1 WWDT Interrupt WWDT Reset System CNTDAT 0 Write RLDCNT 0x00005AA5 WWDTRF STATUS 1 PSCSEL WWDT_CTL 11 8 6 bit down counter value CNTDAT synchronizer WWDTEN WWDT_CTL ...

Page 327: ...s 1101 1024 1024 64 TWWDT 1 706 s 1110 1536 1536 64 TWWDT 2 56 s 1111 2048 2048 64 TWWDT 3 413 s Table 6 9 1 WWDT Prescaler Value Selection WWDT Counting When the WWDTEN WWDT_CTL 0 is set WWDT down counter will start counting from 0x3F to 0 To prevent program runs to disable WWDT counter counting unexpected the WWDT_CTL register can only be written once after chip is powered on or reset User canno...

Page 328: ... reset also The waveform of WWDT reload counter when CNTDAT CMPDAT is shown in Figure 6 9 4 WWDT_CLK WWDTIF WWDT_STATUS 0 WWDTRF WWDT_STATUS 1 TWWDT WWDTVAL 20 1F Note PSCSEL WWDT_CTL 11 8 0x0 CMPDAT WWDT_CTL 21 16 0x10 1E 1D 3F 3E Write 0x00005AA5 to WWDT_RLD 3D 3C Figure 6 9 4 WWDT Reload Counter When CNTDAT CMPDAT When WWDTIF WWDT_STATUS 0 is generated user must reload WWDT counter value to 0x3...

Page 329: ...ng Limitation When user writes 0x00005AA5 to WWDT_RLDCNT register to reload WWDT counter value to 0x3F it needs 3 WWDT clocks to sync the reload command to actually perform reload action Note that if user sets PSCSEL WWDT_CTL 11 8 to 0000 the counter prescale value should be as 1 and the CMPDAT WWDT_CTL 21 16 must be larger than 2 Otherwise writing WWDT_RLDCNT register to reload WWDT counter value...

Page 330: ...le 6 9 2 CMPDAT Setting Limitation WWDT ICE Debug When ICE is connected to MCU the WWDT counter is counting or not by ICEDEBUG WWDT_CTL 31 The default value of ICEDEBUG is 0 The WWDT counter will stop counting when CPU is held by ICE If ICEDEBUG is set to 1 the WWDT counter will keep counting no matter CPU is held by ICE or not ...

Page 331: ...th read and write Register Offset R W Description Reset Value WWDT Base Address WWDT_BA 0x4004_0100 WWDT_RLDCNT WWDT_BA 0x00 W WWDT Reload Counter Register 0x0000_0000 WWDT_CTL WWDT_BA 0x04 R W WWDT Control Register 0x003F_0800 WWDT_STATUS WWDT_BA 0x08 R W WWDT Status Register 0x0000_0000 WWDT_CNT WWDT_BA 0x0C R WWDT Counter Value Register 0x0000_003F ...

Page 332: ...5 24 RLDCNT 23 22 21 20 19 18 17 16 RLDCNT 15 14 13 12 11 10 9 8 RLDCNT 7 6 5 4 3 2 1 0 RLDCNT Bits Description 31 0 RLDCNT WWDT Reload Counter Register Writing 0x00005AA5 to this register will reload the WWDT counter value to 0x3F Note User can only write WWDT_RLDCNT register to reload WWDT counter value when current WWDT counter value between 0 and CMPDAT WWDT_CTL 21 16 If user writes WWDT_RLDCN...

Page 333: ...ster to reload WWDT counter value when current WWDT counter value between 0 and CMPDAT If user writes WWDT_RLDCNT register when current WWDT counter value is larger than CMPDAT WWDT reset signal will be generatec immediately 15 12 Reserved Reserved 11 8 PSCSEL WWDT Counter Prescale Period Selection 0000 Pre scale is 1 Max time out period is 1 64 WWDT_CLK 0001 Pre scale is 2 Max time out period is ...

Page 334: ...is 2048 Max time out period is 2048 64 WWDT_CLK 7 2 Reserved Reserved 1 INTEN WWDT Interrupt Enable Bit If this bit is enabled the WWDT counter compare match interrupt signal is generated and inform to CPU 0 WWDT counter compare match interrupt Disabled 1 WWDT counter compare match interrupt Enabled 0 WWDTEN WWDT Enable Bit 0 WWDT counter is stopped 1 WWDT counter starts counting ...

Page 335: ... 6 5 4 3 2 1 0 Reserved WWDTRF WWDTIF Bits Description 31 2 Reserved Reserved 1 WWDTRF WWDT Timer out Reset Flag This bit indicates the system has been reset by WWDT time out reset or not 0 WWDT time out reset did not occur 1 WWDT time out reset occurred Note This bit is cleared by writing 1 to it 0 WWDTIF WWDT Compare Match Interrupt Flag This bit indicates the interrupt flag status of WWDT while...

Page 336: ...escription Reset Value WWDT_CNT WWDT_BA 0x0C R WWDT Counter Value Register 0x0000_003F 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 Reserved CNTDAT Bits Description 31 6 Reserved Reserved 5 0 CNTDAT WWDT Counter Value CNTDAT will be updated continuously to monitor 6 bit WWDT down counter value ...

Page 337: ...pened Capture function also support PDMA to transfer captured data to memory 6 10 2 Features 6 10 2 1 PWM Function Features Supports maximum clock frequency up to 48 MHz Supports up to one PWM module and provides 6 output channels Supports independent mode for PWM output Capture input channel Supports complementary mode for 3 complementary paired PWM output channel Dead time insertion with 12 bit ...

Page 338: ...M0_BRAKE1 SYNC_IN TIMER0 ADC CLOCK CONTROLLER 5 TIMER1 TIMER2 TIMER3 PWM0_CH0 PWM0_CH5 4 NVIC_MUX 6 Clock Fail Brown Out Detect CPU Lockup Brake Source 4 Figure 6 10 1 PWM Generator Overview Block Diagram The PWM Clock frequency can be set equal to PCLK frequency as Figure 6 10 2 HCLKSEL CLK_CLKSEL0 2 0 1 HCLKDIV 1 HCLK PWM0 Clock PCLK0 PWM0CKEN CLK_APBCLK1 16 HCLKDIV CLK_CLKDIV0 3 0 0 1 2 3 7 HXT...

Page 339: ...K PWM0 Clock PCLK0 PWM0CKEN CLK_APBCLK1 16 HCLKDIV CLK_CLKDIV0 3 0 0 1 2 3 7 HXT LXT Rserved LIRC HIRC 1 APB0DIV 1 APB0DIV CLK_PCLKDIV 3 0 Figure 6 10 2 PWM System Clock Source Control Table 6 10 1 PWM Clock Source Control Registers Setting Table PWM0 clock TIMER0 TIMER1 TIMER2 TIMER3 0 1 2 3 4 ECLKSRC0 PWM0_CLKSRC 2 0 PWM0_CLK0 PWM0 clock TIMER0 TIMER1 TIMER2 TIMER3 0 1 2 3 4 ECLKSRC2 PWM0_CLKSRC...

Page 340: ...omplementary mode even channel use odd channel comparator to generate events Prescaler0 12bits Interrupt Generator Trigger Generator NVIC_MUX ADC PWM0_CH0 Prescaler2 12bits Prescaler4 12bits Pulse Generator0 Output Control0 Pulse Generator1 Output Control1 PWM0_CH1 PWM0_CH2 Pulse Generator2 Output Control2 Pulse Generator3 Output Control3 PWM0_CH3 PWM0_CH4 Pulse Generator4 Output Control4 Pulse Ge...

Page 341: ...LK2 PWM0_CLK4 16 16 16 Comparator1 Comparator0 Counter0_1 a a a 16 16 16 Comparator3 Comparator2 Counter2_3 a a a 16 16 16 Comparator5 Comparator4 Counter4_5 a a a a i t denotes interrupt events denotes trigger events denotes interrupt trigger and pulse generate events Note Figure 6 10 5 PWM Complementary Mode Architecture Diagram 6 10 4 Basic Configuration 6 10 4 1 PWM0 Basic Configuration Clock ...

Page 342: ... 5 MFP5 PB 7 MFP5 PC 0 MFP5 PC 2 MFP5 PC 4 MFP5 PC 6 MFP5 PD 2 MFP2 PD 4 MFP2 PWM0_CH1 PA 0 MFP5 PA 2 MFP5 PA 4 MFP5 PB 4 MFP5 PB 6 MFP5 PC 1 MFP5 PC 3 MFP5 PC 5 MFP5 PC 7 MFP5 PD 3 MFP2 PD 5 MFP2 PWM0_CH2 PA 1 MFP6 PA 3 MFP6 PA 5 MFP6 PB 5 MFP6 PB 7 MFP6 PC 0 MFP6 PC 2 MFP6 PC 4 MFP6 PC 6 MFP6 PD 6 MFP2 PWM0_CH3 PA 0 MFP6 PA 2 MFP6 PA 4 MFP6 ...

Page 343: ...MFP7 PA 2 MFP7 PA 4 MFP7 PB 4 MFP7 PB 6 MFP7 PC 1 MFP7 PC 3 MFP7 PC 5 MFP7 PC 7 MFP7 PD 1 MFP7 6 10 5 Functional Description 6 10 5 1 PWM Prescaler The PWM prescaler is used to divide clock source prescaler counting CLKPSC 1 times PWM counter only count once The prescale double buffer is setting by CLKPSC PWM_CLKPSCn 11 0 n 0 2 4 bits Figure 6 10 6 is an example of PWM channel 0 prescale waveform ...

Page 344: ...ll be set 0 by hardware automatically 0 1 CNT PWM_CNT0 15 0 4 Prescale counter 3 2 1 0 CNTEN0 PWM_CNTEN 0 4 3 2 1 0 4 3 2 1 0 3 2 1 0 4 4 3 0 2 1 2 PWM0_CLK 4 3 2 1 0 x CNTCLR0 PWM_CNTCLR 0 0 PCLK Figure 6 10 7 PWMx Counter Waveform When Setting Clear Counter 6 10 5 3 Up Counter Type When PWM counter is set to up counter type CNTTYPEn PWM_CTL1 2n 1 2n n 0 1 5 is 0x0 it starts up counting from 0 to...

Page 345: ...unter counts to PERIOD and prescale counts to 0 Figure 6 10 9 shows an example of down counter wherein PWM period time PERIOD 1 CLKPSC 1 PWMx_CLK 0 1 2 3 4 X 0 1 2 3 4 5 6 7 8 0 1 2 3 4 5 6 7 8 6 7 8 PWM Period PWM Period PWM Period PERIOD 5 PERIOD 8 PERIOD 8 zero point event period point event CNT PWM_CNTn 15 0 CNTENn PWM_CNTEN n 5 Note n denotes channel 0 1 5 Figure 6 10 9 PWM Down Counter Type ...

Page 346: ...h channel only has one comparator the value of CMPDATn register is continuously compared to the corresponding channel s counter value In Complementary mode each paired channels has two comparators and the value of CMPDATn and CMPDATm n 0 2 4 m 1 3 5 registers are continuously compared to the complementary even channel s counter value because of odd channel s counter is useless For example channel ...

Page 347: ... software hardware will load register value to the buffer register according to the loading mode timing The hardware action is based on the buffer value This can prevent asynchronously operation problem due to software and hardware asynchronism The PWM provides PBUF PWM_PBUFn 15 0 as the active PERIOD buffer register CMPBUF PWM_CMPBUFn 15 0 as the active CMPDAT buffer register The concept of doubl...

Page 348: ...ites CMPDAT DATA1 to CMPDAT at point 1 2 Hardware loads CMPDAT DATA1 to CMPBUF at the end of PWM period at point 2 3 Software writes PERIOD DATA1 to PERIOD at point 3 4 Hardware loads PERIOD DATA1 to PBUF at the end of PWM period at point 4 5 Software writes PERIOD DATA2 to PERIOD at point 5 6 Hardware loads PERIOD DATA2 to PBUF at the end of PWM period at point 6 CMPDAT DATA0 CMPU CMPDAT DATA1 PE...

Page 349: ...IOD DATA1 CMPBUF CMPDAT DATA1 PERIOD DATA2 PERIOD DATA2 point 1 point 2 point 3 Figure 6 10 14 Immediately Loading in Up Count Mode 6 10 5 10 Center Loading Mode When the CTRLDn PWM_CTL0 5 0 bit is set to 1 and PWM counter is set to up down count type CNTTYPEn PWM_CTL1 2n 1 2n n 0 1 5 is 0x2 PWM operates at center loading mode In center loading mode CMP PWM_CMPDATn 15 0 will load to active CMPBUF ...

Page 350: ...r events to generate PWM pulse The events are zero point period point in up counter type and down counter type center point in up down counter type and counter equal to comparator point in three types As to up down counter type there are two counter equal comparator points one at up count and the other at down count Besides Complementary mode has two comparators compared with counter and thus comp...

Page 351: ...2 down counter type Table 6 10 3 and up down counter type Table 6 10 4 By using event priority user can easily generate 0 to 100 duty pulse as shown in Figure 6 10 17 0 1 2 3 4 3 2 1 0 1 2 3 4 3 2 1 0 CMPDAT 0 0 Duty CMPDAT 1 25 Duty CMPDAT 2 50 Duty CMPDAT 3 75 Duty CMPDAT 4 100 Duty DIRF PWM period PWM period 0 1 2 3 4 0 1 2 3 4 CMPDAT 0 0 Duty CMPDAT 1 20 Duty CMPDAT 2 40 Duty CMPDAT 3 60 Duty ...

Page 352: ...period and duty as shown in Figure 6 10 18 PWM_CH2 PWM_CH0 Setting OUTMODE0 PWM_CTL1 24 0x0 PWM_CH1 PWM_CH3 PWM_CH4 PWM_CH5 Setting OUTMODE2 PWM_CTL1 25 0x0 Setting OUTMODE4 PWM_CTL1 26 0x0 Figure 6 10 18 PWM Independent Mode Waveform 6 10 5 15 Complementary mode Complementary mode is enabled when the paired channel corresponding PWMMODEn PWM_CTL1 26 24 bit set to 1 In this mode there are 3 PWM ge...

Page 353: ... to six steps to control the output of PWM channels In independent mode there are Mask Brake Pin Polarity and Output Enable four steps as shown in Figure 6 10 20 In complementary mode it needs two more steps to precede these four steps Complementary channels and Dead Time Insertion as shown in Figure 6 10 21 Mask Data MSKDAT0 PWM_MSK 0 PINV0 PWM_POLCTL 0 POEN0 PWM_POEN 0 Brake BRKAEVEN PWM_BRKCTL0...

Page 354: ...ing formula Dead time DTCNT PWM_DTCTLn 11 0 1 CLKPSC PWM_CLKPSCn 11 0 1 PWMx_CLK period Please note that the PWM_DTCTLn_m are write protected registers Figure 6 10 22 indicates the dead time insertion for one pair of PWM signals PWM_CH0 without Dead Time PWM_CH1 without Dead Time PWM_CH0 with Dead Time PWM_CH1 with Dead Time Dead Time Interval Effect of Dead Time for complementary pairs Figure 6 1...

Page 355: ... clock cycles a filter will recognize the effective edge of the brake signal In addition it can be inversed by setting the BRKxPINV x denotes input external pin 0 or 1 bits of BNF register to realize the polarity setup for the brake control signals Set BRKxPINV bit to 0 brake event will occurred when PWMx_BRAKEy x 0 1 y 0 1 pin status is from low to high set BRKxPINV to 1 brake event will occurred...

Page 356: ...0 or BRKLIF1 PWM_INTSTS1 9 8 BRKLIEN0_1 PWM_INTEN1 8 Edge Detect Brake Source Level Detect Brake Source Note denotes falling edge detect BRKESTS0 PWM_INTSTS1 16 PWM_OUT1 PWM_OUT0 BRKLSTS0 PWM_INTSTS1 24 BRKESTS1 PWM_INTSTS1 17 BRKLSTS1 PWM_INTSTS1 25 BRKAEVEN PWM_BRKCTL0 17 16 BRKAODD PWM_BRKCTL0 19 18 Figure 6 10 25 Brake Block Diagram for PWMx_CH0 and PWMx_CH1 Pair Figure 6 10 26 illustrates the...

Page 357: ...KLIF1 BRKLIF0 s w clear BRKLSTS0 BRKLSTS1 s w clear PWM_CH1 No matter BRKLIF0 or BRKLIF1 clear or not while no brake event occur brake state resume at next start of PWM period Note Output Brake State Setting BRKAEVEN 3 High BRKAODD 2 Low Figure 6 10 27 Level Detector Waveform for PWMx_CH0 and PWMx_CH1 Pair The two kinds of detectors detect the same six brake sources two from external input signals...

Page 358: ...1_O BRKP0LEN PWM_BRKCTL0 12 Brake Noise Filter BRKP1LEN PWM_BRKCTL0 13 CPO0LBEN PWM_BRKCTL0 8 CPO1LBEN PWM_BRKCTL0 9 Brake Noise Filter Brake System Fail SYSLBEN PWM_BRKCTL0 15 BRKETRG0 PWM_SWBRK 0 Figure 6 10 28 Brake Source Block Diagram CSSBRKEN PWM_FAILBRK 0 Clock Fail BODBRKEN PWM_FAILBRK 1 Brown Out Detect CORBRKEN PWM_FAILBRK 3 Core Lockup Brake Source Brake System Fail Figure 6 10 29 Brake...

Page 359: ... to start counting 6 10 5 22 PWM Interrupt Generator There are three independent interrupts for each PWM as shown in Figure 6 10 31 The 1st PWM interrupt PWM_INT comes from PWM complementary pair events The counter can generate the Zero point Interrupt Flag ZIFn PWM_INTSTS0 n n 0 2 4 and the Period point Interrupt Flag PIFn PWM_INTSTS0 n 8 n 0 2 4 When PWM channel n s counter equals to the compara...

Page 360: ... PWM_CH1 Pair Interrupt Architecture Diagram 6 10 5 23 PWM Trigger ADC Generator PWM can be one of the ADC conversion trigger source Each PWM paired channels share the same trigger source Setting TRGSELn is to select the trigger sources where TRGSELn is TRGSEL0 TRGSEL1 and TRGSEL5 which are located in PWM_ADCTS0 3 0 PWM_ADCTS0 11 8 PWM_ADCTS0 19 16 PWM_ADCTS0 27 24 PWM_ADCTS1 3 0 and PWM_ADCTS1 11...

Page 361: ...nput and the PWM output share the same pin and counter The counter can operate in up or down counter type The capture function will always latch the PWM counter to the RCAPDATn PWM_RCAPDATn 15 0 bits or the FCAPDATn PWM_FCAPDATn 15 0 bits if the input channel has a rising transition or a falling transition respectively The capture function will also generate an interrupt CAP_INT using PWM_INT vect...

Page 362: ...s enabled But at the second time the falling edge does not result in a reload because of the disabled FCRLDENn bit In this example the counter also reloads at the rising edge of the capture input because the RCRLDENn bit is enabled too Moreover if the case is setup as the up counter type the counter will reload the value zero and count up to the value PERIOD Figure 6 10 35 also illustrates the tim...

Page 363: ...r to 1 For the negative pulse case the channel low pulse width is calculated as PWM_PERIODn 1 PWM_RCAPDATn PWM counter time where one PWM counter time is CLKPSC 1 PWMx_CLK clock time In Figure 6 10 35 the low pulse width is 8 1 5 4 PWM counter time For the positive pulse case the channel high pulse width is calculated as PWM_PERIODn 1 PWM_FCAPDATn PWM counter time where one PWM counter time is CLK...

Page 364: ..._3 PWM_PDMACTL 12 and CHSEL4_5 PWM_PDMACTL 20 bit is used to decide either channel n or channel m can be serviced by the PDMA channel Figure 6 10 36 is capture PDMA waveform In this case the CHSEL0_1 PWM_PDMACTL 4 bit is set to 0 Hence the PDMA will service channel 0 for the capture data transfer CAPMOD0_1 PWM_PDMACTL 2 1 bits are set to 3 That means both of the rising and falling edge captured da...

Page 365: ...0 PWM_PERIOD4 PWM_BA 0x40 R W PWM Period Register 4 0x0000_0000 PWM_CMPDAT0 PWM_BA 0x50 R W PWM Comparator Register 0 0x0000_0000 PWM_CMPDAT1 PWM_BA 0x54 R W PWM Comparator Register 1 0x0000_0000 PWM_CMPDAT2 PWM_BA 0x58 R W PWM Comparator Register 2 0x0000_0000 PWM_CMPDAT3 PWM_BA 0x5C R W PWM Comparator Register 3 0x0000_0000 PWM_CMPDAT4 PWM_BA 0x60 R W PWM Comparator Register 4 0x0000_0000 PWM_CM...

Page 366: ... Trigger ADC Source Select Register 1 0x0000_0000 PWM_SSCTL PWM_BA 0x110 R W PWM Synchronous Start Control Register 0x0000_0000 PWM_SSTRG PWM_BA 0x114 W PWM Synchronous Start Trigger Register 0x0000_0000 PWM_STATUS PWM_BA 0x120 R W PWM Status Register 0x0000_0000 PWM_CAPINEN PWM_BA 0x200 R W PWM Capture Input Enable Register 0x0000_0000 PWM_CAPCTL PWM_BA 0x204 R W PWM Capture Control Register 0x00...

Page 367: ...00_0000 PWM_CAPIEN PWM_BA 0x250 R W PWM Capture Interrupt Enable Register 0x0000_0000 PWM_CAPIF PWM_BA 0x254 R W PWM Capture Interrupt Flag Register 0x0000_0000 PWM_PBUF0 PWM_BA 0x304 R PWM PERIOD0 Buffer 0x0000_0000 PWM_PBUF2 PWM_BA 0x30C R PWM PERIOD2 Buffer 0x0000_0000 PWM_PBUF4 PWM_BA 0x314 R PWM PERIOD4 Buffer 0x0000_0000 PWM_CMPBUF0 PWM_BA 0x31C R PWM CMPDAT0 Buffer 0x0000_0000 PWM_CMPBUF1 P...

Page 368: ...matter ICE debug mode acknowledged or not Note This bit is write protected Refer to SYS_REGLCTL register 30 DBGHALT ICE Debug Mode Counter Halt Write Protect If counter halt is enabled PWM all counters will keep current value until exit ICE debug mode 0 ICE debug mode counter halt Disable 1 ICE debug mode counter halt Enable Note This bit is write protected Refer to SYS_REGLCTL register 29 22 Rese...

Page 369: ... PWM complementary mode Note When operating in group function these bits must all set to the same mode 23 10 Reserved Reserved 9 8 CNTTYPE4 PWM Counter Behavior Type 4 The two bits control channel5 and channel4 00 Up counter type supported in capture mode 01 Down count type supported in capture mode 10 Up down counter type 11 Reserved 7 6 Reserved Reserved 5 4 CNTTYPE2 PWM Counter Behavior Type 2 ...

Page 370: ...M0A21 M0A23 Series May 06 2022 Page 370 of 746 Rev 1 02 M0A21 M0A23 SERIES TECHNICAL REFERENCE MANUAL 11 Reserved ...

Page 371: ...ption 31 19 Reserved Reserved 18 16 ECLKSRC4 PWM_CH45 External Clock Source Select 000 PWMx_CLK x denotes 0 or 1 001 TIMER0 overflow 010 TIMER1 overflow 011 TIMER2 overflow 100 TIMER3 overflow Others Reserved 15 11 Reserved Reserved 10 8 ECLKSRC2 PWM_CH23 External Clock Source Select 000 PWMx_CLK x denotes 0 or 1 001 TIMER0 overflow 010 TIMER1 overflow 011 TIMER2 overflow 100 TIMER3 overflow Other...

Page 372: ...3 PWM_BA 0x18 R W PWM Clock Prescale Register 2 3 0x0000_0000 PWM_CLKPSC4_5 PWM_BA 0x1C R W PWM Clock Prescale Register 4 5 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved CLKPSC 7 6 5 4 3 2 1 0 CLKPSC Bits Description 31 12 Reserved Reserved 11 0 CLKPSC PWM Counter Clock Prescale The clock of PWM counter is decided by clock prescaler Ea...

Page 373: ...Reserved 7 6 5 4 3 2 1 0 Reserved CNTEN4 Reserved CNTEN2 Reserved CNTEN0 Bits Description 31 5 Reserved Reserved 4 CNTEN4 PWM Counter Enable Bit 4 0 PWM Counter and clock prescaler Stop Running 1 PWM Counter and clock prescaler Start Running 3 Reserved Reserved 2 CNTEN2 PWM Counter Enable Bit 2 0 PWM Counter and clock prescaler Stop Running 1 PWM Counter and clock prescaler Start Running 1 Reserve...

Page 374: ...erved 7 6 5 4 3 2 1 0 Reserved CNTCLR4 Reserved CNTCLR2 Reserved CNTCLR0 Bits Description 31 5 Reserved Reserved 4 CNTCLR4 Clear PWM Counter Control Bit 4 It is automatically cleared by hardware 0 No effect 1 Clear 16 bit PWM counter to 0000H 3 Reserved Reserved 2 CNTCLR2 Clear PWM Counter Control Bit 2 It is automatically cleared by hardware 0 No effect 1 Clear 16 bit PWM counter to 0000H 1 Reser...

Page 375: ... 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 PERIOD 7 6 5 4 3 2 1 0 PERIOD Bits Description 31 16 Reserved Reserved 15 0 PERIOD PWM Period Register Up Count mode In this mode PWM counter counts from 0 to PERIOD and restarts from 0 Down Count mode In this mode PWM counter counts from PERIOD to 0 and restarts from PERIOD PWM period time PERIOD ...

Page 376: ...PWM Comparator Register 4 0x0000_0000 PWM_CMPDAT5 PWM_BA 0x64 R W PWM Comparator Register 5 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 CMP 7 6 5 4 3 2 1 0 CMP Bits Description 31 16 Reserved Reserved 15 0 CMP PWM Comparator Register CMP is used to compare with CNTR to generate PWM waveform interrupt and trigger ADC In independent mode PWM_CM...

Page 377: ... from PWM_CLK 1 Dead time clock source from prescaler output Note This bit is write protected Refer to REGWRPROT register 23 17 Reserved Reserved 16 DTEN Enable Dead time Insertion for PWM Pair Write Protect PWM_CH0 andPWM_CH1 PWM_CH2 andPWM_CH3 PWM_CH4 andPWM_CH5 Dead time insertion is only active when this pair of complementary PWM is enabled If dead time insertion is inactive the outputs of pin...

Page 378: ...98 R PWM Counter Register 2 0x0000_0000 PWM_CNT4 PWM_BA 0xA0 R PWM Counter Register 4 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved DIRF 15 14 13 12 11 10 9 8 CNT 7 6 5 4 3 2 1 0 CNT Bits Description 31 17 Reserved Reserved 16 DIRF PWM Direction Indicator Flag Read Only 0 Counter is counting down 1 Counter is counting up 15 0 CNT PWM Data Register Read Only User can...

Page 379: ...TL0 Bits Description 31 28 Reserved Reserved 17 2n 16 2n n 0 1 5 PRDPCTLn PWM Period or CenterPoint Control 00 Do nothing 01 PWM period orcente point output Low 10 PWM period orcenter point output High 11 PWM period orcenter point output Toggle Note 1 PWM can control output level when PWM counter counts to PERIODn 1 Note 2 This bit is center point control when PWM counter operating in up down coun...

Page 380: ...n 16 2n n 0 1 5 CMPDCTLn PWM Compare Down Point Control 00 Do nothing 01 PWM compare down point output Low 10 PWM compare down point output High 11 PWM compare down point output Toggle Note 1 PWM can control output level when PWM counter counts down to CMPDAT Note 2 In complementary mode CMPDCTL1 3 5 is used as another CMPDCTL for channel 0 2 4 15 12 Reserved Reserved 1 2n 2n n 0 1 5 CMPUCTLn PWM ...

Page 381: ...9 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 Reserved MSKEN5 MSKEN4 MSKEN3 MSKEN2 MSKEN1 MSKEN0 Bits Description 31 6 Reserved Reserved n n 0 1 5 MSKENn PWM Mask Enable Bits The PWM output signal will be masked when this bit is enabled The corresponding PWM channel n will output MSKDATn PWM_MSK 5 0 data 0 PWM output signal is non masked ...

Page 382: ...7 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 Reserved MSKDAT5 MSKDAT4 MSKDAT3 MSKDAT2 MSKDAT1 MSKDAT0 Bits Description 31 6 Reserved Reserved n n 0 1 5 MSKDATn PWM Mask Data Bit This data bit control the state of PWMn output pin if corresponding mask function is enabled Each bit n controls the corresponding PWM channel n 0 Output logic low to ...

Page 383: ...erved 23 17 Reserved Reserved 16 BK0SRC Brake 0 Pin Source Select For PWM0 setting 0 Brake 0 pin source come from PWM0_BRAKE0 1 Reserved 15 BRK1PINV Brake 1 Pin Inverse 0 The state of pin PWMx_BRAKE1 is passed to the negative edge detector 1 The inversed state of pin PWMx_BRAKE1 is passed to the negative edge detector 14 12 BRK1FCNT Brake 1 Edge Detector Filter Count The register bits control the ...

Page 384: ... detector 6 4 BRK0FCNT Brake 0 Edge Detector Filter Count The register bits control the Brake0 filter counter to count from 0 to BRK1FCNT 3 1 BRK0NFSEL Brake 0 Edge Detector Filter Clock Selection 000 Filter clock HCLK 001 Filter clock HCLK 2 010 Filter clock HCLK 4 011 Filter clock HCLK 8 100 Filter clock HCLK 16 101 Filter clock HCLK 32 110 Filter clock HCLK 64 111 Filter clock HCLK 128 0 BRK0NF...

Page 385: ... BODBRKEN CSSBRKEN Bits Description 31 4 Reserved Reserved 3 CORBRKEN Core Lockup Detection Trigger PWM Brake Function 0 Enable Bit 0 Brake Function triggered by Core lockup detection Disabled 1 Brake Function triggered by Core lockup detection Enabled 2 Reserved Reserved 1 BODBRKEN Brown out Detection Trigger PWM Brake Function 0 Enable Bit 0 Brake Function triggered by BOD Disabled 1 Brake Funct...

Page 386: ... low level when level detect brake happened 11 PWM odd channel output high level when level detect brake happened Note These bits are write protected Refer to SYS_REGLCTL register 17 16 BRKAEVEN PWM Brake Action Select for Even Channel Write Protect 00 PWM even channel level detect brake function not affect channel output 01 PWM even channel output tri state when level detect brake happened 10 PWM...

Page 387: ...led 1 System Fail condition as edge detect brake source Enabled Note This bit is write protected Refer to SYS_REGLCTL register 6 Reserved Reserved 5 BRKP1EEN Enable PWMx_BRAKE1 Pin As Edge detect Brake Source Write Protect 0 BKP1 pin as edge detect brake source Disabled 1 BKP1 pin as edge detect brake source Enabled Note This bit is write protected Refer to SYS_REGLCTL register 4 BRKP0EEN Enable P...

Page 388: ...R W PWM Pin Polar Inverse Register 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 Reserved PINV5 PINV4 PINV3 PINV2 PINV1 PINV0 Bits Description 31 6 Reserved Reserved n n 0 1 5 PINVn PWM PIN Polar Inverse Control The register controls polarity state of PWM output 0 PWM output polar inverse Disabled 1 PWM output polar inv...

Page 389: ...ion Reset Value PWM_POEN PWM_BA 0xD8 R W PWM Output Enable Register 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 Reserved POEN5 POEN4 POEN3 POEN2 POEN1 POEN0 Bits Description 31 6 Reserved Reserved n n 0 1 5 POENn PWM Pin Output Enable Bits 0 PWM pin at tri state 1 PWM pin in output mode ...

Page 390: ...LTRG0 7 6 5 4 3 2 1 0 Reserved BRKETRG4 BRKETRG2 BRKETRG0 Bits Description 31 11 Reserved Reserved 8 n 2 n 0 2 4 BRKLTRGn PWM Level Brake Software Trigger Write Only Write Protect Write 1 to this bit will trigger level brake and set BRKLIFn to 1 in PWM_INTSTS1 register Note This bit is write protected Refer to SYS_REGLCTL register 7 3 Reserved Reserved n 2 n 0 2 4 BRKETRGn PWM Edge Brake Software ...

Page 391: ...rrupt Enabled Note In complementary mode CMPDIEN1 3 5 is used as another CMPDIEN for channel 0 2 4 23 22 Reserved Reserved 16 n n 0 1 5 CMPUIENn PWM Compare Up Count Interrupt Enable Bits Each bit n controls the corresponding PWM channel n 0 Compare up count interrupt Disabled 1 Compare up count interrupt Enabled Note In complementary mode CMPUIEN1 3 5 is used as another CMPUIEN for channel 0 2 4 ...

Page 392: ... 1 Zero point interrupt Enabled Note Odd channels will read always 0 at complementary mode 3 Reserved Reserved 2 ZIEN2 PWM Zero Point Interrupt Enable Bit 2 0 Zero point interrupt Disabled 1 Zero point interrupt Enabled Note Odd channels will always read 0 at complementary mode 1 Reserved Reserved 0 ZIEN0 PWM Zero Point Interrupt Enable Bit 0 0 Zero point interrupt Disabled 1 Zero point interrupt ...

Page 393: ...or channel2 3 Enabled Note This bit is write protected Refer to SYS_REGLCTL register 8 BRKLIEN0_1 PWM Level detect Brake Interrupt Enable for Channel0 1 Write Protect 0 Level detect Brake interrupt for channel0 1 Disabled 1 Level detect Brake interrupt for channel0 1 Enabled Note This bit is write protected Refer to SYS_REGLCTL register 7 3 Reserved Reserved 2 BRKEIEN4_5 PWM Edge detect Brake Inte...

Page 394: ...is used as another CMPDIF for channel 0 2 4 23 22 Reserved Reserved 21 16 CMPUIFn PWM Compare Up Count Interrupt Flag Flag is set by hardware when PWM counter up count and reaches PWM_CMPDATn software can clear this bit by writing 1 to it Note In complementary mode CMPUIF1 3 5 is used as another CMPUIF for channel 0 2 4 15 13 Reserved Reserved 12 PIF4 PWM Period Point Interrupt Flag 4 This bit is ...

Page 395: ...ing 1 3 Reserved Reserved 2 ZIF2 PWM Zero Point Interrupt Flag 2 This bit is set by hardware when PWM_CH2 counter reaches 0 Note This bit can be cleared to 0 by software writing 1 1 Reserved Reserved 0 ZIF0 PWM Zero Point Interrupt Flag 0 This bit is set by hardware when PWM_CH0 counter reaches 0 Note This bit can be cleared to 0 by software writing 1 ...

Page 396: ...t PWM period finished The PWM waveform will start output from next full PWM period 23 22 Reserved Reserved 16 n n 0 1 5 BRKESTSn PWM Channel N Edge detect Brake Status Read Only 0 PWM channel n edge detect brake state is released 1 When PWM channel n edge detect brake detects a falling edge of any enabled brake source this flag will be set to indicate the PWM channel n at brake state Note This bit...

Page 397: ... 1 PWM_CH3 Trigger ADC function Enabled 30 28 Reserved Reserved 27 24 TRGSEL3 PWM_CH3 Trigger ADC Source Select 0000 PWM_CH2 zero point 0001 PWM_CH2 period point 0010 PWM_CH2 zero or period point 0011 PWM_CH2 up count CMPDAT point 0100 PWM_CH2 down count CMPDAT point 0101 Reserved 0110 Reserved 0111 Reserved 1000 PWM_CH3 up count CMPDAT point 1001 PWM_CH3 down count CMPDAT point Others reserved 23...

Page 398: ...iod point 0011 PWM_CH0 up count CMPDAT point 0100 PWM_CH0 down count CMPDAT point 0101 Reserved 0110 Reserved 0111 Reserved 1000 PWM_CH1 up count CMPDAT point 1001 PWM_CH1 down count CMPDAT point Others reserved 7 TRGEN0 PWM_CH0 Trigger ADC Enable Bit 0 PWM_CH0 Trigger ADC function Disabled 1 PWM_CH0 Trigger ADC function Enabled 6 4 Reserved Reserved 3 0 TRGSEL0 PWM_CH0 Trigger ADC Source Select 0...

Page 399: ...ger ADC function Disabled 1 PWM_CH5 Trigger ADC function Enabled 14 12 Reserved Reserved 11 8 TRGSEL5 PWM_CH5 Trigger ADC Source Select 0000 PWM_CH4 zero point 0001 PWM_CH4 period point 0010 PWM_CH4 zero or period point 0011 PWM_CH4 up count CMPDAT point 0100 PWM_CH4 down count CMPDAT point 0101 Reserved 0110 Reserved 0111 Reserved 1000 PWM_CH5 up count CMPDAT point 1001 PWM_CH5 down count CMPDAT ...

Page 400: ...ge 400 of 746 Rev 1 02 M0A21 M0A23 SERIES TECHNICAL REFERENCE MANUAL 0100 PWM_CH4 down count CMPDAT point 0101 Reserved 0110 Reserved 0111 Reserved 1000 PWM_CH5 up count CMPDAT point 1001 PWM_CH5 down count CMPDAT point Others reserved ...

Page 401: ... Function Enable Bit 4 When synchronous start function is enabled the PWM_CH4 counter enable bit CNTEN4 can be enabled by writing PWM synchronous start trigger bit CNTSEN 0 PWM synchronous start function Disabled 1 PWM synchronous start function Enabled 3 Reserved Reserved 2 SSEN2 PWM Synchronous Start Function Enable Bit 2 When synchronous start function is enabled the PWM_CH2 counter enable bit ...

Page 402: ...24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 Reserved CNTSEN Bits Description 31 1 Reserved Reserved 0 CNTSEN PWM Counter Synchronous Start Enable Write Only PWM counter synchronous enable function is used to make selected PWM channels include PWM0_CHx start counting at the same time Writing this bit to 1 will also set the counter enable bit CNTENn n ...

Page 403: ...er event has occurred Note This bit can be cleared by software writing 1 15 5 Reserved Reserved 4 CNTMAX4 Time base Counter 4 Equal to 0xFFFF Latched Flag 0 The time base counter never reached its maximum value 0xFFFF 1 The time base counter reached its maximum value Note This bit can be cleared by software writing 1 3 Reserved Reserved 2 CNTMAX2 Time base Counter 2 Equal to 0xFFFF Latched Flag 0 ...

Page 404: ...27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 Reserved CAPINEN5 CAPINEN4 CAPINEN3 CAPINEN2 CAPINEN1 CAPINEN0 Bits Description 31 6 Reserved Reserved n n 0 1 5 CAPINENn Capture Input Enable Bits 0 PWM Channel capture input path Disabled The input of PWM channel capture function is always regarded as 0 1 PWM Channel capture input path Enabled Th...

Page 405: ...d Reserved 24 n n 0 1 5 FCRLDENn Falling Capture Reload Enable Bits 0 Falling capture reload counter Disabled 1 Falling capture reload counter Enabled 23 22 Reserved Reserved 16 n n 0 1 5 RCRLDENn Rising Capture Reload Enable Bits 0 Rising capture reload counter Disabled 1 Rising capture reload counter Enabled 15 14 Reserved Reserved 8 n n 0 1 5 CAPINVn Capture Inverter Enable Bits 0 Capture sourc...

Page 406: ...2 1 0 Reserved CRLIFOV5 CRLIFOV4 CRLIFOV3 CRLIFOV2 CRLIFOV1 CRLIFOV0 Bits Description 31 14 Reserved Reserved 8 n n 0 1 5 CFLIFOVn Capture Falling Latch Interrupt Flag Overrun Status Read Only This flag indicates if falling latch happened when the corresponding CFLIF is 1 Note This bit will be cleared automatically when user clear corresponding CFLIF 7 6 Reserved Reserved n n 0 1 5 CRLIFOVn Captur...

Page 407: ...WM Rising Capture Data Register 2 0x0000_0000 PWM_RCAPDAT3 PWM_BA 0x224 R PWM Rising Capture Data Register 3 0x0000_0000 PWM_RCAPDAT4 PWM_BA 0x22C R PWM Rising Capture Data Register 4 0x0000_0000 PWM_RCAPDAT5 PWM_BA 0x234 R PWM Rising Capture Data Register 5 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 RCAPDAT 7 6 5 4 3 2 1 0 RCAPDAT Bits Desc...

Page 408: ...M Falling Capture Data Register 2 0x0000_0000 PWM_FCAPDAT3 PWM_BA 0x228 R PWM Falling Capture Data Register 3 0x0000_0000 PWM_FCAPDAT4 PWM_BA 0x230 R PWM Falling Capture Data Register 4 0x0000_0000 PWM_FCAPDAT5 PWM_BA 0x238 R PWM Falling Capture Data Register 5 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 FCAPDAT 7 6 5 4 3 2 1 0 FCAPDAT Bits D...

Page 409: ...tured data transferred to memory through PDMA when CAPMOD4_5 11 0 PWM_FCAPDAT4 5 is the first captured data to memory 1 PWM_RCAPDAT4 5 is the first captured data to memory Note If the PDMA function is not supported this bit field will become invalid Please refer to section 3 2 NuMicro M0A21 M0A23 Series Selection Guide for detailed information 18 17 CAPMOD4_5 Select PWM_RCAPDAT4 5 or PWM_FCAPDAT4 ...

Page 410: ... become invalid Please refer to section 3 2 NuMicro M0A21 M0A23 Series Selection Guide for detailed information 7 5 Reserved Reserved 4 CHSEL0_1 Select Channel 0 1 to Do PDMA Transfer 0 Channel0 1 Channel1 Note If the PDMA function is not supported this bit field will become invalid Please refer to section 3 2 NuMicro M0A21 M0A23 Series Selection Guide for detailed information 3 CAPORD0_1 Capture ...

Page 411: ...000_0000 PWM_PDMACAP4_5 PWM_BA 0x248 R PWM Capture Channel 45 PDMA Register 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 CAPBUF 7 6 5 4 3 2 1 0 CAPBUF Bits Description 31 16 Reserved Reserved 15 0 CAPBUF PWM Capture PDMA Register Read Only This register is used as a buffer to transfer PWM capture rising or falling data to memory by PDMA Note I...

Page 412: ...4 13 12 11 10 9 8 Reserved CAPFIEN5 CAPFIEN4 CAPFIEN3 CAPFIEN2 CAPFIEN1 CAPFIEN0 7 6 5 4 3 2 1 0 Reserved CAPRIEN5 CAPRIEN4 CAPRIEN3 CAPRIEN2 CAPRIEN1 CAPRIEN0 Bits Description 31 14 Reserved Reserved 8 n n 0 1 5 CAPFIENn PWM Capture Falling Latch Interrupt Enable Bits 0 Capture falling edge latch interrupt Disabled 1 Capture falling edge latch interrupt Enabled 7 6 Reserved Reserved n n 0 1 5 CAP...

Page 413: ...n n 0 1 5 CFLIFn PWM Capture Falling Latch Interrupt Flag 0 No capture falling latch condition happened 1 Capture falling latch condition happened this flag will be set to high Note 1 When Capture with PDMA operating CAPIF corresponding channel CFLIF will be cleared by hardware after PDMA transfer data Note 2 This bit is cleared by writing 1 to it 7 6 Reserved Reserved n n 0 1 5 CRLIFn PWM Capture...

Page 414: ..._PBUF0 PWM_BA 0x304 R PWM PERIOD0 Buffer 0x0000_0000 PWM_PBUF2 PWM_BA 0x30C R PWM PERIOD2 Buffer 0x0000_0000 PWM_PBUF4 PWM_BA 0x314 R PWM PERIOD4 Buffer 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 PBUF 7 6 5 4 3 2 1 0 PBUF Bits Description 31 16 Reserved Reserved 15 0 PBUF PWM Period Register Buffer Read Only Used as PERIOD active register ...

Page 415: ...1 Buffer 0x0000_0000 PWM_CMPBUF2 PWM_BA 0x324 R PWM CMPDAT2 Buffer 0x0000_0000 PWM_CMPBUF3 PWM_BA 0x328 R PWM CMPDAT3 Buffer 0x0000_0000 PWM_CMPBUF4 PWM_BA 0x32C R PWM CMPDAT4 Buffer 0x0000_0000 PWM_CMPBUF5 PWM_BA 0x330 R PWM CMPDAT5 Buffer 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 CMPBUF 7 6 5 4 3 2 1 0 CMPBUF Bits Description 31 16 Reserv...

Page 416: ...ddress Match AAD mode wake up function Supports 8 bit receiver buffer time out detection function Programmable transmitting data delay time between the last stop and the next start bit by setting DLY UART_TOUT 15 8 Supports Auto Baud Rate measurement and baud rate compensation function Supports 9600 bps for UART_CLK is selected LXT Supports break error frame error parity error and receive transmit...

Page 417: ...on Mode nCTS Wake up Imcoming Data Wake up Received Data FIFO reached threshold Wake up RS 485 Address Match AAD mode Wake up Auto Baud Rate Measurement STOP Bit Length 1 1 5 2 bit 1 2 bit Word Length 5 6 7 8 bits 6 13 bits Even Odd Parity Stick Bit Note Supported Table 6 11 1 NuMicro M0A21 M0A23 Series UART Features 6 11 3 Block Diagram The UART clock control and block diagram are shown in Figure...

Page 418: ... 32 768kHz LXT 48MHz HIRC UART1SEL CLK_CLKSEL1 30 28 UART1DIV CLK_CLKDIV0 15 12 UART1CKEN CLK_APBCLK0 17 UART1_CLK 1 UART1DIV 1 100 PCLK1 101 38 4kHz LIRC 101 38 4kHz LIRC Note1 Before clock switching both the pre selected and newly selected clock sources must be turned on and stable Note2 Without PLL function the clock source will be fixed at PCLK0 1 the same as UARTxSEL 3 b100 Please refer to se...

Page 419: ...fered with a 16 bytes FIFO plus three error bits BIF UART_FIFOSTS 6 FEF UART_FIFOSTS 5 PEF UART_FIFOSTS 4 to reduce the number of interrupts presented to the CPU TX Shift Register This block is responsible for shifting out the transmitting data serially RX Shift Register This block is responsible for shifting in the receiving data serially Modem Control and Status Register This register controls t...

Page 420: ...upt RLSINT Receive Line Status Interrupt parity error or frame error or break error MODEMINT MODEM Status Interrupt RXTOINT Receiver Buffer Time out Interrupt BUFERRINT Buffer Error Interrupt LININT LIN Bus Interrupt WKINT Wake up Interrupt ABRINT Auto Baud Rate Interrupt SWBEINT Single wire Bit Error Detect Interrupt Table 6 11 2 UART Interrupt 6 11 4 Basic Configuration The basic configurations ...

Page 421: ...ck in UART1CKEN CLK_APBCLK0 17 Reset UART1 controller in UART1RST SYS_IPRST1 17 Pin Configuration Group Pin Name GPIO MFP UART1 UART1_RXD PA 0 PA 1 PA 2 PA 3 PA 4 PA 5 PB 4 PB 5 PB 6 PB 7 PC 0 PC 1 PC 2 PC 3 PC 4 PC 5 PC 6 PC 7 MFP29 UART1_TXD PA 0 PA 1 PA 2 PA 4 PA 5 PB 4 PB 5 PB 6 PB 7 PC 0 PC 1 PC 2 PC 3 PC 4 PC 5 PC 6 PC 7 MFP28 UART1_nCTS PD 2 PD 6 MFP6 PB 4 MFP30 UART1_nRTS PD 3 PD 7 MFP6 PC...

Page 422: ... BAUDM0 Baud Rate Equation Mode 0 0 0 UART_CLK 16 BRD 2 Mode 1 1 0 UART_CLK EDIVM1 1 BRD 2 EDIVM1 must 8 Mode 2 1 1 UART_CLK BRD 2 If UART_CLK 3 HCLK BRD must 8 If UART_CLK 3 HCLK BRD must 3 N 1 N is the smallest integer larger than or equal to the ratio of UART_CLK HCLK For example if 3 HCLK UART_CLK 4 HCLK BRD must 11 if 4 HCLK UART_CLK 5 HCLK BRD must 14 If the UART_CLK is selected from LXT BRD...

Page 423: ...s negative compensation for each bit decrease one module clock in the compensated bit There is 9 bit location BRCOMP 8 0 UART_BRCOMP 8 0 can be configured by user to define the relative bit is compensated or not BRCOMP 7 0 is used to define the compensation of DAT UART_DAT 7 0 and BRCOMP 8 is used to define PARITY UART_DAT 8 Example 1 UART s peripheral clock 32 768 kHz and baud rate is 9600 Baud r...

Page 424: ...he measuring baud rate is loaded to BRD UART_BAUD 15 0 Both of the BAUDM1 UART_BAUD 29 and BAUDM0 UART_BAUD 28 are set to 1 automatically UART RX data from Start bit to 1st rising edge time is set by 2ABRDBITS bit time in Auto Baud Rate function detection frame The 2ABRDBITS bit time from Start bit to the 1st rising edge is calculated by setting ABRDBITS UART_ALTCTL 20 19 Setting ABRDEN UART_ALTCT...

Page 425: ...BRDTOIF UART_FIFOSTS 2 is set if auto baud rate counter is overflow 7 Go to Step 3 6 11 5 4 UART Controller Transmit Delay Time Value The UART controller programs DLY UART_TOUT 15 8 to control the transfer delay time between the last stop bit and next start bit in transmission The unit is baud The operation is shown in Figure 6 11 4 Start TX Byte i Byte i 1 Stop DLY Start Figure 6 11 4 Transmit De...

Page 426: ...ition from low to high Power down mode HCLK nCTS CTSWKF stable count CPU run CTSACTLV UART_MODEMSTS 8 0 Note Stable count means HCLK source recovery stable count Figure 6 11 5 UART nCTS Wake up Case1 nCTS Wake up Case 2 nCTS transition from high to low Power down mode HCLK nCTS stable count CPU run CTSACTLV UART_MODEM 8 1 CTSWKF Note Stable count means HCLK source recovery stable count Figure 6 11...

Page 427: ... Received Data FIFO reached threshold wake up is shown in Figure 6 11 8 Note The UART controller clock source should be selected as LXT in Power down mode to receive data Power down mode HCLK RFRTWKF Start DATA0 DATA1 RX FIFO number reached RFITL UART_RXD DATAx stable count Note Stable count means HCLK source recovery stable count Figure 6 11 8 UART Received Data FIFO Reached Threshold Wake up RS ...

Page 428: ...T 7 0 that cause the Received Data FIFO threshold time out wake up wake up flag TOUTWKF UART_WKSTS 4 is generated The Received Data FIFO threshold time out wake up is shown in Figure 6 11 10 Note The UART controller clock source should be selected as LXT or LIRC in Power down mode to receive data Power down mode HCLK TOUTWKF Start DATA0 RX FIFO number not reached RFITL and Time out UART_RXD Time o...

Page 429: ... Detect Interrupt Flag ABRDIF Auto baud Rate Detect Time out Interrupt Flag ABRDTOIF Single wire Bit Error Detect Interrupt SWBEINT Table 6 11 9 describes the interrupt sources and flags The interrupt is generated when the interrupt flag is generated and the interrupt enable bit is set User must clear the interrupt flag after the interrupt is generated Interrupt Source Interrupt Indicator Interrup...

Page 430: ... Wake up Interrupt WKINT WKIEN WKIF WKIF CTSWKF Write 1 to CTSWKF WKIF DATWKF Write 1 to DATWKF WKIF RFRTWKF Write 1 to RFRTWKF WKIF RS485WKF Write 1 to RS485WKF WKIF TOUTWKF Write 1 to TOUTWKF WKIF LINWKF Write 1 to LINWKF Auto Baud Rate Interrupt ABRINT ABRIEN ABRIF ABRIF ABRDIF Write 1 to ABRDIF ABRIF ABRDTOIF Write 1 to ABRDTOIF Single wire Bit Error Detect Interrupt SWBEINT SWBEIEN SWBEIF N A...

Page 431: ...etting Parity Type SPE UART_LINE 5 EPE UART_LINE 4 PSS UART_LINE 7 PBE UART_LINE 3 Description No Parity x x x 0 No parity bit output Parity source from UART_DA T x x 1 1 Parity bit is generated and checked by software Odd Parity 0 0 0 1 Odd Parity is calculated by adding all the 1 s in a data stream and adding a parity bit to the total bits to make the total count an odd number Even Parity 0 1 0 ...

Page 432: ...trol function The CTSACTLV UART_MODEMSTS 8 can set nCTS pin input active state The CTSDETF UART_MODEMSTS 0 is set when any state change of nCTS pin input has occurred and then TX data will be automatically transmitted from TX FIFO nCTS pin input Active nCTS pin input status of UART function mode D0 D1 D2 D3 D4 D5 D6 D7 P Start bit Stop bit TX pin output MODEMINT interrupt Clear by softwave Clear b...

Page 433: ... read the RTSSTS UART_MODEM 13 bit to get real nRTS pin output voltage logic status Active nRTS pin output status of UART function mode default RTS control bit UART_MODEM 1 Set UART_MODEM 1 0 Set UART_MODEM 1 1 by software RTSSTS UART_MODEM 13 nRTS pin output RTSACTLV 0 RTSACTLV 1 Figure 6 11 14 UART nRTS Auto Flow with Software Control 6 11 5 9 IrDA Function Mode The UART controller also provides...

Page 434: ... layer specifies the use of Return to Zero Inverted RZI modulation scheme which represents logic 0 as an infra light pulse The modulated output pulse stream is transmitted to an external output driver and infrared light emitting diode The transmitted pulse width is specified as 3 16 period of baud rate IrDA SIR Receive Decoder The IrDA SIR Receive Decoder demodulates the Return to Zero bit stream ...

Page 435: ... all information transmitted is packed as frames a frame consists of a header provided by the master task and a response provided by a slave task The header provided by the master task consists of a break field and a sync field followed by a frame identifier frame ID The frame identifier uniquely defines the purpose of the frame The slave task is appointed for providing the response associated wit...

Page 436: ...hardware will control the header sending sequence automatically but software must filled frame ID data to PID UART_LINCTL 31 24 When operating in header selected mode in which the selected header is break field sync field and frame ID field the frame ID parity bit can be calculated by software or hardware depending on whether the IDPEN UART_LINCTL 9 bit is set or not HSEL Break Field Sync Field ID...

Page 437: ...oose the hardware transmission header field to only include break field by setting HSEL UART_LINCTL 23 22 to 00 2 Enable break detection function by setting BRKDETEN UART_LINCTL 10 3 Request break break sync delimiter transmission by setting the SENDH UART_LINCTL 8 4 Wait until the BRKDETF UART_LINSTS 8 flag is set to 1 by hardware 5 Request sync field transmission by writing 0x55 into UART_DAT re...

Page 438: ...NCTL 30 and P1 UART_LINCTL 31 otherwise user must filled frame ID and parity in this field PID start ID0 ID1 ID2 ID3 ID4 ID5 P0 P1 P0 ID0 xor ID1 xor ID2 xor ID4 P1 ID1 xor ID3 xor ID4 xor ID5 Figure 6 11 20 LIN Frame ID and Parity Format LIN Slave Mode The UART Controller supports LIN Slave mode To enable and initialize the LIN Slave mode the following steps are necessary 1 Set the UART_BAUD regi...

Page 439: ...abled at each break detect edge and stopped in the following conditions A LIN frame ID field has been received The header error flag asserts Writing 1 to the SLVSYNCF UART_LINSTS 3 to re search a new frame header Mute Mode and LIN Exit from Mute Mode Condition In Mute mode a LIN slave node will not receive any data until specified condition occurred It allows header detection only and prevents the...

Page 440: ...5 bit6 bit7 stop UART_BAUD m UART_BAUD n Measurement time Break field LIN Bus UART_BAUD Update baud rate if auto re sync function enable Figure 6 11 21 LIN Sync Field Measurement When operating in Automatic Resynchronization AR mode software must select the desired baud rate by setting the UART_BAUD register and hardware will store it at internal TEMP_REG register after each LIN break field the ti...

Page 441: ...UD register _ BAUD BAUD_ LIN value Both of TEMP_REG and BAUD_LIN are internal register If SLVDUEN value is 0 H W will not restore initial baud rate UART_BAUD UART_BAUD UART_BAUD update UART UART BAUD_LIN value is UART_BAUD m TEMP_REG value is UART_BAUD n Figure 6 11 23 UART_BAUD Update Sequence in AR mode if SLVDUEN is 0 Deviation Error on the Sync Field When operating in Automatic Resynchronizati...

Page 442: ...zation mode The sync field measure time out With Automatic Resynchronization mode LIN header reception time out 6 11 5 11 RS 485 Function Mode Another alternate function of UART controller is RS 485 function user must set UART_FUNCSEL 2 0 to 011 to enable RS 485 function and direction control provided by nRTS pin from an asynchronous serial port The RS 485 transceiver control is implemented by usi...

Page 443: ...ented by using the nRTS control signal from an asynchronous serial port The nRTS line is connected to the RS 485 transceiver enable pin such that setting the nRTS line to high logic 1 enables the RS 485 transceiver Setting the nRTS line to low logic 0 puts the transceiver into the tri state condition to disabled User can set RTSACTLV in UART_MODEM register to change the nRTS driving level Figure 6...

Page 444: ...FUNCSEL in UART_FUNCSEL to select RS 485 function 2 Program the RXOFF UART_FIFO 8 to determine enable or disable the receiver RS 485 receiver 3 Program the RS485NMM UART_ALTCTL 8 or RS485AAD UART_ALTCTL 9 mode 4 If the RS485AAD UART_ALTCTL 9 mode is selected the ADDRMV UART_ALTCTL 31 24 is programmed for auto address match value 5 Determine auto direction control by programming RS485AUD UART_ALTCT...

Page 445: ... state the SWBEIF UART_INTSTS 16 will be set Note1 Before writing data to TX buffer the bus state should be checked in idle state by RXIDLE UART_FIFOSTS 29 And the bus confliction may cause RX receive broken data Note2 Single wire does not support auto flow control Because the nRTS is actived automatic during TX transmitted 6 11 5 13 PDMA Transfer Function The UART controller supports PDMA transfe...

Page 446: ...W UART Modem Control Register 0x0000_0200 UART_MODEM STS x 0 1 UARTx_BA 0x14 R W UART Modem Status Register 0x0000_0110 UART_FIFOST S x 0 1 UARTx_BA 0x18 R W UART FIFO Status Register 0xB040_4000 UART_INTSTS x 0 1 UARTx_BA 0x1C R W UART Interrupt Status Register 0x0040_0002 UART_TOUT x 0 1 UARTx_BA 0x20 R W UART Time out Register 0x0000_0000 UART_BAUD x 0 1 UARTx_BA 0x24 R W UART Baud Rate Divider...

Page 447: ...UARTx_BA 0x40 R W UART Wake up Control Register 0x0000_0000 UART_WKSTS x 0 1 UARTx_BA 0x44 R W UART Wake up Status Register 0x0000_0000 UART_DWKCO MP x 0 1 UARTx_BA 0x48 R W UART Incoming Data Wake up Compensation Register 0x0000_0000 UART_LINRTO UT x 0 1 UARTx_BA 0x4C R W UART LIN Response Time out Register 0x00FF_FFFF UART_LINWKC TL x 0 1 UARTx_BA 0x50 R W UART LIN Wake up Control Register 0x000...

Page 448: ...o this bit the parity bit will be stored in transmitter FIFO If PBE UART_LINE 3 and PSS UART_LINE 7 are set the UART controller will send out this bit follow the DAT UART_DAT 7 0 through the UART_TXD Read Operation If PBE UART_LINE 3 and PSS UART_LINE 7 are enabled the parity bit can be read by this bit Note This bit has effect only when PBE UART_LINE 3 and PSS UART_LINE 7 are set 7 0 DAT Data Rec...

Page 449: ...nterrupt Enabled 21 19 Reserved Reserved 18 ABRIEN Auto baud Rate Interrupt Enable Bit 0 Auto baud rate interrupt Disabled 1 Auto baud rate interrupt Enabled 17 Reserved Reserved 16 SWBEIEN Single wire Bit Error Detection Interrupt Enable Bit Set this bit the Single wire Half Duplex Bit Error Detection Interrupt SWBEINT UART_INTSTS 24 is generated when Single wire Bit Error Detection SWBEIF UART_I...

Page 450: ...serted 12 ATORTSEN nRTS Auto flow Control Enable Bit 0 nRTS auto flow control Disabled 1 nRTS auto flow control Enabled Note When nRTS auto flow is enabled if the number of bytes in the RX FIFO equals the RTSTRGLV UART_FIFO 19 16 the UART will de assert nRTS signal 11 TOCNTEN Receive Buffer Time out Counter Enable Bit 0 Receive Buffer Time out counter Disabled 1 Receive Buffer Time out counter Ena...

Page 451: ...ES TECHNICAL REFERENCE MANUAL 0 Transmit holding register empty interrupt Disabled 1 Transmit holding register empty interrupt Enabled 0 RDAIEN Receive Data Available Interrupt Enable Bit 0 Receive data available interrupt Disabled 1 Receive data available interrupt Enabled ...

Page 452: ...Note This field is used for auto nRTS flow control 15 9 Reserved Reserved 8 RXOFF Receiver Disable Bit The receiver is disabled or not set 1 to disable receiver 0 Receiver Enabled 1 Receiver Disabled Note This bit is used for RS 485 Normal Multi drop mode It should be programmed before RS485NMM UART_ALTCTL 8 is programmed 7 4 RFITL RX FIFO Interrupt Trigger Level When the number of bytes in the re...

Page 453: ...ote2 Before setting this bit it should wait for the TXEMPTYF UART_FIFOSTS 28 be set 1 RXRST RX Field Software Reset When RXRST UART_FIFO 1 is set all the byte in the receiver FIFO and RX internal state machine are cleared 0 No effect 1 Reset the RX internal state machine and pointers Note1 This bit will automatically clear at least 3 UART peripheral clock cycles Note2 Before setting this bit it sh...

Page 454: ...5 function 8 TXDINV TX Data Inverted 0 Transmitted data signal inverted Disabled 1 Transmitted data signal inverted Enabled Note1 Before setting this bit TXRXDIS UART_FUNCSEL 3 should be set then waited for TXRXACT UART_FIFOSTS 31 is cleared When the configuration is done cleared TXRXDIS UART_FUNCSEL 3 to activate UART controller Note2 This bit is valid when FUNCSEL UART_FUNCSEL 2 0 is select UART...

Page 455: ...checked as 1 4 EPE Even Parity Enable Bit 0 Odd number of logic 1 s is transmitted and checked in each word 1 Even number of logic 1 s is transmitted and checked in each word Note This bit has effect only when PBE UART_LINE 3 is set 3 PBE Parity Bit Enable Bit 0 Parity bit generated Disabled 1 Parity bit generated Enabled Note Parity bit is generated on each outgoing character and is checked on ea...

Page 456: ...put 0 nRTS pin output is high level active 1 nRTS pin output is low level active Default Note1 Refer to Figure 6 11 13 and Figure 6 11 14 for UART function mode Note2 Refer to Figure 6 11 24 and Figure 6 11 25 for RS 485 function mode Note3 Before setting this bit TXRXDIS UART_FUNCSEL 3 should be set then waited for TXRXACT UART_FIFOSTS 31 is cleared When the configuration is done cleared TXRXDIS ...

Page 457: ...Before setting this bit TXRXDIS UART_FUNCSEL 3 should be set then waited for TXRXACT UART_FIFOSTS 31 is cleared When the configuration is done cleared TXRXDIS UART_FUNCSEL 3 to activate UART controller 7 5 Reserved Reserved 4 CTSSTS nCTS Pin Status Read Only This bit mirror from nCTS pin input of voltage logic status 0 nCTS pin input is low level voltage logic state 1 nCTS pin input is high level ...

Page 458: ...red The UART controller can not transmit or receive data at this moment Otherwise this bit is set 30 Reserved Reserved 29 RXIDLE RX Idle Status Read Only This bit is set by hardware when RX is idle 0 RX is busy 1 RX is idle Default 28 TXEMPTYF Transmitter Empty Flag Read Only This bit is set by hardware when TX FIFO UART_DAT is empty and the STOP bit of the last byte has been transmitted 0 TX FIFO...

Page 459: ... Note This bit is set when the number of usage in RX FIFO Buffer is equal to 16 otherwise it is cleared by hardware 14 RXEMPTY Receiver FIFO Empty Read Only This bit initiate RX FIFO empty or not 0 RX FIFO is not empty 1 RX FIFO is empty Note When the last byte of RX FIFO has been read by CPU hardware sets this bit high It will be cleared when UART receives any new data 13 8 RXPTR RX FIFO Pointer ...

Page 460: ...on mode Note2 This bit can be cleared by writing 1 to it 2 ABRDTOIF Auto baud Rate Detect Time out Interrupt Flag This bit is set to logic 1 in Auto baud Rate Detect mode when the baud rate counter is overflow 0 Auto baud rate counter is underflow 1 Auto baud rate counter is overflow Note This bit can be cleared by writing 1 to it 1 ABRDIF Auto baud Rate Detect Interrupt Flag This bit is set to lo...

Page 461: ...or Read Only This bit is set if TXENDIEN UART_INTEN 22 and TXENDIF UART_INTSTS 22 are both set to 1 0 No Transmitter Empty interrupt is generated 1 Transmitter Empty interrupt is generated 29 HWBUFEINT PDMA Mode Buffer Error Interrupt Indicator Read Only This bit is set if BUFERRIEN UART_INTEN 5 and HWBUFEIF UART_INTSTS 21 are both set to 1 0 No buffer error interrupt is generated in PDMA mode 1 B...

Page 462: ... TXOVIF UART_FIFOSTS 24 and RXOVIF UART_FIFOSTS 0 are cleared 20 HWTOIF PDMA Mode RX Time out Interrupt Flag Read Only This bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time out counter equal to TOIC UART_TOUT 7 0 If RXTOIEN UART_INTEN 4 is enabled the RX time out interrupt will be generated 0 No RX time out interrupt flag is generated in PDMA mode 1 R...

Page 463: ... UART wake up interrupt is generated 1 UART wake up interrupt is generated 13 BUFERRINT Buffer Error Interrupt Indicator Read Only This bit is set if BUFERRIEN UART_INTEN 5 and BUFERRIF UART_ INTSTS 5 are both set to 1 0 No buffer error interrupt is generated 1 Buffer error interrupt is generated 12 RXTOINT RX Time out Interrupt Indicator Read Only This bit is set if RXTOIEN UART_INTEN 4 and RXTOI...

Page 464: ...errupt flag 5 BUFERRIF Buffer Error Interrupt Flag Read Only This bit is set when the TX FIFO or RX FIFO overflows TXOVIF UART_FIFOSTS 24 or RXOVIF UART_FIFOSTS 0 is set When BUFERRIF UART_INTSTS 5 is set the transfer is not correct If BUFERRIEN UART_INTEN 5 is enabled the buffer error interrupt will be generated 0 No buffer error interrupt flag is generated 1 Buffer error interrupt flag is genera...

Page 465: ...DRDETF UART_FIFOSTS 3 are cleared 1 THREIF Transmit Holding Register Empty Interrupt Flag This bit is set when the last data of TX FIFO is transferred to Transmitter Shift Register If THREIEN UART_INTEN 1 is enabled the THRE interrupt will be generated 0 No THRE interrupt flag is generated 1 THRE interrupt flag is generated Note This bit is read only and it will be cleared when writing data into U...

Page 466: ...or The time out counter resets and starts counting the counting clock baud rate whenever the RX FIFO receives a new data word if time out counter is enabled by setting TOCNTEN UART_INTEN 11 Once the content of time out counter is equal to that of time out interrupt comparator TOIC UART_TOUT 7 0 a receiver time out interrupt RXTOINT UART_INTSTS 12 is generated if RXTOIEN UART_INTEN 4 enabled A new ...

Page 467: ...UART_BAUD 28 to select baud rate calculation mode The detail description is shown in Table 6 11 4 Note In IrDA mode must be operated in mode 0 28 BAUDM0 BAUD Rate Mode Selection Bit 0 This bit is baud rate mode selection bit 0 UART provides three baud rate calculation modes This bit combines with BAUDM1 UART_BAUD 29 to select baud rate calculation mode The detail description is shown in Table 6 11...

Page 468: ...set then waited for TXRXACT UART_FIFOSTS 31 is cleared When the configuration is done cleared TXRXDIS UART_FUNCSEL 3 to activate UART controller Note2 This bit is valid when FUNCSEL UART_FUNCSEL 2 0 is select IrDA function 5 TXINV IrDA Inverse Transmitting Output Signal 0 None inverse transmitting signal Default 1 Inverse transmitting output signal Note1 Before setting this bit TXRXDIS UART_FUNCSE...

Page 469: ...shall be 0x02 10 4 bit time from Start bit to the 1st rising edge The input pattern shall be 0x08 11 8 bit time from Start bit to the 1st rising edge The input pattern shall be 0x80 Note The calculation of bit number includes the START bit 18 ABRDEN Auto baud Rate Detect Enable Bit 0 Auto baud rate detect function Disabled 1 Auto baud rate detect function Enabled Note This bit is cleared automatic...

Page 470: ...D Enabled Note It cannot be active with RS 485_NMM operation mode 8 RS485NMM RS 485 Normal Multi drop Operation Mode NMM 0 RS 485 Normal Multi drop Operation mode NMM Disabled 1 RS 485 Normal Multi drop Operation mode NMM Enabled Note It cannot be active with RS 485_AAD operation mode 7 LINTXEN LIN TX Break Mode Enable Bit 0 LIN TX Break mode Disabled 1 LIN TX Break mode Enabled Note When TX break...

Page 471: ...glitch Enabled Note When this bit is set to logic 1 any pulse width less than about 300 ns will be considered a glitch and will be removed in the serial data input RX This bit acts only on RX line and has no effect on the transmitter logic 5 4 Reserved Reserved 3 TXRXDIS TX and RX Disable Bit Setting this bit can disable TX and RX 0 TX and RX Enabled 1 TX and RX Disabled Note The TX and RX will no...

Page 472: ...st Note2 This field can be used for LIN master mode or slave mode 23 22 HSEL LIN Header Select 00 The LIN header includes break field 01 The LIN header includes break field and sync field 10 The LIN header includes break field sync field and frame ID field 11 Reserved Note This bit is used to master mode for LIN to send header field SENDH UART_LINCTL 8 1 or used to slave to indicates exit from mut...

Page 473: ...ed frame ID parity checked Note2 This bit is only used when the operation header transmitter is in HSEL UART_LINCTL 23 22 10 8 SENDH LIN TX Send Header Enable Bit The LIN TX header can be break field or break and sync field or break sync and frame ID field it is depend on setting HSEL UART_LINCTL 23 22 0 Send LIN TX header Disabled 1 Send LIN TX header Enabled Note1 This bit is shadow bit of LINTX...

Page 474: ...f this field are explained in 6 11 5 10 Slave mode with automatic resynchronization 2 SLVAREN LIN Slave Automatic Resynchronization Mode Enable Bit 0 LIN automatic resynchronization Disabled 1 LIN automatic resynchronization Enabled Note1 This bit only is valid in LIN slave mode SLVEN UART_LINCTL 0 1 Note2 When operation in Automatic Resynchronization mode the baud rate setting must be mode2 BAUDM...

Page 475: ...d by writing 1 to it Note2 This bit is only valid when enable bit error detection function BITERREN UART_LINCTL 12 1 8 BRKDETF LIN Break Detection Flag This bit is set by hardware when a break is detected and be cleared by writing 1 to it through software 0 LIN break not detected 1 LIN break detected Note1 This bit can be cleared by writing 1 to it Note2 This bit is only valid when LIN break detec...

Page 476: ... SLVEN UART_LINCTL 0 1 and enable LIN frame ID parity check function IDPEN UART_LINCTL 9 1 SLVHEF LIN Slave Header Error Flag This bit is set by hardware when a LIN header error is detected in LIN slave mode and be cleared by writing 1 to it The header errors include break delimiter is too short less than 0 5 bit time frame error in sync field or Identifier field sync field data is not 0x55 in Non...

Page 477: ... 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved BRCOMP 7 6 5 4 3 2 1 0 BRCOMP Bits Description 31 BRCOMPDEC Baud Rate Compensation Decrease 0 Positive increase one module clock compensation for each compensated bit 1 Negative decrease one module clock compensation for each compensated bit 30 9 Reserved Reserved 8 0 BRCOMP Baud Rate Compensation Patten These 9 bits are used to define the relative...

Page 478: ...s set to 1 3 WKRS485EN RS 485 Address Match AAD Mode Wake up Enable Bit 0 RS 485 Address Match AAD mode wake up system function Disabled 1 RS 485 Address Match AAD mode wake up system function Enabled Note1 When the system is in Power down mode RS 485 Address Match will wake up system from Power down mode Note2 This bit is used for RS 485 Auto Address Detection AAD mode in RS 485 function mode and...

Page 479: ...1 M0A23 Series May 06 2022 Page 479 of 746 Rev 1 02 M0A21 M0A23 SERIES TECHNICAL REFERENCE MANUAL Note When the system is in Power down mode an external nCTS change will wake up system from Power down mode ...

Page 480: ...FO reached threshold time out wake up cause this bit is set to 1 Note2 This bit can be cleared by writing 1 to it 3 RS485WKF RS 485 Address Match AAD Mode Wake up Flag This bit is set if chip wake up from power down state by RS 485 Address Match AAD mode 0 Chip stays in power down state 1 Chip wake up from power down state by RS 485 Address Match AAD mode wake up Note1 If WKRS485EN UART_WKCTL 3 is...

Page 481: ...e up Note1 If WKDATEN UART_WKCTL 1 is enabled the Incoming Data wake up cause this bit is set to 1 Note2 This bit can be cleared by writing 1 to it 0 CTSWKF nCTS Wake up Flag This bit is set if chip wake up from power down state by nCTS wake up 0 Chip stays in power down state 1 Chip wake up from power down state by nCTS wake up Note1 If WKCTSEN UART_WKCTL 0 is enabled the nCTS wake up cause this ...

Page 482: ... Wake up Compensation Register 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 STCOMP 7 6 5 4 3 2 1 0 STCOMP Bits Description 31 16 Reserved Reserved 15 0 STCOMP Start Bit Compensation Value These bits field indicate how many clock cycle selected by UART_CLK do the UART controller can get the 1st bit start bit when the device is wake up from Powe...

Page 483: ... 21 20 19 18 17 16 LINRTOIC 15 14 13 12 11 10 9 8 LINRTOIC 7 6 5 4 3 2 1 0 LINRTOIC Bits Description 31 24 Reserved Reserved 23 0 LINRTOIC LIN Response Time out Comparator The time out counter resets and starts counting the counting clock UART_CLK whenever LIN master sends a header or LIN slave detects a header Once the content of time out counter is equal to or bigger than that of time out compar...

Page 484: ...abled the LIN wake up event will cause this bit set to 1 Note2 This bit can be cleared by writing 1 to it 28 LINWKEN LIN Wake up Enable Bit 0 LIN wake up system function Disabled 1 LIN wake up system function Enabled Note1 When the system is in Power down mode LIN wake up event will wake up system from Power down mode 27 25 Reserved Reserved 24 SENDLINW LIN Send Wake up Enable Bit 0 Send LIN Wake ...

Page 485: ...t Signal USCIx_CLK USCIx_CTL0 1 Wake up Control Protocol Relative Clock Generator fPCLK Output Configuration Note x 0 1 Figure 6 12 1 USCI Block Diagram 6 12 4 Functional Description The structure of the Universal Serial Control Interface USCI controller is shown in Figure 6 12 1 The input signal is implemented in input processor The data buffers and the data shift unit support the data transfers ...

Page 486: ...SS USCIx_CTL1 Data Input USCIx_DAT0 RX SPI_MOSI_0 SDA USCIx_DAT1 SPI_MISO_0 Table 6 12 1 Input Signals for Different Protocols The description of protocol specific items are given in the related protocol chapters General Input Structure The input structures of data and control signals include inverter digital filter and edge detection data signal only Data Shift Unit Digital Filter USCIx_DAT 1 0 U...

Page 487: ... 0 USCI_CLKIN 0 is set to 0 the paths of input signals do not contain any delay due to synchronization or filtering If there is noise on the input signals there is the possibility to synchronize the input signal signal IN_SYNC is synchronized to fPCLK The synchronized input signal is taken into account by SYNCSEL 1 The synchronization leads to a delay in the signal path of 2 3 times the period of ...

Page 488: ...ansmitter includes transmit shift register TX_SFTR and a transmit data buffer TX_BUF The TXFULL TXEMPTY USCI_BUFSTS 9 8 and TXENDIF USCI_PROTSTS 2 can indicate the status of transmitter A receiver includes receive shift register RX_SFTR and a double receive buffer structure RX_BUF0 RX_BUF1 In double buffer structure user need not care about the reception sequence and two received data can be hold ...

Page 489: ...ft Control Status Control TX_SFTR Data Serial Bus Clock Input Control Input Shift Data Output TX_BUF 16 Transmit Buffer Status USCI_LINECTL USCI_BUFSTS USCI_TXDAT Figure 6 12 6 Transmit Data Path Transmit Data Validation The status of TXEMPTY USCI_BUFSTS 8 indicates the transmission data is valid or not in the transmit buffer TX_BUF and the TXSTIF USCI_PROTSTS 1 labels the start conditions for eac...

Page 490: ...e cleared automatically when transmit buffer TX_BUF is updated with new data While a transmission is in progress TX_BUF can be loaded with new data User has to update the TX_BUF before a new transmission Receive Data Path The receive data path is based on 16 bit wide receive shift register RX_SFTR and receive buffers RX_BUF0 and RX_BUF1 The data transfer parameters like data word length or the shi...

Page 491: ...rotocol Processor Unit Note Refer to the Basic Clock Divider Counter section to get the fSAMP_CLK Figure 6 12 8 Protocol Relative Clock Generator The protocol related counter contains basic clock divider counter and timing measurement counter It is based on a divider stages providing the frequencies needed for the different protocols It contains The basic clock divider counter provides the protoco...

Page 492: ...gnals with fPROT_CLK or fDIV_CLK It stops counting when it reaches the user specified value Divider by 2 0 1 fREF_CLK PTCTLSEL USCI_BRGEN 1 Up Counter fPROT_CLK Protocol Relation Definition Clear 0 1 fDIV_CLK FUNMODE USCI_CTL 2 0 TMCNTSRC USCI_BRGEN 5 TMCNTEN USCI_BRGEN 4 Figure 6 12 10 Block of Timing Measurement Counter The timing measurement counter is used to perform time out function or auto ...

Page 493: ...nsmit start interrupt Transmit end interrupt event to indicate that a data word transmission has been done A transmit end interrupt event occurs when the current transmit data in shift register had been finished It is indicated by flag TXENDIF USCI_PROTSTS 2 and if enabled leads to transmit end interrupt This event also indicates when the shift control settings word length shift direction etc are ...

Page 494: ... and Interrupt Handling 6 12 4 7 Protocol specific Events and Interrupts These events are related to protocol specific actions that are described in the corresponding protocol chapters The related indication flags are located in register USCI_PROTSTS All events can be individually enabled for the generation of the common protocol interrupt Table 6 12 4 Protocol specific Events and Interrupt Handli...

Page 495: ... PDMAEN USCI_PDMACTL 3 is set to 1 the PDMA function is enabled When TXPDMAEN USCI_PDMACTL 1 is set to 1 the controller will issue request to PDMA controller to start the PDMA transmission process automatically When RXPDMAEN USCI_PDMACTL 2 is set to 1 the controller will start the PDMA reception process USCI will issue request to PDMA controller automatically when there is data in the receive FIFO...

Page 496: ...the system 6 13 2 Features Supports one transmit buffer and two receive buffer for data payload Supports hardware auto flow control function Supports programmable baud rate generator Support 9 bit Data Transfer Support 9 bit RS 485 Baud rate detection by built in capture event of baud rate generator Supports PDMA capability Supports Wake up function Data and nCTS Wakeup Only 6 13 3 Block Diagram P...

Page 497: ... MFP4 PA 0 PA 1 PA 2 PA 3 PA 4 PA 5 PB 4 PB 5 PB 6 PB 7 PC 0 PC 1 PC 2 PC 3 PC 4 PC 5 PC 6 PC 7 MFP11 USCI0_DAT1 PD 6 MFP4 PA 0 PA 1 PA 2 PA 4 PA 5 PB 4 PB 5 PB 6 PB 7 PC 0 PC 1 PC 2 PC 3 PC 4 PC 5 PC 6 PC 7 MFP12 The basic configurations of USCI1_UART are as follows Clock Source Configuration Enable USCI1 peripheral clock in USCI1CKEN CLK_APBCLK1 9 Reset USCI1 controller in USCI1RST SYS_IPRST2 9 ...

Page 498: ...unication an independent communication line is needed for each transfer direction Figure 6 13 2 shows an example with a point to point full duplex connection between two communication partners UART module A and UART module B RX_BUF TX_BUF Transfer Control Baud Rate Generator UART Module A fPCLK USCIx_DAT0 USCIx_DAT1 RX_BUF TX_BUF Transfer Control Baud Rate Generator UART Module B fPCLK USCIx_DAT0 ...

Page 499: ...it One or two stop bits with the signal level 1 IDLE SOF 1 0 1 Bit 6 13 Bit DATA P STOP IDLE 1 2 Bit 0 1 Bit Figure 6 13 3 UART Standard Frame Format The protocol specific bits SOF P STOP are automatically handled by the UART protocol state machine and do not appear in the data flow via the receive and transmit buffers Start Bit The receiver input signal USCIx_DAT0 is checked for a falling edge An...

Page 500: ...UART Mode The UART protocol can be selected by setting FUNMODOE UUART_CTL 2 0 to 010B and the UART protocol can be enabled by setting PROTEN UUART_PROTCTL 31 to 1 Note that the FUNMODE must be set 0 before protocol changing and it is recommended to configure all parameters of the UART before UART protocol is enabled Pin Connections The USCIx_DAT0 pin is used for UART receive data input signal RX i...

Page 501: ...CLKSEL PDSCNT and DSCNT define the baud rate setting RCLKSEL UUART_BRGEN 0 to define the input frequency fREF_CLK SPCLKSEL UUART_BRGEN 3 2 to define the multiple source of the sample clock fSAM_CLK PDSCNT UUART_BRGEN 9 8 to define the length of a data sample time division of fREF_CLK by 1 2 3 or 4 DSCNT UUART_BRGEN 14 10 to define the number of data sample time per bit time The standard setting is...

Page 502: ...TV UUART_PROTCTL 25 16 after the auto baud rate function done the time of 4th falling edge of input signal If the user want to receive the next successive frame correctly it is better to set the value of CLKDIV UUART_BRGEN 25 16 and DSCNT UUART_BRGEN 14 10 as the same value the value shall be among the rang of 0xF and 0x5 because the DSCNT is used to define the sample counter of each bit and the P...

Page 503: ...OTCTL 1 be set when the STICKEN UUART_PROTCTL 26 is set For example if the STICKEN is set to 1 and data sequence are 0x8015 0x8033 0x0055 0x0033 and 0x80AA the transmitted parity of data 0x15 0x33 0x55 0x33 and 0xAA will be 1 1 0 0 and 1 The UART controller can also play as an RS 485 addressable slave the protocol related error of PARITYERR UUART_PROTSTS 5 can be acted as the address bit detection...

Page 504: ...nt Figure 6 13 7 nCTS Wake Up Case 1 Case 2 nCTS transition from high to low Power down mode CLK USCIx_CTL0 nCTS stable count CPU run WKF Note 1 Stable count means HCLK source recovery stable count Figure 6 13 8 nCTS Wake Up Case 2 Interrupt Events The UART provided interrupt for protocol event and data transfer event The description show below Protocol Interrupt Events The following protocol rela...

Page 505: ...upt Handling The data transfer interrupts indicate events related to UART frame handling Transmit Start Interrupt Bit TXSTIF UUART_PROTSTS 1 is set after the start bit of a data word In buffer mode this is the earliest point in time when a new data word can be written to UUART_TXDAT Transmitter Finished This interrupt indicates that the transmitter has completely finished all data in the buffer Bi...

Page 506: ...OTEN UUART_PROTCTL 31 to 1 to enable UART protocol 5 Transmit and receive data Write transmit data register UUART_TXDAT to transmit data Wait until TXSTIF UUART_PROTSTS 1 is set and then user can write the next data in UUART_TXDAT When TXENDIF UUART_PROTSTS 2 is set the transmit buffer is empty and the stop bit of the last data has been transmitted If RXENDIF UUART_PROTSTS 4 is set the receiver ha...

Page 507: ...8 R W USCI Input Clock Signal Configuration Register 0x0000_0000 UUART_LINECTL UUARTn_BA 0x2C R W USCI Line Control Register 0x0000_0000 UUART_TXDAT UUARTn_BA 0x30 W USCI Transmit Data Register 0x0000_0000 UUART_RXDAT UUARTn_BA 0x34 R USCI Receive Data Register 0x0000_0000 UUART_BUFCTL UUARTn_BA 0x38 R W USCI Transmit Receive Buffer Control Register 0x0000_0000 UUART_BUFSTS UUARTn_BA 0x3C R USCI T...

Page 508: ...ts Description 31 3 Reserved Reserved 2 0 FUNMODE Function Mode This bit field selects the protocol for this USCI controller Selecting a protocol that is not available or a reserved combination disables the USCI When switching between two protocols the USCI has to be disabled before selecting a new protocol Simultaneously the USCI will be reset when user write 000 to FUNMODE 000 The USCI is disabl...

Page 509: ...pt generation in case of a receive finish event 0 The receive end interrupt Disabled 1 The receive end interrupt Enabled 3 RXSTIEN Receive Start Interrupt Enable BIt This bit enables the interrupt generation in case of a receive start event 0 The receive start interrupt Disabled 1 The receive start interrupt Enabled 2 TXENDIEN Transmit End Interrupt Enable Bit This bit enables the interrupt genera...

Page 510: ...it 6 The user can use revised CLKDIV and new BRDETITV UUART_PROTCTL 24 16 to calculate the precise baud rate 15 Reserved Reserved 14 10 DSCNT Denominator for Sample Counter This bit field defines the divide ratio of the sample clock fSAMP_CLK The divided frequency fDS_CNT fPDS_CNT DSCNT 1 Note The maximum value of DSCNT is 0xF on UART mode and suggest to set over 4 to confirm the receiver data is ...

Page 511: ...AMP_CLK fSCLK 11 fSAMP_CLK fREF_CLK 1 PTCLKSEL Protocol Clock Source Selection This bit selects the source signal of protocol clock fPROT_CLK 0 Reference clock fREF_CLK 1 fREF_CLK2 its frequency is half of fREF_CLK 0 RCLKSEL Reference Clock Source Selection This bit selects the source signal of reference clock fREF_CLK 0 Peripheral device clock fPCLK 1 Reserved ...

Page 512: ...g edge activates the trigger event of input data signal 10 A falling edge activates the trigger event of input data signal 11 Both edges activate the trigger event of input data signal Note In UART function mode it is suggested to set this bit field as 10 2 ININV Input Signal Inverse Selection This bit defines the inverter enable of the input asynchronous signal 0 The un synchronized input signal ...

Page 513: ...s Description 31 3 Reserved Reserved 2 ININV Input Signal Inverse Selection This bit defines the inverter enable of the input asynchronous signal 0 The un synchronized input signal will not be inverted 1 The un synchronized input signal will be inverted 1 Reserved Reserved 0 SYNCSEL Input Synchronization Signal Selection This bit selects if the un synchronized input signal with optionally inverted...

Page 514: ...7 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 Reserved SYNCSEL Bits Description 31 1 Reserved Reserved 0 SYNCSEL Input Synchronization Signal Selection This bit selects if the un synchronized input signal or the synchronized and optionally filtered signal can be used as input for the data shift unit 0 The un synchronized signal can be taken as ...

Page 515: ... Reserved 0x4 The data word contains 4 bits located at bit positions 3 0 0x5 The data word contains 5 bits located at bit positions 4 0 0xF The data word contains 15 bits located at bit positions 14 0 Note In UART protocol the length can be configured as 6 13 bits 7 CTLOINV Control Signal Output Inverse Selection This bit defines the relation between the internal control signal and the output cont...

Page 516: ...M0A21 M0A23 Series May 06 2022 Page 516 of 746 Rev 1 02 M0A21 M0A23 SERIES TECHNICAL REFERENCE MANUAL is transmitted received first 1 The LSB the bit 0 of data buffer will be transmitted received first ...

Page 517: ... R W Description Reset Value UUART_TXDAT UUARTn_BA 0x30 W USCI Transmit Data Register 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 TXDAT 7 6 5 4 3 2 1 0 TXDAT Bits Description 31 16 Reserved Reserved 15 0 TXDAT Transmit Data Software can use this bit field to write 16 bit transmit data for transmission ...

Page 518: ..._BA 0x34 R USCI Receive Data Register 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 RXDAT 7 6 5 4 3 2 1 0 RXDAT Bits Description 31 16 Reserved Reserved 15 0 RXDAT Received Data This bit field monitors the received data which stored in receive data buffer Note RXDAT 15 13 indicate the same frame status of BREAK FRMERR and PARITYERR UUART_PROTST...

Page 519: ...ore this bit will be set to 1 16 TXRST Transmit Reset 0 No effect 1 Reset the transmit related counters state machine and the content of transmit shift register and data buffer Note It is cleared automatically after one PCLK cycle 15 RXCLR Clear Receive Buffer 0 No effect 1 The receive buffer is cleared filling level is cleared and output pointer is set to input pointer value Should only be used w...

Page 520: ...r is not full 1 Transmit buffer is full 8 TXEMPTY Transmit Buffer Empty Indicator 0 Transmit buffer is not empty 1 Transmit buffer is empty 7 4 Reserved Reserved 3 RXOVIF Receive Buffer Over run Error Interrupt Status This bit indicates that a receive buffer overrun error event has been detected If RXOVIEN UUART_BUFCTL 14 is enabled the corresponding interrupt request is activated It is cleared by...

Page 521: ...13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 Reserved PDMAEN RXPDMAEN TXPDMAEN PDMARST Bits Description 31 4 Reserved Reserved 3 PDMAEN PDMA Mode Enable Bit 0 PDMA function Disabled 1 PDMA function Enabled 2 RXPDMAEN PDMA Receive Channel Available 0 Receive PDMA function Disabled 1 Receive PDMA function Enabled 1 TXPDMAEN PDMA Transmit Channel Available 0 Transmit PDMA function Disabled 1 Transmit PDM...

Page 522: ...5 4 3 2 1 0 Reserved PDBOPT Reserved WKEN Bits Description 31 3 Reserved Reserved 2 PDBOPT Power Down Blocking Option 0 If user attempts to enter Power down mode by executing WFI while the protocol is in transferring MCU will stop the transfer and enter Power down mode immediately 1 If user attempts to enter Power down mode by executing WFI while the protocol is in transferring the on going transf...

Page 523: ...on Reset Value UUART_WKSTS UUARTn_BA 0x58 R W USCI Wake up Status Register 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 Reserved WKF Bits Description 31 1 Reserved Reserved 0 WKF Wake up Flag When chip is woken up from Power down mode this bit is set to 1 Software can write 1 to clear this bit ...

Page 524: ...rial data input RX This bit acts only on RX line and has no effect on the transmitter logic 29 BCEN Transmit Break Control Enable Bit 0 Transmit Break Control Disabled 1 Transmit Break Control Enabled Note When this bit is set to logic 1 the serial data output TX is forced to the Spacing State logic 0 This bit acts only on TX line and has no effect on the transmitter logic 27 Reserved Reserved 26 ...

Page 525: ... direction control Enabled Note 1 This bit is used for nRTS auto direction control for RS485 Note 2 This bit has effect only when the RTSAUTOEN is not set 4 CTSAUTOEN nCTS Auto flow Control Enable Bit When nCTS auto flow is enabled the UART will send data to external device when nCTS input assert UART will not send data to device if nCTS input is dis asserted 0 nCTS auto flow control Disabled 1 nC...

Page 526: ...erved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 Reserved RLSIEN ABRIEN Reserved Bits Description 31 3 Reserved Reserved 2 RLSIEN Receive Line Status Interrupt Enable Bit 0 Receive line status interrupt Disabled 1 Receive line status interrupt Enabled Note UUART_PROTSTS 7 5 indicates the current interrupt event for receive line status interrupt 1 ABRIEN Auto ba...

Page 527: ... to indicate the current status of the internal synchronized nCTS signal 0 The internal synchronized nCTS is low 1 The internal synchronized nCTS is high 15 12 Reserved Reserved 11 ABERRSTS Auto baud Rate Error Status This bit is set when auto baud rate detection counter overrun When the auto baud rate counter overrun the user shall revise the CLKDIV UUART_BRGEN 25 16 value and enable ABREN UUART_...

Page 528: ...ated Note This bit can be cleared by writing 1 among the BREAK FRMERR and PARITYERR bits 5 PARITYERR Parity Error Flag This bit is set to logic 1 whenever the received character does not have a valid parity bit 0 No parity error is generated 1 Parity error is generated Note This bit can be cleared by writing 1 among the BREAK FRMERR and PARITYERR bits 4 RXENDIF Receive End Interrupt Flag 0 A recei...

Page 529: ...application block diagrams in Master and Slave mode are shown below SPI Slave Device Master Transmit Data Master Receive Data Serial Bus Clock Slave Select SPI_MOSI USCIx_DAT0 SPI_MISO USCIx_DAT1 SPI_CLK USCIx_CLK SPI_SS USCIx_CTL SPI_MOSI SPI_MISO USCI SPI Master USCI SPI Master SPI_CLK SPI_SS Note x 0 1 Figure 6 14 1 SPI Master Mode Application Block Diagram SPI Master Device Slave Receive Data ...

Page 530: ...Processor Unit Input Processor Buffer Control Interrupt Generation USCIx_DAT0 1 To Interrupt Signal USCIx_CLK USCIx_CTL0 Wake up Control Protocol Relative Clock Generator fPCLK Output Configuration Note x 0 1 Figure 6 14 3 USCI SPI Mode Block Diagram 6 14 4 Basic Configuration USCI0 SPI Basic Configurations Clock Source Configuration Enable USCI0 peripheral clock in USCI0CKEN CLK_APBCLK1 8 Enable ...

Page 531: ... PD 1 MFP4 USCI1_DAT1 PA 0 PA 5 PB 4 PB 7 PC 0 PC 7 MFP17 PD 2 MFP4 6 14 5 Functional Description USCI Common Function Description Please refer to section 6 12 4 for detailed information Signal Description A device operating in Master mode controls the start and end of a data transfer as well as the generation of the SPI bus clock and slave select signal The slave select signal indicates the start...

Page 532: ...SCIx_CLK SPI_MISO USCIx_DAT1 TX Data Word 0 TX Data Word N Note x 0 1 Figure 6 14 54 Wire Full Duplex SPI Communication Signals Slave Mode Serial Bus Clock Configuration The USCI controller needs the peripheral clock to drive the USCI logic unit to perform the data transfer The peripheral clock frequency is equal to PCLK frequency In Master mode the frequency of the SPI bus clock is determined by ...

Page 533: ...should have the same SCLKMODE configuration The four kinds of serial bus clock configuration are shown below SCLKMODE 1 0 SPI Clock Idle State Transmit Timing Receive Timing 0x0 Low Falling edge Rising edge 0x1 Low Rising edge Falling edge 0x2 High Rising edge Falling edge 0x3 High Falling edge Rising edge Table 6 14 1 Serial Bus Clock Configuration Figure 6 14 6 SPI Communication with Different S...

Page 534: ...PI_CLK USCIx_CLK SPI_MISO USCIx_DAT1 MSB TX n TX n 1 RX n 1 MSB RX n MSB TX n TX n 1 LSB TX 0 LSB RX 0 RX n 1 MSB RX n LSB TX 0 LSB RX 0 Note x 0 1 USCI_PROTCTL 0 0 USCI_PROTCTL 7 6 0x1 USCI_CTLIN0 2 1 USCI_LINECTL 0 0 USCI_LINECTL 7 1 Data N Data N 1 Data Frame SPI_SS USCIx_CTL0 SPI_MOSI USCIx_DAT0 SPI_CLK USCIx_CLK SPI_MISO USCIx_DAT1 MSB TX n TX n 1 LSB TX 0 LSB RX 0 RX n 1 MSB RX n MSB TX n TX...

Page 535: ... The duration between the slave select active edge and the first SPI clock input edge shall over 2 USCI peripheral clock cycles The input slave select signal of SPI Slave has to be keep inactive for at least 2 USCI peripheral clock cycles between two consecutive frames in order to correctly detect the end of a frame Transmit and Receive Data The bit length of a transmit receive data word in SPI pr...

Page 536: ...is SCLKMODE 1 0 0x0 LSB 0 DWIDTH 3 0 0x0 Note x 0 1 Figure 6 14 11 Word Suspend Interval between Two Transaction Words Automatic Slave Select Function AUTOSS USPI_PROTCTL 3 is used for SPI Master mode to enable the automatic slave select function If the bit AUTOSS USPI_PROTCTL 3 is set the slave select signal will be generated automatically and the setting value of SS USPI_PROTCTL 2 will not affec...

Page 537: ...CIx_CTL0 TXEMPTY USCI_BUFSTS 8 CTLOINV USCI_LINECTL 7 SPI_CLK USCIx_CLK SS USCI_PROTCTL 2 Note Automatic slave select is enabled One word transaction One word transaction Figure 6 14 13 Auto Slave Select SUSPITV 0x3 Slave 3 wire Mode When the SLV3WIRE USPI_PROTCTL 1 is set by software to enable the Slave 3 wire mode the USCI SPI communication can work with no slave select signal in Slave mode The ...

Page 538: ... duplex SPI transfer In one data channel half duplex SPI transfer there is only one data pin for data transfer Thus the data transmission and data reception are at different time interval The data shift direction is determined by PORTDIR USPI_TXDAT 16 Refer to the register description for more detail information The function of one data channel half duplex SPI transfer is similar to the full duple...

Page 539: ...rupt The interrupt event RXENDIF USPI_PROTSTS 4 is set after the start of the last data bit of a receive data word It can be cleared only by writing 1 to it Protocol Related Interrupts SPI slave select interrupt In SPI Slave mode there are slave select active and in active interrupt flags SSACTIF USPI_PROTSTS 9 and SSINAIF USPI_PROTSTS 8 will be set to 1 when SLAVE USPI_PROTCTL 0 is set to 1 and S...

Page 540: ...UFSTS 11 will be set as 1 It can be cleared by write 1 into it Timing Diagram The slave select signal of USCI SPI protocol is active high by default and it can be inverted by CTLOINV USPI_LINECTL 7 setting The idle state of serial bus clock and the serial bus clock edge used for transmit receive data can be configured by setting SCLKMODE USPI_PROTCTL 7 6 The bit length of a transaction word data i...

Page 541: ... RX 6 SCLKMODE 0x3 Master Mode FUNMODE 0x1 SLAVE 0 LSB 1 DWIDTH 0x8 CTLOINV 0 CTLOINV 1 Figure 6 14 17 SPI Timing in Master Mode Alternate Phase of Serial Bus Clock SPI_CLK SPI_MOSI SPI_MISO TX0 6 TX0 0 TX1 7 TX1 6 LSB TX1 0 RX0 6 RX0 0 RX1 6 LSB RX1 0 MSB RX0 7 RX1 7 MSB TX0 7 SPI_SS SCLKMODE 0x0 SCLKMODE 0x2 Slave Mode FUNMODE 0x1 SLAVE 1 SLV3WIRE 0 LSB 0 DWIDTH 0x8 CTLIN0 ININV 0 CTLIN0 ININV 1...

Page 542: ...ser s application configure the settings as follows CTLOINV USPI_LINECTL 7 If the slave selection signal is active low set this bit to 1 otherwise set it to 0 DWIDTH USPI_LINECTL 11 8 Data width setting LSB USPI_LINECTL 0 LSB first or MSB first TSMSEL USPI_PROTCTL 14 12 Full duplex SPI transfer or one channel half duplex SPI transfer SCLKMODE USPI_PROTCTL 7 6 Determine the clock timing AUTOSS USPI...

Page 543: ...ion is determined by PORTDIR USPI_TXDAT 16 setting 7 User can get the received data by reading USPI_RXDAT register as long as RXEMPTY USPI_BUFSTS 0 is 0 The next datum for transmission can be written to USPI_TXDAT register as long as TXFULL USPI_BUFSTS 9 is 0 Wake up Function The USCI Controller in SPI mode supports wake up system function The wake up source in SPI protocol is the transition of in...

Page 544: ...ransmit Receive Buffer Status Register 0x0000_0101 USPI_PDMACTL USPIn_BA 0x40 R W USCI PDMA Control Register 0x0000_0000 USPI_WKCTL USPIn_BA 0x54 R W USCI Wake up Control Register 0x0000_0000 USPI_WKSTS USPIn_BA 0x58 R W USCI Wake up Status Register 0x0000_0000 USPI_PROTCTL USPIn_BA 0x5C R W USCI Protocol Control Register 0x0000_0300 USPI_PROTIEN USPIn_BA 0x60 R W USCI Protocol Interrupt Enable Re...

Page 545: ...s Description 31 3 Reserved Reserved 2 0 FUNMODE Function Mode This bit field selects the protocol for this USCI controller Selecting a protocol that is not available or a reserved combination disables the USCI When switching between two protocols the USCI has to be disabled before selecting a new protocol Simultaneously the USCI will be reset when user write 000 to FUNMODE 000 The USCI is disable...

Page 546: ...on in case of a receive start event 0 The receive start interrupt Disabled 1 The receive start interrupt Enabled Note For SPI master mode the receive start event happens when SPI master sends slave select active and spi clock to the external SPI slave For SPI slave mode the receive start event happens when slave select of SPI slave is active and spi clock of SPI slave is inputed from the external ...

Page 547: ...DIV 1 15 6 Reserved Reserved 5 TMCNTSRC Time Measurement Counter Clock Source Selection 0 Time measurement counter with fPROT_CLK 1 Time measurement counter with fDIV_CLK 4 TMCNTEN Time Measurement Counter Enable Bit This bit enables the 10 bit timing measurement counter 0 Time measurement counter Disabled 1 Time measurement counter Enabled 3 2 SPCLKSEL Sample Clock Source Selection This bit field...

Page 548: ...defines the inverter enable of the input asynchronous signal 0 The un synchronized input signal will not be inverted 1 The un synchronized input signal will be inverted Note In SPI protocol it is suggested this bit should be set as 0 1 Reserved Reserved 0 SYNCSEL Input Signal Synchronization Selection This bit selects if the un synchronized input signal with optionally inverted or the synchronized...

Page 549: ... Signal Inverse Selection This bit defines the inverter enable of the input asynchronous signal 0 The un synchronized input signal will not be inverted 1 The un synchronized input signal will be inverted 1 Reserved Reserved 0 SYNCSEL Input Synchronization Signal Selection This bit selects if the un synchronized input signal with optionally inverted or the synchronized and optionally filtered signa...

Page 550: ...ed 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 Reserved SYNCSEL Bits Description 31 1 Reserved Reserved 0 SYNCSEL Input Synchronization Signal Selection This bit selects if the un synchronized input signal or the synchronized and optionally filtered signal which is synchronized with PCLK can be used as input for the data shift unit 0 The un synchronized signal can be taken as input for the data...

Page 551: ...e data word contains 4 bits located at bit positions 3 0 0x5 The data word contains 5 bits located at bit positions 4 0 0xF The data word contains 15 bits located at bit positions 14 0 7 CTLOINV Control Signal Output Inverse Selection This bit defines the relation between the internal control signal and the output control signal 0 No effect 1 The control signal will be inverted before its output N...

Page 552: ...M0A21 M0A23 Series May 06 2022 Page 552 of 746 Rev 1 02 M0A21 M0A23 SERIES TECHNICAL REFERENCE MANUAL 1 The LSB the bit 0 of data buffer will be transmitted received first ...

Page 553: ...Port Direction Control This bit field is only available while USCI operates in SPI protocol FUNMODE 0x1 with half duplex transfer It is used to define the direction of the data port pin When software writes USPI_TXDAT register the transmit data and its port direction are settled simultaneously 0 The data pin is configured as output mode 1 The data pin is configured as input mode 15 0 TXDAT Transmi...

Page 554: ...t R W Description Reset Value USPI_RXDAT USPIn_BA 0x34 R USCI Receive Data Register 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 RXDAT 7 6 5 4 3 2 1 0 RXDAT Bits Description 31 16 Reserved Reserved 15 0 RXDAT Received Data This bit field monitors the received data which stored in receive data buffer ...

Page 555: ...Reset the transmit related counters state machine and the content of transmit shift register and data buffer Note 1 It is cleared automatically after one PCLK cycle Note 2 Write 1 to this bit will set the output data pin to zero if USPI_PROTCTL 28 0 15 RXCLR Clear Receive Buffer 0 No effect 1 The receive buffer is cleared Should only be used while the buffer is not taking part in data traffic Note...

Page 556: ...M0A21 M0A23 Series May 06 2022 Page 556 of 746 Rev 1 02 M0A21 M0A23 SERIES TECHNICAL REFERENCE MANUAL 5 0 Reserved Reserved ...

Page 557: ...tes 1 to this bit 0 A transmit buffer under run event has not been detected 1 A transmit buffer under run event has been detected 10 Reserved Reserved 9 TXFULL Transmit Buffer Full Indicator 0 Transmit buffer is not full 1 Transmit buffer is full 8 TXEMPTY Transmit Buffer Empty Indicator 0 Transmit buffer is not empty 1 Transmit buffer is empty and available for the next transmission datum 7 4 Res...

Page 558: ...M0A21 M0A23 Series May 06 2022 Page 558 of 746 Rev 1 02 M0A21 M0A23 SERIES TECHNICAL REFERENCE MANUAL 1 Receive buffer is empty ...

Page 559: ... 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 Reserved PDMAEN RXPDMAEN TXPDMAEN PDMARST Bits Description 31 4 Reserved Reserved 3 PDMAEN PDMA Mode Enable Bit 0 PDMA function Disabled 1 PDMA function Enabled 2 RXPDMAEN PDMA Receive Channel Available 0 Receive PDMA function Disabled 1 Receive PDMA function Enabled 1 TXPDMAEN PDMA Transmit Channel Available 0 Transmit PDMA function Disabled 1 Transmit PDMA ...

Page 560: ...4 3 2 1 0 Reserved PDBOPT Reserved WKEN Bits Description 31 3 Reserved Reserved 2 PDBOPT Power Down Blocking Option 0 If user attempts to enter Power down mode by executing WFI while the protocol is in transferring MCU will stop the transfer and enter Power down mode immediately 1 If user attempts to enter Power down mode by executing WFI while the protocol is in transferring the on going transfer...

Page 561: ...on Reset Value USPI_WKSTS USPIn_BA 0x58 R W USCI Wake up Status Register 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 Reserved WKF Bits Description 31 1 Reserved Reserved 0 WKF Wake up Flag When chip is woken up from Power down mode this bit is set to 1 Software can write 1 to clear this bit ...

Page 562: ...LVTOCNT Slave Mode Time out Period In Slave mode this bit field is used for Slave time out period This bit field indicates how many clock periods selected by TMCNTSRC USPI_BRGEN 5 between the two edges of input SCLK will assert the Slave time out event Writing 0x0 into this bit field will disable the Slave time out function Example Assume SLVTOCNT is 0x0A and TMCNTSRC USPI_BRGEN 5 is 1 it means th...

Page 563: ... MODE3 The idle state of SPI clock is high level Data is transmitted with falling edge and received with rising edge 5 4 Reserved Reserved 3 AUTOSS Automatic Slave Select Function Enable 0 Slave select signal will be controlled by the setting value of SS USPI_PROTCTL 2 bit 1 Slave select signal will be generated automatically The slave select signal will be asserted by the SPI controller when tran...

Page 564: ...of DWIDTH USPI_LINECTL 11 8 Bit count error event occurs 0 The Slave mode bit count error interrupt Disabled 1 The Slave mode bit count error interrupt Enabled 2 SLVTOIEN Slave Time out Interrupt Enable Bit In SPI protocol this bit enables the interrupt generation in case of a Slave time out event 0 The Slave time out interrupt Disabled 1 The Slave time out interrupt Enabled 1 SSACTIEN Slave Selec...

Page 565: ... run event occurs 17 BUSY Busy Status Read Only 0 SPI is in idle state 1 SPI is in busy state The following listing are the bus busy conditions a USPI_PROTCTL 31 1 and the TXEMPTY 0 b For SPI Master mode the TXEMPTY 1 but the current transaction is not finished yet c For SPI Slave mode the USPI_PROTCTL 31 1 and there is serial clock input into the SPI core logic when slave select is active d For S...

Page 566: ...End Interrupt Flag 0 Receive end event did not occur 1 Receive end event occurred Note It is cleared by software write 1 to this bit The receive end event happens when hardware receives the last bit of RX data into shift data unit 3 RXSTIF Receive Start Interrupt Flag 0 Receive start event did not occur 1 Receive start event occurred Note It is cleared by software write 1 to this bit For SPI maste...

Page 567: ...ure 6 15 1 I2 C Bus Timing The device s on chip I2 C provides the serial interface that meets the I2 C bus standard mode specification The I2 C port handles byte transfers autonomously The I2 C mode is selected by FUNMODE UI2C_CTL 2 0 100B When enabling this port the USCI interfaces to the I2 C bus via two pins SDA and SCL When I O pins are used as I2 C ports user must set the pins function to I2 ...

Page 568: ...ic Configurations The basic configurations of USCI0_I2C are as follows Clock Source Configuration Enable USCI0 peripheral clock in USCI0CKEN CLK_APBCLK1 8 Enable USCI0_I2C function UI2C_CTL 2 0 register UI2C_CTL 2 0 3 b100 Reset Configuration Reset USCI0 controller in USCI0RST SYS_IPRST2 8 Pin Configuration Group Pin Name GPIO MFP USCI0 USCI0_CLK PA 5 PA 4 PC 5 PC 4 PC 3 PC 6 PC 7 PB 7 PB 6 PB 5 P...

Page 569: ...P signal generation SDA SCL 1 7 8 9 S 1 7 8 9 1 7 8 9 P ADDRESS W R ACK DATA ACK DATA ACK Figure 6 15 3 I2 C Protocol When the bus is free idle meaning no master device is engaging the bus both SCL and SDA lines are high a master can initiate a transfer by sending a START signal A START signal usually referred to as the S bit is defined as a HIGH to LOW transition on the SDA line while SCL is HIGH...

Page 570: ...Rn n 0 1 In 7 bit address mode the first 7 bits of a received first address byte are compared to the programmed slave address UI2C_DEVADDRn 6 0 If these bits match the slave sends an acknowledge For 10 bit addressing mode if the slave address is programmed to 1111 0XXB the XX bits are compared to the bits UI2C_DEVADDR 9 8 to check for address match and also sends an acknowledge when ADDR10EN UI2C_...

Page 571: ...ta baud rate of I2 C is determined by UI2C_BRGEN register when I2 C is in Master Mode and it is not necessary in a Slave mode In the Slave mode I2 C will automatically synchronize it with any clock frequency from master I2 C device The bits RCLKSEL SPCLKSEL PDSCNT and DSCNT define the baud rate setting RCLKSEL UI2C_BRGEN 0 to define the input frequency fREF_CLK SPCLKSEL UI2C_BRGEN 3 2 to define th...

Page 572: ... may transmit data simultaneously The I2 C supports multi master by including collision detection and arbitration to prevent data corruption If two masters sometimes initiate I2 C command at the same time the arbitration procedure determines which master wins and can continue with the command Arbitration is performed on the SDA signal while the SCL signal is high Each master checks if the SDA sign...

Page 573: ... it passes through the input stage and the input filter before it is sampled This complete loop has to be finished including all settling times to obtain stable signal levels before the SCL signal changes again The delays in this path have to be taken into account for the calculation of the baud rate as a function of fPCLK and fPROT_CLK We suggest user adopt fPCLK Non Acknowledge and Error Conditi...

Page 574: ...de the I2 C port hardware looks for its own slave address and the general call address If one of these addresses is detected and if the slave is willing to receive or transmit data from to master by setting the AA UI2C_PROTCTL 1 bit acknowledge pulse will be transmitted out on the 9th clock hence an interrupt is requested on both master and slave devices if interrupt is enabled When the microcontr...

Page 575: ...legde Figure 6 15 9 Master Transmits Data to Slave with a 7 bit Address Figure 6 15 10 shows a master read data from slave A master addresses a slave with a 7 bit address and 1 bit read index to denote that the master wants to read data from the slave The slave will start transmitting data after the slave returns acknowledge to the master 1 read S SLAVE ADDRESS R W A DATA A DATA A A P data transfe...

Page 576: ...ss read write bit data and Repeat START STOP to perform I2 C protocol TXDAT SLA W Master to Slave Slave to Master TXDAT Data P P STARIF 1 PTRG STA STO AA 0 1 0 x Clear protocol status register ACKIF 1 NACKIF 1 ACKIF 1 NACKIF 1 TXDAT Data PTRG STA STO AA 1 0 0 x Writing 1 to ACKIF Writing 1 to NACKIF STARIF 1 PTRG STA STO AA 1 1 0 x Writing 1 to ACKIF Writing 1 to NACKIF STORIF 1 PTRG STA STO AA 1 ...

Page 577: ...r Slave to Master Arbitration Lost Arbitration Lost RXDAT Data PTRG STA STO AA 1 0 0 0 Writing 1 to ACKIF ARBLOIF 1 TXDAT SLA R TXDAT SLA R PTRG STA STO AA 1 0 0 X ARBLOIF 1 PTRG STA STO AA 1 0 0 X Writing 1 to ARBLOIF I2 C bus will be release Not addressed SLV mode will be enterd PTRG STA STO AA 1 1 0 X Writing 1 to ARBLOIF A START will be transmitted when the bus becomes free Enter not addressed...

Page 578: ...TO AA 1 0 0 x Write 1 to STARIF TXDAT Data ARBLOIF 1 TXDAT Data PTRG STA STO AA 1 0 0 x Writing 1 to ACKIF Writing 1 to NACKIF Arbitration Lost PTRG STA STO AA 1 0 0 X Writing 1 to ARBLOIF I2 C bus will be release Not addressed SLV mode will be enterd PTRG STA STO AA 1 1 0 X Writing 1 to ARBLOIF A START will be transmitted when the bus becomes free Enter not addressed SLV mode Send a START when bu...

Page 579: ...TRG STA STO AA 1 0 0 x Write 1 to STARIF ACK ACKIF 1 ACK ACKIF 1 TXDAT SLA PTRG STA STO AA 1 0 0 x Write 1 to ACKIF Figure 6 15 16 Master Recevier Mode Control Flow with 10 bit Address If the I2 C is in Master mode and gets arbitration lost the bit of ARBLOIF UI2C_PROTSTS 11 will be set User may writing 1 to ARBLOIF UI2C_PROTSTS 11 and set PTRG STA STO AA 1 1 0 X to send START to re start Master o...

Page 580: ...iting 1 to ARBLOIF ACKIF 1 NACKIF 1 NAK ARBLOIF 1 ACKIF 1 RXDAT Data PTRG STA STO AA 1 0 0 1 Writing 1 to ACKIF RXDAT Data PTRG STA STO AA 1 0 0 0 Writing 1 to ACKIF ACKIF 1 NACKIF 1 Arbitration Lost Master to Slave Slave to Master STORIF 1 ARBLOIF 1 Sr Sr Sr PTRG STA STO AA 1 0 0 1 Writing 1 to ACKIF Writing 1 to NACKIF Writing 1 to STORIF Switch to not addressed mode Own SLA will be recognized B...

Page 581: ...IF Writing 1 to ARBLOIF TXDAT Data PTRG STA STO AA 1 0 0 X Writing 1 to ACKIF Writing 1 to ARBLOIF Sr PTRG STA STO AA 1 0 0 X Writing 1 to ACKIF PTRG STA STO AA 1 0 0 X Writing 1 to ACKIF ACK NAK P ACK NAK ACK RXDAT SLA RXDAT SLA R S ACK ACK NAK P S Switch to not addressed mode Own SLA will not be recognized Send START when bus free Become I2 C Master PTRG STA STO AA 1 1 0 0 Writing 1 to ACKIF Wri...

Page 582: ...ter Become I2 C Master Bus Free Bus Free PTRG STA STO AA 1 0 0 1 Writing 1 to ACKIF Write 1 to STORIF Switch to not addressed mode Own SLA will be recognized Become I2 C Slave Become I2 C Slave RXDAT SLA W 0x00 ARBLOIF 1 Arbitraion Lost Arbitraion Lost Master to Slave Master to Slave Slave to Master Slave to Master STORIF 1 Sr Sr Sr PTRG STA STO AA 1 0 0 X Writing 1 to ACKIF Writing 1 to ARBLOIF P...

Page 583: ...these interrupts the processor may read the data register to see what was actually transmitted on the bus Loss of Arbitration in Monitor Mode In monitor mode the I2 C module will not be able to respond to a request for information by the bus master or issue an ACK Some other slave on the bus will respond instead Software should be aware of the fact that the module is in monitor mode and should not...

Page 584: ...ow duty 60 PCLK When HTCTL UI2C_TMCTL 24 16 is set to 63 and STCTL UI2C_TMCTL 8 0 is set to 0 then SDA output delay will over SCL high duty and cause bus error The hold time setting limitation HTlimit UI2C_BRGEN 25 16 1 9 Note Hold time adjust function can only work in master mode when slave mode the USCI I2 C HTCTL UI2C_TMCTL 24 16 should set as 0 SCL SDA SDA delay over SCL low duty Bus error Fig...

Page 585: ...h one of the device address register UI2C_DEVADDRn the user shall check the WKAKDONE UI2C_PROTSTS 16 bit is set to 1 to confirm the address wakeup frame has done The WKAKDONE bit indicates that the ACK bit cycle of address match frame is done in power down Remind user must clear WKF after clearing the WKAKDONE bit to 0 The WRSTSWK UI2C_PROTSTS 17 bit records the Read Write command on the address m...

Page 586: ...0 x Clear protocol status register ACKIF 1 TXDAT SLA W PTRG STA STO AA 1 0 0 x Write 1 to STARIF ACKIF 1 TXDAT ROM Address High Byte PTRG STA STO AA 1 0 0 x Writing 1 to ACKIF STARIF 1 PTRG STA STO AA 1 1 0 x Clear protocol status register STORIF 1 PTRG STA STO AA 1 0 1 x Writing 1 to NACKIF TXDAT SLA R PTRG STA STO AA 1 0 0 x Write 1 to STARIF ACKIF 1 NAK NACKIF 1 TXDAT ROM Address Low Byte ACK A...

Page 587: ...R0 UI2Cn_BA 0x44 R W USCI Device Address Register 0 0x0000_0000 UI2C_DEVADDR1 UI2Cn_BA 0x48 R W USCI Device Address Register 1 0x0000_0000 UI2C_ADDRMSK0 UI2Cn_BA 0x4C R W USCI Device Address Mask Register 0 0x0000_0000 UI2C_ADDRMSK1 UI2Cn_BA 0x50 R W USCI Device Address Mask Register 1 0x0000_0000 UI2C_WKCTL UI2Cn_BA 0x54 R W USCI Wake up Control Register 0x0000_0000 UI2C_WKSTS UI2Cn_BA 0x58 R W U...

Page 588: ...s Description 31 3 Reserved Reserved 2 0 FUNMODE Function Mode This bit field selects the protocol for this USCI controller Selecting a protocol that is not available or a reserved combination disables the USCI When switching between two protocols the USCI has to be disabled before selecting a new protocol Simultaneously the USCI will be reset when user write 000 to FUNMODE 000 The USCI is disable...

Page 589: ...e Counter This bit field defines the divide ratio of the sample clock fSAMP_CLK The divided frequency fDS_CNT fPDS_CNT DSCNT 1 9 8 PDSCNT Pre divider for Sample Counter This bit field defines the divide ratio of the clock division from sample clock fSAMP_CLK The divided frequency fPDS_CNT fSAMP_CLK PDSCNT 1 7 6 Reserved Reserved 5 TMCNTSRC Time Measurement Counter Clock Source Selection 0 Time mea...

Page 590: ...CE MANUAL This bit selects the source signal of protocol clock fPROT_CLK 0 Reference clock fREF_CLK 1 fREF_CLK2 its frequency is half of fREF_CLK 0 RCLKSEL Reference Clock Source Selection This bit selects the source signal of reference clock fREF_CLK 0 Peripheral device clock fPCLK 1 Reserved ...

Page 591: ...ta word length amount of bits for reception and transmission The data word is always right aligned in the data buffer USCI support word length from 4 to 16 bits 0x0 The data word contains 16 bits located at bit positions 15 0 0x1 Reserved 0x2 Reserved 0x3 Reserved 0x4 The data word contains 4 bits located at bit positions 3 0 0x5 The data word contains 5 bits located at bit positions 4 0 0xF The d...

Page 592: ...t R W Description Reset Value UI2C_TXDAT UI2Cn_BA 0x30 W USCI Transmit Data Register 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 TXDAT 7 6 5 4 3 2 1 0 TXDAT Bits Description 31 16 Reserved Reserved 15 0 TXDAT Transmit Data Software can use this bit field to write 16 bit transmit data for transmission ...

Page 593: ...x34 R USCI Receive Data Register 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 RXDAT 7 6 5 4 3 2 1 0 RXDAT Bits Description 31 16 Reserved Reserved 15 0 RXDAT Received Data This bit field monitors the received data which stored in receive data buffer Note In I2 C protocol RXDAT 12 8 indicate the different transmission conditions which defined i...

Page 594: ... 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved DEVADDR 7 6 5 4 3 2 1 0 DEVADDR Bits Description 31 10 Reserved Reserved 9 0 DEVADDR Device Address In I2 C protocol this bit field contains the programmed slave address If the first received address byte are 1111 0AAXB the AA bits are compared to the bits DEVADDR 9 8 to check for address match where the X is R W bit Then the second address b...

Page 595: ...erved 15 14 13 12 11 10 9 8 Reserved ADDRMSK 7 6 5 4 3 2 1 0 ADDRMSK Bits Description 31 10 Reserved Reserved 9 0 ADDRMSK USCI Device Address Mask 0 Mask Disabled the received corresponding register bit should be exact the same as address register 1 Mask Enabled the received corresponding address bit is don t care USCI support multiple address recognition with two address mask register When the bi...

Page 596: ...e up Control Register 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 Reserved WKADDREN WKEN Bits Description 31 2 Reserved Reserved 1 WKADDREN Wake up Address Match Enable Bit 0 The chip is woken up according data toggle 1 The chip is woken up according address match 0 WKEN Wake up Enable Bit 0 Wake up function Disabled ...

Page 597: ...on Reset Value UI2C_WKSTS UI2Cn_BA 0x58 R W USCI Wake up Status Register 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 Reserved WKF Bits Description 31 1 Reserved Reserved 0 WKF Wake up Flag When chip is woken up from Power down mode this bit is set to 1 Software can write 1 to clear this bit ...

Page 598: ...hen TOCNT bigger than 0 Note The TMCNTSRC UI2C_BRGEN 5 must be set zero on I2 C mode 15 10 Reserved Reserved 9 MONEN Monitor Mode Enable Bit This bit enables monitor mode In monitor mode the SDA output will be put in high impedance mode This prevents the I2 C module from outputting data of any kind including ACK onto the I2 C data bus 0 The monitor mode Disabled 1 The monitor mode Enabled Note Dep...

Page 599: ...re sends a START or repeat START condition to bus when the bus is free 2 STO I2 C STOP Control In Master mode setting STO to transmit a STOP condition to bus then I2 C hardware will check the bus condition if a STOP condition is detected this bit will be cleared by hardware automatically In a slave mode setting STO resets I2 C hardware to the defined not addressed slave mode when bus error UI2C_PR...

Page 600: ... condition is detected indicated by ERRIF UI2C_PROTSTS 12 0 The error interrupt Disabled 1 The error interrupt Enabled 4 ARBLOIEN Arbitration Lost Interrupt Enable Bit This bit enables the generation of a protocol interrupt if an arbitration lost event is detected 0 The arbitration lost interrupt Disabled 1 The arbitration lost interrupt Enabled 3 NACKIEN Non Acknowledge Interrupt Enable Bit This ...

Page 601: ... Rev 1 02 M0A21 M0A23 SERIES TECHNICAL REFERENCE MANUAL 0 TOIEN Time out Interrupt Enable Bit In I2 C protocol this bit enables the interrupt generation in case of a time out event 0 The time out interrupt Disabled 1 The time out interrupt Enabled ...

Page 602: ...TART condition is present 18 BUSHANG Bus Hang up This bit indicates bus hang up status There is 4 bit counter count when SCL hold high and refer fSAMP_CLK The hang up counter will count to overflow and set this bit when SDA is low The counter will be reset by falling edge of SCL signal 0 The bus is normal status for transmission 1 The bus is hang up status for transmission Note This bit has no int...

Page 603: ...This bit indicates that an arbitration has been lost A protocol interrupt can be generated if UI2C_PROTIEN ARBLOIEN 1 0 An arbitration has not been lost 1 An arbitration has been lost Note It is cleared by software writing 1 into this bit 10 NACKIF Non Acknowledge Received Interrupt Flag This bit indicates that a non acknowledge has been received in master mode A protocol interrupt can be generate...

Page 604: ... is cleared by hardware when a STOP condition is detected 0 The bus is IDLE both SCLK and SDA High 1 The bus is busy 5 TOIF Time out Interrupt Flag 0 A time out interrupt status has not occurred 1 A time out interrupt status has occurred Note It is cleared by software writing 1 into this bit 4 0 Reserved Reserved ...

Page 605: ... 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 Reserved ADMAT1 ADMAT0 Bits Description 31 2 Reserved Reserved 1 ADMAT1 USCI Address 1 Match Status Register When address 1 is matched hardware will inform which address used This bit will set to 1 and software can write 1 to clear this bit 0 ADMAT0 USCI Address 0 Match Status Register When address 0 is matched hardwa...

Page 606: ... 1 0 STCTL Bits Description 31 25 Reserved Reserved 24 16 HTCTL Hold Time Configure Control This field is used to adjust SDA transfer timing which master will transfer SDA after SCL fallinng edge The delay hold time is numbers of peripheral clock HTCTL x fPCLK Note Hold time adjust function can only work in master mode when slave mode this field should set as 0 15 9 Reserved Reserved 8 0 STCTL Set...

Page 607: ...t of the C_CAN can be accessed directly by the software through the module interface These registers are used to control configure the CAN Core and the Message Handler and to access the Message RAM 6 16 2 Features Supports CAN protocol version 2 0 part A and B Bit rates up to 1 MBit s 32 Message Objects Each Message Object has its own identifier mask Programmable FIFO mode concatenation of Message...

Page 608: ...rupt C_CAN Figure 6 16 1 CAN Peripheral Block Diagram 6 16 4 Basic Configuration CAN Basic Configuration Clock source Configuration Enable CAN clock CAN0CKEN CLK_APBCLK0 24 Reset Configuration Reset CAN controller CAN0RST SYS_IPRST1 24 Pin Configuration Group Pin Name GPIO MFP CAN0 CAN0_RXD GPA0 GPA1 GPA2 GPA3 GPA4 GPA5 MFP20 GPB4 GPB5 GPB6 GPB7 MFP20 GPC0 GPC1 GPC2 GPC3 GPC4 GPC5 GPC6 GPC7 MFP20 ...

Page 609: ...are has to start by resetting the corresponding MsgVal bit When the configuration is completed MsgVal bit is set again CAN Message Transfer Once the C_CAN is initialized and Init bit CAN_CON 0 is reset to zero the C_CAN Core synchronizes itself to the CAN bus and starts the message transfer Received messages are stored in their appropriate Message Objects if they pass the Message Handler s accepta...

Page 610: ...Mode Test Mode is entered by setting the Test bit CAN_CON 7 In Test Mode bits Tx1 CAN_TEST 6 Tx0 CAN_TEST 5 LBack CAN_TEST 4 Silent CAN_TEST 3 and Basic CAN_TEST 2 are writeable Bit Rx CAN_TEST 7 monitors the state of the CAN_RX pin and therefore is only readable All Test Register functions are disabled when the Test bit is cleared Silent Mode The CAN Core can be set in Silent Mode by programming ...

Page 611: ...ected from the CAN Core and the CAN_TX pin is held recessive Figure 6 16 4 shows the connection of signals CAN_TX and CAN_RX to the CAN Core in case of the combination of Loop Back Mode with Silent Mode C_CAN 1 CAN_TX CAN_RX CAN_Core Tx Rx Figure 6 16 4 CAN Core in Loop Back Mode Combined with Silent Mode Basic Mode The CAN Core can be set in Basic Mode by programming the Basic bit CAN_TEST 2 to o...

Page 612: ...en CAN message transfer or any of the test modes Loop Back Mode Silent Mode or Basic Mode are selected 6 16 7 CAN Communications Managing Message Objects The configuration of the Message Objects in the Message RAM with the exception of the bits MsgVal NewDat IntPnd and TxRqst will not be affected by resetting the chip All the Message Objects must be initialized by the application software or they ...

Page 613: ...ts bytes of one Message Object It is always necessary to write a complete Message Object into the Message RAM Therefore the data transfer from the IFn Registers to the Message RAM requires a read modify write cycle First those parts of the Message Object that are not to be changed are read from the Message RAM and then the complete contents of the Message Buffer Registers are written into the Mess...

Page 614: ..._MCON 7 of Message Object 1 are then loaded into the Acceptance Filtering unit and compared with the arbitration field from the shift register This is repeated with each following Message Object until a matching Message Object is found or until the end of the Message RAM is reached If a match occurs the scan is stopped and the Message Handler FSM proceeds depending on the type of frame Data Frame ...

Page 615: ... Frame is used it is programmed to ID28 ID18 The ID17 ID0 can then be disregarded If the TxIE bit CAN_IFn_MCON 11 is set the IntPnd bit CAN_IFn_MCON 13 will be set after a successful transmission of the Message Object If the RmtEn bit CAN_IFn_MCON 9 is set a matching received Remote Frame will cause the TxRqst bit CAN_IFn_MCON 8 to be set the Remote Frame will autonomously be answered by a Data Fr...

Page 616: ...s The Mask Registers Msk28 0 UMask MXtd and MDir bits may be used UMask CAN_IFn_MCON 12 1 to allow groups of Data Frames with similar identifiers to be accepted The Dir bit CAN_IFn_ARB2 13 should not be masked in typical applications Handling Received Messages The application software may read a received message any time through the IFn Interface registers The data consistency is guaranteed by the...

Page 617: ... of this Message Object is set By setting NewDat while EoB CAN_IFn_MCON 7 is zero the Message Object is locked for further write access by the Message Handler until the application software has written the NewDat bit back to zero Messages are stored into a FIFO Buffer until the last Message Object of this FIFO Buffer is reached If none of the preceding Message Objects is released by writing NewDat...

Page 618: ...ir chronological order An interrupt remains pending until the application software has cleared it The Status Interrupt has the highest priority Among the message interrupts interrupt priority of the Message Object decreases with increasing message number A message interrupt is cleared by clearing the IntPnd bit CAN_IFn_MCON 13 of the Message Object The Status Interrupt is cleared by reading the St...

Page 619: ...re CAN nodes simultaneously try to transmit a frame a misplaced sample point may cause one of the transmitters to become error passive The analysis of such sporadic errors requires a detailed knowledge of the CAN bit synchronization inside a CAN node and interaction of the CAN nodes on the CAN bus Bit Time and Bit Rate CAN supports bit rates in the range of lower than 1 Kbit s up to 1000 Kbit s Ea...

Page 620: ...he oscillator s tolerance range have to be considered Propagation Time Segment This part of the bit time is used to compensate physical delay time within the network These delay time consist of the signal propagation time on the bus and the internal delay time of the CAN nodes Any CAN node synchronized to the bit stream on the CAN bus will be out of phase with the transmitter of that bit stream ca...

Page 621: ...ilter using three samples and a majority logic to determine the valid bit value This results in an additional input delay of 1 tq requiring a longer Prop_Seg Phase Buffer Segments and Synchronization The Phase Buffer Segments Phase_Seg1 and Phase_Seg2 and the Synchronization Jump Width SJW are used to compensate for the oscillator tolerance The Phase Buffer Segments may be lengthened or shortened ...

Page 622: ...er The same happens at the acknowledge field where the transmitter and some of the receivers will have to synchronize to that receiver that takes the lead in the transmission of the dominant acknowledge bit Synchronizations after the end of the arbitration will be caused by oscillator tolerance when the differences in the oscillator s clock periods of transmitter and receivers sum up during the ti...

Page 623: ...ed by synchronisations In both examples the spike starts at the end of Prop_Seg and has the length of Prop_Seg Phase_Seg1 In the first example the Synchronization Jump Width is greater than or equal to the phase error of the spike s edge from recessive to dominant Therefore the Sample Point is shifted after the end of the spike a recessive bus level is sampled In the second example SJW is shorter ...

Page 624: ...eg1 as TSEG1 CAN_BTIME 11 8 is combined with Phase_Seg2 as TSEG2 CAN_BTIME 14 12 in one byte SJW CAN_BTIME 7 6 and BRP CAN_BTIME 5 0 are combined in the other byte In these bit timing registers the four components TSEG1 TSEG2 SJW and BRP have to be programmed to a numerical value that is one less than its functional value Therefore instead of values in the range of 1 n values in the range of 0 n 1...

Page 625: ...ned by the Baud Rate Prescaler with tq Baud Rate Prescaler fapb_clk Several combinations may lead to the desired bit time allowing iterations of the following steps First part of the bit time to be defined is the Prop_Seg Its length depends on the delay time measured in the APB clock A maximum bus length as well as a maximum node delay has to be defined for expandible CAN bus systems The resulting...

Page 626: ... the phase buffer segment 1 2 The subscript of 2 1 3 indicates the number of bits in the corresponding bit of Bit Timing Register CAN Interface Reset State After the hardware reset the C_CAN registers hold the reset values which are given in the register description in 0 Additionally the bus off state is reset and the output CAN_TX is set to recessive HIGH The value 0x0001 Init 1 in the CAN Contro...

Page 627: ...s tProp tSJW tTSeg2 4us Information Processing Time 3 tq tSync Seg 1us 1 tq bit time 10us tSync Seg tTSeg1 tTSeg2 tolerance for APB_CLK 1 58 2 13 2 2 1 PB time bit PB PB Min 4 10 13 2 4 us us us In this example the concatenated bit time parameters are 4 1 3 5 1 4 4 1 2 2 1 6 and the Bit Timing Register is programmed to 0x34C1 ...

Page 628: ... W IFn Command Mask Registers 0x0000_0000 CAN_IFn_MASK1 n 1 2 CAN_BA 0x28 0x60 n 1 R W IFn Mask 1 Registers 0x0000_FFFF CAN_IFn_MASK2 n 1 2 CAN_BA 0x2C 0x60 n 1 R W IFn Mask 2 Registers 0x0000_FFFF CAN_IFn_ARB1 n 1 2 CAN_BA 0x30 0x60 n 1 R W IFn Arbitration 1 Registers 0x0000_0000 CAN_IFn_ARB2 n 1 2 CAN_BA 0x34 0x60 n 1 R W IFn Arbitration 2 Registers 0x0000_0000 CAN_IFn_MCON n 1 2 CAN_BA 0x38 0x6...

Page 629: ..._MVLD1 CAN_BA 0x160 R Message Valid Register 1 0x0000_0000 CAN_MVLD2 CAN_BA 0x164 R Message Valid Register 2 0x0000_0000 CAN_WU_EN CAN_BA 0x168 R W Wake up Enable Control Register 0x0000_0000 CAN_WU_STATUS CAN_BA 0x16C R W Wake up Status Register 0x0000_0000 Note 1 0x00 0br0000000 where r signifies the actual value of the CAN_RX 2 IFn The two sets of Message Interface Registers IF1 and IF2 have id...

Page 630: ...d BOff EWarn EPass RxOk TxOk LEC 08h CAN_ERR RP REC6 0 TEC7 0 0Ch CAN_BTIME Res TSeg2 TSeg1 SJW BRP 10h CAN_IIDR IntId15 8 IntId7 0 14h CAN_TEST Reserved Rx Tx1 Tx0 LBack Silent Basic Reserved 18h CAN_BRPE Reserved BRPE 20h CAN_IF1_CRE Q Busy Reserved Message Number 24h CAN_IF1_CMA SK Reserved WR RD Mask Arb Control ClrIntPnd TxRqst Data A Data B 28h CAN_IF1_MAS K1 Msk15 0 2Ch CAN_IF1_MAS K2 MXtd ...

Page 631: ... 0 40h CAN_IF1_DAT_ A2 Data 3 Data 2 44h CAN_IF1_DAT_ B1 Data 5 Data 4 48h CAN_IF1_DAT_ B2 Data 7 Data 6 80h CAN_IF2_CREQ Busy Reserved Message Number 84h CAN_IF2_CMAS K Reserved WR RD Mask Arb Control ClrIntPnd TxRqst Data A Data B 88h CAN_IF2_MASK 1 Msk15 0 8Ch CAN_IF2_MASK 2 MXtd MDir Res Msk28 16 90h CAN_IF2_ARB1 ID15 0 94h CAN_IF2_ARB2 MsgVal Xtd Dir ID28 16 98h CAN_IF2_MCO N NewDat MsgLst In...

Page 632: ...TxRqst16 1 104h CAN_TXREQ2 TxRqst32 17 120h CAN_NDAT1 NewDat16 1 124h CAN_NDAT2 NewDat32 17 140h CAN_IPND1 IntPnd16 1 144h CAN_IPND2 IntPnd32 17 160h CAN_MVLD1 MsgVal16 1 164h CAN_MVLD2 MsgVal32 17 168h CAN_WU_EN Reserved WAKUP _EN 16Ch CAN_WU_STAT US Reserved WAKUP _STS 170h CAN_RAM_CEN Reserved RAM_ CEN Others Reserved Reserved Table 6 16 4 CAN Register Map for Each Bit Function Note Reserved bi...

Page 633: ...E SIE IE Init Bits Description 31 8 Reserved Reserved 7 Test Test Mode Enable Bit 0 Normal Operation 1 Test Mode 6 CCE Configuration Change Enable Bit 0 No write access to the Bit Timing Register 1 Write access to the Bit Timing Register CAN_BTIME allowed while Init bit CAN_CON 0 1 5 DAR Automatic Re transmission Disable Bit 0 Automatic Retransmission of disturbed messages Enabled 1 Automatic Retr...

Page 634: ...cord stopping all bus activities Once Init has been cleared by the CPU the device will then wait for 129 occurrences of Bus Idle 129 11 consecutive recessive bits before resuming normal operations At the end of the bus off recovery sequence the Error Management Counters will be reset During the waiting time after resetting Init each time a sequence of 11 recessive bits has been monitored a Bit0Err...

Page 635: ... in the CAN Specification 4 RxOK Received a Message Successfully 0 No message has been successfully received since this bit was last reset by the CPU This bit is never reset by the CAN Core 1 A message has been successfully received since this bit was last reset by the CPU independent of the result of acceptance filtering 3 TxOK Transmitted a Message Successfully 0 Since this bit was reset by the ...

Page 636: ...ecovery this status is set each time a sequence of 11 recessive bits has been monitored This enables the CPU to monitor the proceedings of the bus off recovery sequence indicating the bus is not stuck at dominant or continuously disturbed 6 CRCError The CRC check sum was incorrect in the message received the CRC received for an incoming message does not match with the calculated CRC for the receiv...

Page 637: ...8 17 16 Reserved 15 14 13 12 11 10 9 8 RP REC 7 6 5 4 3 2 1 0 TEC Bits Description 31 16 Reserved Reserved 15 RP Receive Error Passive 0 The Receive Error Counter is below the error passive level 1 The Receive Error Counter has reached the error passive level as defined in the CAN Specification 14 8 REC Receive Error Counter Actual state of the Receive Error Counter Values between 0 and 127 7 0 TE...

Page 638: ...id values for TSeg1 are 1 15 The actual interpretation by the hardware of this value is such that one more than the value programmed is used 7 6 SJW Re Synchronization Jump Width 0x0 0x3 Valid programmed values are 0 3 The actual interpretation by the hardware of this value is such that one more than the value programmed here is used 5 0 BRP Baud Rate Prescaler 0x01 0x3F The value by which the osc...

Page 639: ...rder An interrupt remains pending until the application software has cleared it If IntId is different from 0x0000 and IE CAN_CON 1 is set the IRQ interrupt signal to the EIC is active The interrupt remains active until IntId is back to value 0x0000 the cause of the interrupt is reset or until IE is reset The Status Interrupt has the highest priority Among the message interrupts the Message Object ...

Page 640: ...RX 1 6 5 Tx Tx 1 0 Control of CAN_TX Pin 00 Reset value CAN_TX pin is controlled by the CAN Core 01 Sample Point can be monitored at CAN_TX pin 10 CAN_TX pin drives a dominant 0 value 11 CAN_TX pin drives a recessive 1 value 4 LBack Loop Back Mode Enable Bit 0 Loop Back Mode Disabled 1 Loop Back Mode Enabled 3 Silent Silent Mode 0 Normal operation 1 The module is in Silent Mode 2 Basic Basic Mode ...

Page 641: ...ion Register 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 Reserved BRPE Bits Description 31 4 Reserved Reserved 3 0 BRPE BRPE Baud Rate Prescaler Extension 0x00 0x0F By programming BRPE the Baud Rate Prescaler can be extended to values up to 1023 The actual interpretation by the hardware is that one more than the value...

Page 642: ...ace Register sets Each set of Interface Registers consists of Message Buffer Registers controlled by their own Command Registers The Command Mask Register specifies the direction of the data transfer and which parts of a Message Object will be transferred The Command Request Register is used to select a Message Object in the Message RAM as target or source for the transfer and to start the action ...

Page 643: ...rved 5 0 Message Number Message Number 0x01 0x20 Valid Message Number the Message Object in the Message RAM is selected for data transfer 0x00 Not a valid Message Number interpreted as 0x20 0x21 0x3F Not a valid Message Number interpreted as 0x01 0x1F A message transfer is started as soon as the application software has written the message number to the Command Request Register With this write ope...

Page 644: ...r data from the Message Object addressed by the Command Request Register into the selected Message Buffer Registers 1 Write Transfer data from the selected Message Buffer Registers to the Message Object addressed by the Command Request Register 6 Mask Access Mask Bits Write Operation 0 Mask bits unchanged 1 Transfer Identifier Mask MDir MXtd to Message Object Read Operation 0 Mask bits unchanged 1...

Page 645: ... IFn Message Control Register will be ignored Access New Data Bit when Read Operation 0 NewDat bit remains unchanged 1 Clear NewDat bit in the Message Object Note A read access to a Message Object can be combined with the reset of the control bits IntPnd and NewDat The values of these bits transferred to the IFn Message Control Register always reflect the status before resetting these bits 1 DAT_A...

Page 646: ...0 n 1 R W IFn Mask 1 Registers 0x0000_FFFF 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Msk 7 6 5 4 3 2 1 0 Msk Bits Description 31 16 Reserved Reserved 15 0 Msk Identifier Mask 15 0 0 The corresponding bit in the identifier of the message object cannot inhibit the match in the acceptance filtering 1 The corresponding identifier bit is used for acceptance...

Page 647: ...identifier bit IDE is used for acceptance filtering Note When 11 bit standard Identifiers are used for a Message Object the identifiers of received Data Frames are written into bits ID28 to ID18 CAN_IFn_ARB2 12 2 For acceptance filtering only these bits together with mask bits Msk28 to Msk18 CAN_IFn_MASK2 12 2 are considered 14 MDir Mask Message Direction 0 The message direction bit Dir CAN_IFn_AR...

Page 648: ...cription Reset Value CAN_IFn_ARB1 CAN_BA 0x30 0x60 n 1 R W IFn Arbitration 1 Registers 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 ID 7 6 5 4 3 2 1 0 ID Bits Description 31 16 Reserved Reserved 15 0 ID Message Identifier 15 0 ID28 ID0 29 bit Identifier Extended Frame ID28 ID18 11 bit Identifier Standard Frame ...

Page 649: ...et before the identifier Id28 0 CAN_IFn_ARB1 2 the control bits Xtd CAN_IFn_ARB2 14 Dir CAN_IFn_ARB2 13 or the Data Length Code DLC3 0 CAN_IFn_MCON 3 0 are modified or if the Messages Object is no longer required 14 Xtd Extended Identifier 0 The 11 bit standard Identifier will be used for this Message Object 1 The 29 bit extended Identifier will be used for this Message Object 13 Dir Message Direc...

Page 650: ... still set the CPU has lost a message Note Only valid for Message Objects with direction receive 13 IntPnd Interrupt Pending 0 This message object is not the source of an interrupt 1 This message object is the source of an interrupt The Interrupt Identifier in the Interrupt Register will point to this message object if there is no other interrupt source with higher priority 12 UMask Use Acceptance...

Page 651: ... has 8 data bytes Note The Data Length Code of a Message Object must be defined the same as in all the corresponding objects with the same identifier at other nodes When the Message Handler stores a data frame it will write the DLC to the value given by the received message Data 0 1st data byte of a CAN Data Frame Data 1 2nd data byte of a CAN Data Frame Data 2 3rd data byte of a CAN Data Frame Da...

Page 652: ...t Value CAN_IFn_DAT_A1 CAN_BA 0x3C 0x60 n 1 R W IFn Data A1 Registers Register Map Note 3 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Data 1 7 6 5 4 3 2 1 0 Data 0 Bits Description 31 16 Reserved Reserved 15 8 Data 1 Data Byte 1 2nd data byte of a CAN Data Frame 7 0 Data 0 Data Byte 0 1st data byte of a CAN Data Frame ...

Page 653: ...set Value CAN_IFn_DAT_A2 CAN_BA 0x40 0x60 n 1 R W IFn Data A2 Registers Register Map Note 3 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Data 3 7 6 5 4 3 2 1 0 Data 2 Bits Description 31 16 Reserved Reserved 15 8 Data 3 Data Byte 3 4th data byte of CAN Data Frame 7 0 Data 2 Data Byte 2 3rd data byte of CAN Data Frame ...

Page 654: ...set Value CAN_IFn_DAT_B1 CAN_BA 0x44 0x60 n 1 R W IFn Data B1 Registers Register Map Note 3 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Data 5 7 6 5 4 3 2 1 0 Data 4 Bits Description 31 16 Reserved Reserved 15 8 Data 5 Data Byte 5 6th data byte of CAN Data Frame 7 0 Data 4 Data Byte 4 5th data byte of CAN Data Frame ...

Page 655: ... Note 3 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Data 7 7 6 5 4 3 2 1 0 Data 6 Bits Description 31 16 Reserved Reserved 15 8 Data 7 Data Byte 7 8th data byte of CAN Data Frame 7 0 Data 6 Data Byte 6 7th data byte of CAN Data Frame In a CAN Data Frame Data 0 is the first Data 7 is the last byte to be transmitted or received In CAN s serial ...

Page 656: ...d CAN_IFn_ARB2 14 and Dir CAN_IFn_ARB2 13 are used to define the identifier and type of outgoing messages and are used together with the mask registers Msk28 0 CAN_IFn_MASK1 2 MXtd CAN_IFn_MASK2 15 and MDir CAN_IFn_MASK2 14 for acceptance filtering of incoming messages A received message is stored in the valid Message Object with matching identifier and Direction receive Data Frame or Direction tr...

Page 657: ...e IFn Message Interface Registers or by the Message Handler after reception of a Remote Frame or after a successful transmission Register Offset R W Description Reset Value CAN_TXREQ1 CAN_BA 0x100 R Transmission Request Register 1 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 TxRqst16 9 7 6 5 4 3 2 1 0 TxRqst8 1 Bits Description 31 16 Reserved ...

Page 658: ...nsmission Request Register 2 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 TxRqst32 25 7 6 5 4 3 2 1 0 TxRqst24 17 Bits Description 31 16 Reserved Reserved 15 0 TxRqst32 17 Transmission Request Bits 32 17 of All Message Objects Read Only 0 This Message Object is not waiting for transmission 1 The transmission of this Message Object is requested...

Page 659: ...n of a Data Frame or after a successful transmission Register Offset R W Description Reset Value CAN_NDAT1 CAN_BA 0x120 R New Data Register 1 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 NewData16 9 7 6 5 4 3 2 1 0 NewData8 1 Bits Description 31 16 Reserved Reserved 15 0 NewData16 1 New Data Bits 16 1 of All Message Objects 0 No new data has b...

Page 660: ... 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 NewData32 25 7 6 5 4 3 2 1 0 NewData24 17 Bits Description 31 16 Reserved Reserved 15 0 NewData32 17 New Data Bits 32 17 of All Message Objects 0 No new data has been written into the data portion of this Message Object by the Message Handler since the last time this flag was cleared by the application software 1 The Message Handler or the application...

Page 661: ...terface Registers or by the Message Handler after reception or after a successful transmission of a frame This will also affect the value of IntId in the Interrupt Register Register Offset R W Description Reset Value CAN_IPND1 CAN_BA 0x140 R Interrupt Pending Register 1 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 IntPnd16 9 7 6 5 4 3 2 1 0 In...

Page 662: ...N_BA 0x144 R Interrupt Pending Register 2 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 IntPnd32 25 7 6 5 4 3 2 1 0 IntPnd24 17 Bits Description 31 16 Reserved Reserved 15 0 IntPnd32 17 Interrupt Pending Bits 32 17 of All Message Objects 0 This message object is not the source of an interrupt 1 This message object is the source of an interrupt ...

Page 663: ...e Registers Register Offset R W Description Reset Value CAN_MVLD1 CAN_BA 0x160 R Message Valid Register 1 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 MsgVal16 9 7 6 5 4 3 2 1 0 MsgVal8 1 Bits Description 31 16 Reserved Reserved 15 0 MsgVal16 1 Message Valid Bits 16 1 of All Message Objects Read Only 0 This Message Object is ignored by the Mes...

Page 664: ...ved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 MsgVal32 25 7 6 5 4 3 2 1 0 MsgVal24 17 Bits Description 31 16 Reserved Reserved 15 0 MsgVal32 17 Message Valid Bits 32 17 of All Message Objects Read Only 0 This Message Object is ignored by the Message Handler 1 This Message Object is configured and should be considered by the Message Handler Note CAN_MVLD2 15 means Message object No 32 ...

Page 665: ...CAN_BA 0x168 R W Wake up Enable Control Register 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 Reserved WAKUP_EN Bits Description 31 1 Reserved Reserved 0 WAKUP_EN Wake up Enable Bit 0 The wake up function Disabled 1 The wake up function Enabled Note User can wake up system when there is a falling edge in the CAN_Rx pin...

Page 666: ...set Value CAN_WU_STATUS CAN_BA 0x16C R W Wake up Status Register 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 Reserved WAKUP_STS Bits Description 31 1 Reserved Reserved 0 WAKUP_STS Wake up Status 0 No wake up event occurred 1 Wake up event occurred Note This bit can be cleared by writing 0 to it ...

Page 667: ...e Supports programmable order reverse setting for input data and CRC checksum Supports programmable 1 s complement setting for input data and CRC checksum Supports 8 16 32 bit of data width 8 bit write mode 1 AHB clock cycle operation 16 bit write mode 2 AHB clock cycle operation 32 bit write mode 4 AHB clock cycle operation Supports using PDMA to write data to perform CRC operation 6 17 3 Block D...

Page 668: ...setting CHKSFMT CRC_CTL 27 Checksum 1 s Complement 2 Configure bit order reverse for CRC checksum by setting CHKSREV CRC_CTL 25 Checksum Bit Order Reverse The funcitonal block is also shown in Figure 6 17 2 CHECKSUM Bit Order Reverse Functional Block 3 Configure 1 s complement for CRC write data by setting DATFMT CRC_CTL 26 Write Data 1 s Complement 4 Configure bit order reverse for CRC write data...

Page 669: ...A21 M0A23 SERIES TECHNICAL REFERENCE MANUAL BIT31 Write Data Bit Order Reverse BIT30 BIT24 BIT7 BIT6 BIT0 BIT24 BIT25 BIT31 Bit Order Reverse per byte Bit Order Reverse per byte BIT0 BIT1 BIT7 MSB LSB Figure 6 17 3 Write Data Bit Order Reverse Functional Block ...

Page 670: ... only R W both read and write Register Offset R W Description Reset Value CRC Base Address CRC_BA 0x4003_1000 CRC_CTL CRC_BA 0x00 R W CRC Control Register 0x2000_0000 CRC_DAT CRC_BA 0x04 R W CRC Write Data Register 0x0000_0000 CRC_SEED CRC_BA 0x08 R W CRC Seed Register 0xFFFF_FFFF CRC_CHECKSUM CRC_BA 0x0C R CRC Checksum Register 0xFFFF_FFFF ...

Page 671: ...ength is 32 bit mode Note When the write data length is 8 bit mode the valid data in CRC_DAT register is only DATA 7 0 bits if the write data length is 16 bit mode the valid data in CRC_DAT register is only DATA 15 0 27 CHKSFMT Checksum 1 s Complement This bit is used to enable the 1 s complement function for checksum result in CRC_CHECKSUM register 0 1 s complement for CRC checksum Disabled 1 1 s...

Page 672: ...rsed for CRC write data in Disabled 1 Bit order reversed for CRC write data in Enabled per byte Note If the write data is 0xAABBCCDD the bit order reverse for CRC write data in is 0x55DD33BB 23 2 Reserved Reserved 1 CHKSINIT Checksum Initialization 0 No effect 1 Initial checksum value by auto reload CRC_SEED register value to CRC_CHECKSUM register value Note This bit will be cleared automatically ...

Page 673: ...27 26 25 24 DATA 23 22 21 20 19 18 17 16 DATA 15 14 13 12 11 10 9 8 DATA 7 6 5 4 3 2 1 0 DATA Bits Description 31 0 DATA CRC Write Data Bits User can write data directly by CPU mode or use PDMA function to write data to this field to perform CRC operation Note When the write data length is 8 bit mode the valid data in CRC_DAT register is only DATA 7 0 bits if the write data length is 16 bit mode t...

Page 674: ...et Value CRC_SEED CRC_BA 0x08 R W CRC Seed Register 0xFFFF_FFFF 31 30 29 28 27 26 25 24 SEED 23 22 21 20 19 18 17 16 SEED 15 14 13 12 11 10 9 8 SEED 7 6 5 4 3 2 1 0 SEED Bits Description 31 0 SEED CRC Seed Value This field indicates the CRC seed value Note This field will be reloaded as checksum initial value CRC_CHECKSUM register after perform CHKSINIT CRC_CTL 1 ...

Page 675: ...ts Description 31 0 CHECKSUM CRC Checksum Results This field indicates the CRC checksum result Note Data in CRC_CHECKSUM register has different length when user chooses different operation polynomial modes For example If final checksum result is 0x12 in CRC 8 polynomial mode the CHECKSUM 31 0 value will be read as 0x12121212 only CHECKSUM 7 0 is valid in this mode If final checksum result is 0x123...

Page 676: ... it needs to set dividend first Then set divisor and the hardware divider will trigger calculation automatically after divisor written The calculation results including the quotient and remainder could be obtained by reading DIVQUO and DIVREM register User can read quotient and remainder after one cycle of writing the divisor DIV0 flag of DIVSTS will be set if divisor is 0 The dividend is 32 bit s...

Page 677: ...r Offset R W Description Reset Value HDIV Base Address HDIV_BA 0x4001_4000 DIVIDEND HDIV_BA 0x00 R W Dividend Source Register 0x0000_0000 DIVISOR HDIV_BA 0x04 R W Divisor Source Resister 0x0000_FFFF DIVQUO HDIV_BA 0x08 R W Quotient Result Resister 0x0000_0000 DIVREM HDIV_BA 0x0C R W Remainder Result Register 0x0000_0000 DIVSTS HDIV_BA 0x10 R Divider Status Register 0x0000_0001 ...

Page 678: ...IVIDEND Register Offset R W Description Reset Value DIVIDEND HDIV_BA 0x00 R W Dividend Source Register 0x0000_0000 31 30 29 28 27 26 25 24 DIVIDEND 23 22 21 20 19 18 17 16 DIVIDEND 15 14 13 12 11 10 9 8 DIVIDEND 7 6 5 4 3 2 1 0 DIVIDEND Bits Description 31 0 DIVIDEND Dividend Source This register is given the dividend of divider before calculation started ...

Page 679: ...HDIV_BA 0x04 R W Divisor Source Resister 0x0000_FFFF 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 DIVISOR 7 6 5 4 3 2 1 0 DIVISOR Bits Description 31 16 Reserved Reserved 15 0 DIVISOR Divisor Source This register is given the divisor of divider before calculation starts Note When this register is written hardware divider will start calculation ...

Page 680: ...Offset R W Description Reset Value DIVQUO HDIV_BA 0x08 R W Quotient Result Resister 0x0000_0000 31 30 29 28 27 26 25 24 QUOTIENT 23 22 21 20 19 18 17 16 QUOTIENT 15 14 13 12 11 10 9 8 QUOTIENT 7 6 5 4 3 2 1 0 QUOTIENT Bits Description 31 0 QUOTIENT Quotient Result This register holds the quotient result of divider after calculation is complete ...

Page 681: ...31 30 29 28 27 26 25 24 REMAINDER 23 22 21 20 19 18 17 16 REMAINDER 15 14 13 12 11 10 9 8 REMAINDER 7 6 5 4 3 2 1 0 REMAINDER Bits Description 31 16 REMAINDER 31 16 Sign Extension of REMAINDER 15 0 The remainder of hardware divider is 16 bit sign integer REMAINDER 15 0 with sign extension REMAINDER 31 16 to 32 bit integer 15 0 REMAINDER 15 0 Remainder Result This register holds the remainder resul...

Page 682: ...er 0x0000_0001 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 Reserved DIV0 Reserved Bits Description 31 2 Reserved Reserved 1 DIV0 Divisor Zero Warning Read Only 0 The divisor is not 0 1 The divisor is 0 Note The DIV0 flag is used to indicate divide by zero situation and updated whenever DIVISOR is written This register is read onl...

Page 683: ...tores the result in FIFO Single cycle Scan mode A D conversion is performed only one cycle on all specified channels with the sequence from the smallest numbered channel to the largest numbered channel Continuous Scan mode A D converter continuously performs Single cycle Scan mode until software stops A D conversion An A D conversion can be started by Software Write 1 to ADST bit External pin STAD...

Page 684: ...29 30 ADDR29 30 PDMA request SYS_VREFCTL 3 0 INT_VREF AIN0 AIN1 AIN16 VTEMPEN SYS_IVSCTL 0 DAC0_OUT INT_VREF Figure 6 19 1 AD Controller Block Diagram 6 19 4 Basic Configuration The ADC pin functions are configured in SYS_GPA_MFP0 SYS_GPA_MFP1 SYS_GPB_MFP1 SYS_GPC_MFP0 SYS_GPC_MFP1 registers It is recommended to disable the digital input path of the analog input pins to avoid the leakage current U...

Page 685: ...formed only once on the specified single channel The operations are as follows 1 A D conversion will be started when the ADST bit of ADC_ADCR register is set to 1 by software or external trigger input 2 When A D conversion is finished the result is stored in the ADC data register corresponding to the channel 3 The ADF bit of ADC_ADSR0 register will be set to 1 If the ADIE bit of ADC_ADCR register ...

Page 686: ...R register is set to 1 by software or external trigger input A D conversion is started on the enabled channel with the smallest number 2 When A D conversion for the specified channel is completed the result is sequentially transferred to FIFO and can be accessed only from the ADC data register 0 3 When more than or equal to 8 samples in FIFO the ADF bit in ADC_ADSR0 register is set to 1 If the ADI...

Page 687: ...verter samples and converts all of the specified channels once in the sequence from the smallest number enabled channel to the largest number enabled channel Operations are as follows 1 When the ADST bit in ADC_ADCR register is set to 1 by software or external trigger input A D conversion is started on the enabled channel with the smallest number 2 When A D conversion for each enabled channel is c...

Page 688: ... software or external trigger input A D conversion is started on the enabled channel with the smallest number 2 When A D conversion for each enabled channel is completed the result of each enabled channel is stored in the ADC data register corresponding to each enabled channel 3 When A D converter completes the conversions of all enabled channels sequentially the ADF bit in ADC_ADSR0 register will...

Page 689: ...n external condition trigger condition disappears If edge trigger condition is selected the high and low state must be kept at least 4 PCLKs Pulse that is shorter than this specification will be ignored Note User enables the external trigger function or enables ADC must be at least 4 PCLKs after enabling ADC peripheral clock Timer trigger There are 4 Timer trigger sources for ADC When the TRGEN bi...

Page 690: ...6 19 7 A D Conversion Result Monitor Logic Diagram Compare Window Mode The ADC controller supports a compare window mode User can set CMPWEN ADC_ADCMPR0 15 to enable this function If user enables this function CMPF0 ADC_ADSR0 1 will be set only when compared conditions of two conversion result monitor logic are matched and CMPF1 ADC_ADSR0 2 will always be zero The range of compare window is betwee...

Page 691: ...egisters the corresponding flag will be set to 1 When one of the flags ADF CMPF0 and CMPF1 is set to 1 and the corresponding interrupt enable bit ADIE of ADC_ADCR register and CMPIE of ADC_ADCMPR0 1 registers is set to 1 the ADC interrupt will be asserted Software can clear these flags to revoke the interrupt request ADF ADSR0 0 ADIE ADCR 1 CMPF1 ADSR0 2 CMPIE ADCMPR1 1 ADC_INT CMPF0 ADSR0 1 CMPIE...

Page 692: ...000 ADC_ADDR10 ADC_BA 0x28 R ADC Data Register 10 0x0000_0000 ADC_ADDR11 ADC_BA 0x2C R ADC Data Register 11 0x0000_0000 ADC_ADDR12 ADC_BA 0x30 R ADC Data Register 12 0x0000_0000 ADC_ADDR13 ADC_BA 0x34 R ADC Data Register 13 0x0000_0000 ADC_ADDR14 ADC_BA 0x38 R ADC Data Register 14 0x0000_0000 ADC_ADDR15 ADC_BA 0x3C R ADC Data Register 15 0x0000_0000 ADC_ADDR16 ADC_BA 0x40 R ADC Data Register 16 0x...

Page 693: ...2 M0A21 M0A23 SERIES TECHNICAL REFERENCE MANUAL ADC_ADSR2 ADC_BA 0x98 R ADC Status Register2 0x0000_0000 ADC_ADTDCR ADC_BA 0x9C R W ADC Trigger Delay Control Register 0x0000_0000 ADC_ADPDMA ADC_BA 0x100 R ADC PDMA Current Transfer Data Register 0x0000_0000 ...

Page 694: ...ADC_ADDR8 ADC_BA 0x20 R ADC Data Register 8 0x0000_0000 ADC_ADDR9 ADC_BA 0x24 R ADC Data Register 9 0x0000_0000 ADC_ADDR10 ADC_BA 0x28 R ADC Data Register 10 0x0000_0000 ADC_ADDR11 ADC_BA 0x2C R ADC Data Register 11 0x0000_0000 ADC_ADDR12 ADC_BA 0x30 R ADC Data Register 12 0x0000_0000 ADC_ADDR13 ADC_BA 0x34 R ADC Data Register 13 0x0000_0000 ADC_ADDR14 ADC_BA 0x38 R ADC Data Register 14 0x0000_000...

Page 695: ...ly If converted data in RSLT bits has not been read before new conversion result is loaded to this register OVERRUN bit is set to 1 It is cleared by hardware after ADDR register is read 0 Data in RSLT bits is not overwrote 1 Data in RSLT bits is overwrote 15 0 RSLT A D Conversion Result Read Only This field contains conversion result of ADC Note Vref voltage comes from VREF AVDD Single end Input V...

Page 696: ...0001 1000_0000_0000 0111_1111_1111 0 1 LSB Vref 4096 1111_1000_0000_0000 ADC result in RSLT 15 0 DMOF 1 1111_1000_0000_0001 1111_1000_0000_0010 0000_0111_1111_1111 0000_0111_1111_1110 0000_0111_1111_1101 Vref 1 LSB Vref 1 LSB Differential Input Voltage Vdiff V 0000_0000_0000_0001 0000_0000_0000_0000 1111_1111_1111_1111 0 1 LSB Vref 4096 Note Vref voltage comes from VREF AVDD Note Vref voltage come...

Page 697: ...ete conversion 001 5 ADC clock for sampling 17 ADC clock for complete conversion 010 6 ADC clock for sampling 18 ADC clock for complete conversion 011 7 ADC clock for sampling 19 ADC clock for complete conversion 100 8 ADC clock for sampling 20 ADC clock for complete conversion 101 9 ADC clock for sampling 21 ADC clock for complete conversion 110 10 ADC clock for sampling 22 ADC clock for complete...

Page 698: ... Enabled Note The ADC external trigger function is only supported in Single cycle Scan mode 7 6 TRGCOND External Trigger Condition These two bits decide external pin STADC trigger event is level or edge The signal must be kept at stable state at least 8 PCLKs for level trigger and at least 4 PCLKs for edge trigger 00 Low level 01 High level 10 Falling edge 11 Rising edge 5 4 TRGS Hardware Trigger ...

Page 699: ...DCHER 16 0 bits to enable the corresponding analog input channel 16 0 If DIFFEN bit is set to 1 only the even number channel needs to be enabled Besides set ADC_ ADCHER 26 ADC_ ADCHER 27 ADC_ ADCHER 29 ADC_ ADCHER 30 bits will enable internal channel for internal reference voltage DAC0_OUT band gap voltage and temperature sensor respectively Other bits are reserved 0 Channel Disabled 1 Channel Ena...

Page 700: ...rved Reserved 11 8 CMPMATCNT Compare Match Count When the specified A D channel analog conversion result matches the compare condition defined by CMPCOND bit the internal match counter will increase 1 When the internal counter reaches the value to CMPMATCNT 1 the CMPFx bit will be set 7 3 CMPCH Compare Channel Selection 00000 Channel 0 conversion result is selected to be compared 00001 Channel 1 c...

Page 701: ...ndition as that when a 12 bit A D conversion result is less than the 12 bit CMPD bits the internal match counter will increase one 1 Set the compare condition as that when a 12 bit A D conversion result is greater than or equal to the 12 bit CMPD bits the internal match counter will increase one Note When the internal counter reaches to CMPMATCNT 1 the CMPFx bit will be set 1 CMPIE Compare Interru...

Page 702: ... 15 9 Reserved Reserved 8 VALIDF Data Valid Flag Read Only If any one of VALID ADDRx 17 is set this flag will be set to 1 Note When ADC is in burst mode and any conversion result is valid this flag will be set to 1 7 BUSY BUSY IDLE Read Only This bit is a mirror of ADST bit in ADCR register 0 A D converter is in idle state 1 A D converter is busy at conversion 6 3 Reserved Reserved 2 CMPF1 Compare...

Page 703: ...tes the end of A D conversion Software can write 1 to clear this bit ADF bit is set to 1 at the following three conditions 1 When A D conversion ends in Single mode 2 When A D conversion ends on all specified channels in Single cycle Scan mode and Continuous Scan mode 3 When more than or equal to 8 samples in FIFO in Burst mode ...

Page 704: ... 30 29 28 27 26 25 24 VALID 23 22 21 20 19 18 17 16 VALID 15 14 13 12 11 10 9 8 VALID 7 6 5 4 3 2 1 0 VALID Bits Description 31 0 VALID Data Valid Flag Read Only VALID 30 29 VALID 27 26 VALID 16 0 are the mirror of the VALID bits in ADDR30 17 ADDR29 17 ADDR27 17 ADDR26 17 ADDR16 17 ADDR0 17 The other bits are reserved Note When ADC is in burst mode and any conversion result is valid VALID 30 29 VA...

Page 705: ...29 28 27 26 25 24 OVERRUN 23 22 23 22 19 18 17 16 OVERRUN 15 14 15 14 11 10 9 8 OVERRUN 7 6 5 4 3 2 1 0 OVERRUN Bits Description 31 0 OVERRUN Overrun Flag Read Only OVERRUN 30 29 OVERRUN 27 26 OVERRUN 16 0 are the mirror of the OVERRUN bit in ADDR30 16 ADDR29 16 ADDR27 16 ADDR26 16 ADDR16 16 ADDR0 16 The other bits are reserved Note When ADC is in burst mode and the FIFO is overrun OVERRUN 30 29 O...

Page 706: ... Value ADC_ADTDCR ADC_BA 0x9C R W ADC Trigger Delay Control Register 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 PTDT Bits Description 31 8 Reserved Reserved 7 0 PTDT PWM Trigger Delay Time Set this field will delay ADC start conversion time after PWM trigger PWM trigger delay time is 4 PTDT system clock ...

Page 707: ...er Data Register 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 23 22 19 18 17 16 Reserved CURDAT 15 14 15 14 11 10 9 8 CURDAT 7 6 5 4 3 2 1 0 CURDAT Bits Description 31 18 Reserved Reserved 17 0 CURDAT ADC PDMA Current Transfer Data Register Read Only When PDMA transferring read this register can monitor current PDMA transfer data Current PDMA transfer data could be the content of ADDR0 ADDR1...

Page 708: ...g output voltage range 0 AVDD voltage of VDD pin Reference voltage from internal reference voltage VREF pin or AVDD DAC maximum conversion updating rate 100k SPS Rail to rail settle time 10us Supports software and timer0 3 trigger to start DAC conversion Supports PDMA mode 6 20 3 Block Diagram TIMER0_TRIG TIMER3_TRIG SWTRIG TIMER1_TRIG TIMER2_TRIG Reserved Reserved Control Logic DAC_DOR DAC_DHR DM...

Page 709: ...d in the DAC_DAT register is automatically transferred to the data output buffer DAC_DATOUT after occurring one PCLK APB clock the event When DAC data output register DAC_DATOUT is loaded with the DAC_DAT contents the analog output voltage becomes available after specified conversion settling time The conversion settling time is 10us when 5 bit input code transition from lowest code 0x00 to highes...

Page 710: ...AC starts converting once DAC_DATOUT 4 0 is updated Trigger Event 0x13 PCLK 0x13 0x14 0x14 DAC_DAT DAC_DATOUT Figure 6 20 3 DAC Conversion Started by Hardware Trigger Event PDMA Operation DAC to PDMA request is generated when a hardware trigger event occurs while DMAEN DAC_CTL 2 is set The content of DAC_DAT is transferred to the DAC_DATOUT 4 0 and DAC starts data conversion The new transferred da...

Page 711: ...enerated by software enable user sets DMAEN DAC_CTL 2 to 1 and TRGEN DAC_CTL 4 to 0 DMA request is generated periodically according to the conversion time defined by SETTLET DAC_TCTL 9 0 value DAC output is updated periodically When user clears DMAEN DAC_CTL 2 to 0 DAC controller will stop issuing next new PDMA transfer request PDMA Acknowledge 0x13 PCLK 0x13 0x14 0x14 PDMA Request TSETTLING 0x15 ...

Page 712: ...under run interrupt When DAC conversion finish the FINISH DAC_STATUS 0 is set to 1 and an interrupt occurs while DACIEN DAC_CTL 1 is enabled If new DMA trigger event occurs during DAC data conversion period the DMA under run flag DMAUDR DAC_STATUS 1 is generated and an interrupt occurs if DMAURIEN DAC_CTL 3 is enabled DAC_INT DACIEN DAC_CTL 1 FINISH DAC_STATUS 0 DMAIEN DAC_CTL 3 DMAUDR DAC_STATUS ...

Page 713: ...DAC Base Address DAC_BA 0x4004_7000 DAC_CTL DAC_BA 0x00 R W DAC Control Register 0x0000_0000 DAC_SWTRG DAC_BA 0x04 R W DAC Software Trigger Control Register 0x0000_0000 DAC_DAT DAC_BA 0x08 R W DAC Data Holding Register 0x0000_0000 DAC_DATOUT DAC_BA 0x0C R DAC Data Output Register 0x0000_0000 DAC_STATUS DAC_BA 0x10 R W DAC Status Register 0x0000_0000 DAC_TCTL DAC_BA 0x14 R W DAC Timing Control Regi...

Page 714: ... 10 Reserved Reserved 9 DACPSEL DAC Reference Voltage Selection 0 Select AVDD voltage of VDD pin 1 Select VREF 8 OUTPUTOE DAC Output Enable 1 DAC otuput to PAD Enabled 0 DAC output to PAD disabled 7 5 TRGSEL Trigger Source Selection 000 Software trigger 001 reserved 010 Timer 0 trigger 011 Timer 1 trigger 100 Timer 2 trigger 101 Timer 3 trigger 110 reserved 111 reserved 4 TRGEN Trigger Mode Enable...

Page 715: ...eries May 06 2022 Page 715 of 746 Rev 1 02 M0A21 M0A23 SERIES TECHNICAL REFERENCE MANUAL 1 DACIEN DAC Interrupt Enable Bit 0 Interrupt Disabled 1 Interrupt Enabled 0 DACEN DAC Enable Bit 0 DAC Disabled 1 DAC Enabled ...

Page 716: ...Software Trigger Control Register 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 Reserved SWTRG Bits Description 31 1 Reserved Reserved 0 SWTRG Software Trigger 0 Software trigger Disabled 1 Software trigger Enabled User writes this bit to generate one shot pulse and it is cleared to 0 by hardware automatically Reading t...

Page 717: ...Reset Value DAC_DAT DAC_BA 0x08 R W DAC Data Holding Register 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 Reserved DACDAT Bits Description 31 16 Reserved Reserved 4 0 DACDAT DAC 5 bit Holding Data These bits are written by user software which specifies 5 bit conversion data for DAC output ...

Page 718: ...ATOUT DAC_BA 0x0C R DAC Data Output Register 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 Reserved DATOUT Bits Description 31 5 Reserved Reserved 4 0 DATOUT DAC 5 bit Output Data These bits are current digital data for DAC output conversion It is loaded from DAC_DAT register and user cannot write it directly ...

Page 719: ...s Description 31 9 Reserved Reserved 8 BUSY DAC Busy Flag Read Only 0 DAC is ready for next conversion 1 DAC is busy in conversion This is read only bit 7 2 Reserved Reserved 1 DMAUDR DMA Under Run Interrupt Flag 0 No DMA under run error condition occurred 1 DMA under run error condition occurred User writes 1 to clear this bit 0 FINISH DAC Conversion Complete Finish Flag 0 DAC is in conversion st...

Page 720: ...29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved SETTLET 7 6 5 4 3 2 1 0 SETTLET Bits Description 31 10 Reserved Reserved 9 0 SETTLET DAC Output Settling Time User software needs to write appropriate value to these bits to meet DAC conversion settling time base on PCLK APB clock speed For example DAC controller clock speed is 72 MHz and DAC conversion sett...

Page 721: ...d 30mV Supports wake up function Selectable input sources of positive input and negative input ACMP0 supports 3 multiplexed I O pins at positive sources ACMP0_P0 Comparator Reference Voltage CRV and DAC0 output 5 negative sources ACMP0_N0 ACMP0_N1 ACMP0_N2 ACMP0_N3 Comparator Reference Voltage CRV ACMP1 supports 3 multiplexed I O pins at positive sources ACMP1_P0 Comparator Reference Voltage CRV a...

Page 722: ... 12 ACMP0_P0 ACMP0_O ACMP1_O ACMP01_INT 0 1 ACMP1 ACMP0 ACMPS1 ACMP_STATUS 13 Filter Block DAC0_OUT 001 010 011 100 101 ACMP0_N1 ACMP0_N0 ACMP0_N2 ACMP0_N3 001 010 011 DAC0_OUT 001 010 011 100 101 ACMP1_P0 ACMP1_N0 ACMP1_N1 ACMP1_N2 ACMP1_N3 CRV function CRVEN ACMP_VREF 8 INTPOL ACMP_CTL0 21 20 INTPOL ACMP_CTL1 21 20 AVDD Figure 6 21 1 Analog Comparator Block Diagram 6 21 4 Basic Configuration 6 2...

Page 723: ...itive input voltage exceeds the negative input voltage by a high threshold voltage Similarly if comparator output is 1 it will not be changed to 0 until the positive input voltage drops below the negative input voltage by a low threshold voltage High threshold voltage Low threshold voltage ACMP0_P ACMP0_N ACMP0_O Figure 6 21 2 Comparator Hysteresis Function of ACMP0 6 21 5 2 Window Latch Mode Figu...

Page 724: ...e it can be output to ACMPO0 If the comparing result is shorter than 4 PCLK it will be filted ACMP0_P ACMP0_N ACMPO0 PCLK 1 2 3 4 1 2 3 4 1 Comparing Result Comparing Result 1 2 3 4 Figure 6 21 4 Filter Function Example 6 21 5 4 Interrupt Sources The outputs of ACMP0 and ACMP1 are reflected at ACMPO0 ACMP_STATUS 4 and ACMPO1 ACMP_STATUS 5 respectively Then they are processed by window latch and fi...

Page 725: ... pin or the internal VREF 0 1 4R R Internal VREF CRVSSEL ACMP_VREF 6 R R R R 4R 0000 0001 0010 1111 1110 1101 AVDD CRVCTL ACMP_VREF 3 0 CRV output Figure 6 21 6 Comparator Reference Voltage Block Diagram 6 21 5 6 Window Compare Mode The comparator provides window compare mode When window compare mode is enabled by setting WCMPSEL ACMP_CTL0 1 18 to 1 user can monitor a specific analog voltage sourc...

Page 726: ...ge of lower bound and upper bound which are called as the voltage source is in the window Otherwise the voltage source is outside the window ACMP0 ACMP1 Analog macro Voltage of lower bound ACMPS1 ACMPS0 ACMPWO Voltage source Voltage of upper bound Figure 6 21 7 Example of Window Compare Mode The comparator window output ACMPWO can be shown in ACMP_STATUS 16 and the truth table of window compare lo...

Page 727: ...of Window Compare Mode As shown in Figure 6 21 8 if ACMPWO equals 1 it means positive input voltage is inside the window Otherwise the positive input voltage is outside the window Therefore ACMPWO can be used to monitor voltage transition of external analog pin Furthermore ACMPWO still can be applied to window latch filter functions and interrupt of ACMP Note that negative inputs must choose diffe...

Page 728: ... Description Reset Value ACMP Base Address ACMP01_BA 0x4004_5000 ACMP_CTL0 ACMP01_BA 0x00 R W Analog Comparator 0 Control Register 0x0000_0000 ACMP_CTL1 ACMP01_BA 0x04 R W Analog Comparator 1 Control Register 0x0000_0000 ACMP_STATUS ACMP01_BA 0x08 R W Analog Comparator Status Register 0x0000_0000 ACMP_VREF ACMP01_BA 0x0C R W Analog Comparator Reference Voltage Control Register 0x0000_0000 ...

Page 729: ... Description 31 Reserved Reserved 30 HYSBYPASS Hysteresis Adjust Function Selection 0 Enable adjust function 1 Bypass adjust function 29 26 Reserved Reserved 25 24 HYSSEL Hysteresis Mode Selection 00 Hysteresis is 0mV 11 Hysteresis is 30mV 23 22 Reserved Reserved 21 20 INTPOL Interrupt Condition Polarity Selection ACMPIF0 will be set to 1 when comparator output edge condition is detected 00 Rising...

Page 730: ...Comparator 0 output to ACMP0_O pin is from filter output 11 Reserved Reserved 10 8 POSSEL Comparator Positive Input Selection 000 All positive input disabled 001 Input from ACMP0_P0 010 Comparator Reference Voltage CRV 011 DAC0 output Others Reserved 7 Reserved Reserved 6 4 NEGSEL Comparator Negative Input Selection 000 All negative input disbaled 001 ACMP0_N0 010 ACMP0_N1 011 ACMP0_N2 100 ACMP0_N...

Page 731: ...s 0mV 11 Hysteresis is 30mV 23 22 Reserved Reserved 21 20 INTPOL Interrupt Condition Polarity Selection ACMPIF0 will be set to 1 when comparator output edge condition is detected 00 Rising edge or falling edge 01 Rising edge 10 Falling edge 11 Reserved 19 Reserved Reserved 18 WCMPSEL Window Compare Mode Selection 0 Window Compare Mode Disabled 1 Window Compare Mode Selected 17 WLATEN Window Latch ...

Page 732: ...n 000 All positive input disabled 001 Input from ACMP1_P0 010 Comparator Reference Voltage CRV 011 DAC0 output Others Reserved 7 Reserved Reserved 6 4 NEGSEL Comparator Negative Input Selection 000 All negative input disbaled 001 ACMP1_N0 010 ACMP1_N1 011 ACMP1_N2 100 ACMP1_N3 101 Comparator Reference Voltage CRV Others Reserved 3 ACMPOINV Comparator Output Inverse Control 0 Comparator 1 output in...

Page 733: ...s Synchronized to the PCLK to allow reading by software Cleared when the comparator 1 is disabled i e ACMPEN ACMP_CTL1 0 is cleared to 0 12 ACMPS0 Comparator 0 Status Synchronized to the PCLK to allow reading by software Cleared when the comparator 0 is disabled i e ACMPEN ACMP_CTL0 0 is cleared to 0 11 10 Reserved Reserved 9 WKIF1 Comparator 1 Power down Wake up Interrupt Flag This bit will be se...

Page 734: ...IF1 Comparator 1 Interrupt Flag This bit is set by hardware when the edge condition defined by INTPOL ACMP_CTL1 21 20 is detected on comparator 1 output This will cause an interrupt if ACMPIE ACMP_CTL1 1 is set to 1 Note Write 1 to clear this bit to 0 0 ACMPIF0 Comparator 0 Interrupt Flag This bit is set by hardware when the edge condition defined by INTPOL ACMP_CTL0 21 20 is detected on comparato...

Page 735: ... 11 10 9 8 Reserved COMPEN CRVEN 7 6 5 4 3 2 1 0 Reserved CRVSSEL Reserved CRVCTL Bits Description 31 10 Reserved Reserved 9 COMPEN Comparator Bias Enable Bit 0 Comparator bias Disabled 1 Comparator bias Enabled 8 CRVEN CRV Function Enable Bit 0 CRV function Disabled 1 CRV function Enabled 7 Reserved Reserved 6 CRVSSEL CRV Source Voltage Selection 0 AVDD voltage of VDD pin is selected as CRV sourc...

Page 736: ...The detailed PWM trigger conditions are described in section 6 10 5 23 Timer Trigger ADC Conversion Timer0 Timer3 can be one of the ADC conversion trigger source When timer counter value matches the timer compared value or when the TMx_EXT pin edge transition meets setting timer will trigger the ADC to start the conversion Setting the ADC external hardware trigger input source from timer trigger i...

Page 737: ...RC clock Speed Set the timer capture source from LIRC clock and measure the time interval of the signal by using timer capture function The results of time interval can be used to trim LIRC through software The detailed setting of time capture function is described in section 6 7 6 8 From Timer0 2 to Timer1 3 Inter Timer Trigger Capture Mode Timer0 2 will be forced in event counting mode counting ...

Page 738: ...0A21 M0A23 SERIES TECHNICAL REFERENCE MANUAL 7 APPLICATION CIRCUIT 7 1 Power Supply Scheme VDD VSS 0 1uF N 10uF 0 1uF EXT_PWR EXT_VSS as close to VDD as possible as close to the EXT_PWR as possible VREF L 30Z as close to VREF as possible 2 2uF 1uF 470pF L 30Z ...

Page 739: ...eiver ROUT TIN RIN TOUT PC COM Port UART UART_RXD UART_TXD DVCC 10 uF nRESET 4 24 MHz crystal XT1_OUT XT1_IN VDD VSS I2 C Device CLK DIO I2C_SDA I2C_SCL DVCC DVCC VDD VSS nRESET ICE_DAT ICE_CLK SWD Interface X32_OUT X32_IN Reset Circuit VDD VSS SPI Device CS CLK MISO SPI_SS MOSI SPI_CLK SPI_MISO SPI_MOSI DVCC 20pF 20pF 20pF 20pF 10K 32 768 kHz crystal 4 7K 4 7K DVCC 100K 100K ...

Page 740: ...y 06 2022 Page 740 of 746 Rev 1 02 M0A21 M0A23 SERIES TECHNICAL REFERENCE MANUAL 8 ELECTRICAL CHARACTERISTICS Please refer to the relative Datasheet for detailed information about the M0A21 M0A23 electrical characteristics ...

Page 741: ...M0A21 M0A23 Series May 06 2022 Page 741 of 746 Rev 1 02 M0A21 M0A23 SERIES TECHNICAL REFERENCE MANUAL 9 PACKAGE DIMENSIONS 9 1 SSOP 20 5 3x7 2x1 75 mm ...

Page 742: ...M0A21 M0A23 Series May 06 2022 Page 742 of 746 Rev 1 02 M0A21 M0A23 SERIES TECHNICAL REFERENCE MANUAL 9 2 TSSOP 28 4 4x9 7x1 0 mm ...

Page 743: ...ernet MAC Controller EPWM Enhanced Pulse Width Modulation FIFO First In First Out FMC Flash Memory Controller FPU Floating point Unit GPIO General Purpose Input Output HCLK The Clock of Advanced High Performance Bus HIRC 12 MHz Internal High Speed RC Oscillator HXT 4 24 MHz External High Speed Crystal Oscillator IAP In Application Programming ICP In Circuit Programming ISP In System Programming LD...

Page 744: ...erface SD Secure Digital SPI Serial Peripheral Interface SPS Samples per Second TDES Triple Data Encryption Standard TK Touch Key TMR Timer Controller UART Universal Asynchronous Receiver Transmitter UCID Unique Customer ID USB Universal Serial Bus WDT Watchdog Timer WWDT Window Watchdog Timer Table 10 1 1 List of Abbreviations ...

Page 745: ...M0A21 M0A23 SERIES TECHNICAL REFERENCE MANUAL 11 REVISION HISTORY Date Revision Description 2020 11 23 1 00 Initial version 2022 02 23 1 01 Fixed Figure 6 14 7 and Figure 6 14 8 overlapping 2022 05 06 1 02 Fixed the max frequency of HXT from 32 MHz to 24 MHz ...

Page 746: ...e includes but is not limited to equipment for surgical implementation atomic energy control instruments airplane or spaceship instruments the control or operation of dynamic brake or safety systems designed for vehicular use traffic signal instruments all types of safety devices and other applications intended to support or sustain life All Insecure Usage shall be made at customer s risk and in t...

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