NEC IMAGE P100E - SERVICE, Service Manual

Page: 31 / 220

Technical Information 1-15
Table 1-4 I/O Address Map (cont’d)
Address (Hex) I/O Device Name Location Access
03F0 Floppy control System I/O controller R/W
0401-04FF DMA registers ESC W, R. R/W
0800-08FF Configuration SRAM ESC R/W
0C10, 0C11,
0C12, 0C13 NEC Proprietary Ports R, W, R/W
0CF8 Configuration Space Enable (CSE) PCMC R/W
0CF9 Turbo-reset control (TRC) PCMC R/W
0CFA Forward register PCMC R/W
0CFB PCI mechanism control (PMC) PCMC R/W
0CFC Configuration data PCMC R/W
Determined by
PCEB BTMR
configuration
register
BIOS timer PCEB R/W
0C00 Configuration SRAM page register ESC R/W
NEC Proprietary Ports
The ESC is programmed to drive the GPCS0* output active when a read or write is done to
I/O 0C40h, 0C41h, 0C42h, or 0C43h. NEC ports are accessed by gating GPCS0* with the
lower two bits of the address bus. The following paragraphs describe the NEC proprietary
ports 0C10h, 0C11h, 0C12h, and 0C13h.