Motorola MVME1X7P Programmer'S Reference Manual Download Page 89

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Error Conditions

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1-63

SCSI LTO Error

Description:

Local Bus Time-out occurred while the 53C710 was Local
Bus master.

MPU Notification:

53C710 Interrupt

Status:

53C710 DMA Status register
53C710 DMA Interrupt Status register
PCCchip2 SCSI Error Status register ($FFF4202C)

Comments:

53C710 interrupt enables are controlled in the 53C710 and
in the PCCchip2.

Summary of Contents for MVME1X7P

Page 1: ...MVME1X7P Single Board Computer Programmer s Reference Guide V1X7PA PG1 Edition of October 2000 ...

Page 2: ...e United States of America Motorola and the Motorola logo are registered trademarks of Motorola Inc MC68040 and MC68060 are trademarks of Motorola Inc All other products mentioned in this document are trademarks or registered trademarks of their respective holders ...

Page 3: ...ide the Equipment Operating personnel must not remove equipment covers Only Factory Authorized Service Personnel or other qualified service personnel may remove equipment covers for internal subassembly or component replacement or any internal adjustment Service personnel should not replace components with power cable connected Under certain conditions dangerous voltages may exist even with the po...

Page 4: ...losion if battery is replaced incorrectly Replace battery only with the same or equivalent type recommended by the equipment manufacturer Dispose of used batteries according to the manufacturer s instructions Attention Il y a danger d explosion s il y a remplacement incorrect de la batterie Remplacer uniquement avec une batterie du même type ou d un type équivalent recommandé par le constructeur M...

Page 5: ...tion of Conformity is available on request Please contact your sales representative Notice While reasonable efforts have been made to assure the accuracy of this document Motorola Inc assumes no liability resulting from any omissions in this document or from the use of the information obtained therein Motorola reserves the right to revise this document and to make changes from time to time in the ...

Page 6: ...d to in writing by Motorola Inc Use duplication or disclosure by the Government is subject to restrictions as set forth in subparagraph b 3 of the Rights in Technical Data clause at DFARS 252 227 7013 Nov 1995 and of the Rights in Noncommercial Computer Software and Documentation clause at DFARS 252 227 7014 Jun 1995 Motorola Inc Computer Group 2900 South Diablo Way Tempe Arizona 85282 ...

Page 7: ...ramming Interfaces 1 7 MC680X0 MPU 1 7 Data Bus Structure 1 7 EEPROMs on the MVME1X7P 1 8 MVME167 1 8 MVME177 1 9 Flash Memory on the MVME177 1 9 SRAM 1 10 Onboard SDRAM 1 11 Battery Backed Up RAM and Clock 1 12 VMEbus Interface 1 12 I O Interfaces 1 12 Serial Port Interface 1 13 Parallel Printer Interface 1 14 Ethernet Interface 1 15 SCSI Interface 1 16 Local Resources 1 16 Programmable Tick Time...

Page 8: ...Interrupt 1 47 Cache Coherency MVME167P 1 49 Cache Coherency MVME177P 1 50 Using Bus Timers 1 51 Indivisible Cycles 1 52 Supervisor Stack Pointer MC68060 1 53 Sources of Local Bus Errors 1 54 Local Bus Timeout 1 54 VMEbus Access Timeout 1 54 VMEbus BERR 1 54 VMEchip2 1 55 Bus Error Processing 1 55 Error Conditions 1 55 MPU Parity Error 1 56 MPU Offboard Error 1 56 MPU TEA Cause Unidentified 1 56 M...

Page 9: ...7 Reset Driver 2 18 Local Bus Interrupter and Interrupt Handler 2 18 Global Control and Status Registers 2 20 LCSR Programming Model 2 20 Programming the VMEbus Slave Map Decoders 2 26 VMEbus Slave Ending Address Register 1 2 28 VMEbus Slave Starting Address Register 1 2 28 VMEbus Slave Ending Address Register 2 2 29 VMEbus Slave Starting Address Register 2 2 29 VMEbus Slave Address Translation Ad...

Page 10: ...ster 3 2 44 Local Bus Slave VMEbus Master Attribute Register 2 2 45 Local Bus Slave VMEbus Master Attribute Register 1 2 46 VMEbus Slave GCSR Group Address Register 2 47 VMEbus Slave GCSR Board Address Register 2 48 Local Bus to VMEbus Enable Control Register 2 49 Local Bus to VMEbus I O Control Register 2 50 ROM Control Register 2 51 Programming the VMEchip2 DMA Controller 2 51 DMAC Registers 2 5...

Page 11: ...Register bits 8 15 2 83 Local Bus Interrupter Enable Register bits 0 7 2 84 Software Interrupt Set Register bits 8 15 2 85 Interrupt Clear Register bits 24 31 2 85 Interrupt Clear Register bits 16 23 2 86 Interrupt Clear Register bits 8 15 2 87 Interrupt Level Register 1 bits 24 31 2 87 Interrupt Level Register 1 bits 16 23 2 88 Interrupt Level Register 1 bits 8 15 2 88 Interrupt Level Register 1 ...

Page 12: ...ose Register 4 2 108 General Purpose Register 5 2 108 CHAPTER 3 PCCchip2 Introduction 3 1 Summary of Major Features 3 1 Functional Description 3 2 General Description 3 2 BBRAM Interface 3 3 82596CA LAN Controller Interface 3 3 MPU Port and MPU Channel Attention 3 3 MC68040 Bus Master Support for 82596CA 3 4 LANC Bus Error 3 4 LANC Interrupt 3 5 53C710 SCSI Controller Interface 3 6 Parallel Port I...

Page 13: ...e Interrupt Control Register 3 30 Modem PIACK Register 3 31 Transmit PIACK Register 3 32 Receive PIACK Register 3 33 LANC Error Status and Interrupt Control Registers 3 34 LANC Error Status Register 3 34 82596CA LANC Interrupt Control Register 3 35 LANC Bus Error Interrupt Control Register 3 36 Programming the SCSI Error Status and Interrupt Registers 3 37 SCSI Error Status Register 3 37 SCSI Inte...

Page 14: ...e or Greater Bit Error Cycle Type Non Burst Write 4 7 Single Bit Error Cycle Type Scrub 4 7 Double Bit Error Cycle Type Scrub 4 7 Triple or Greater Bit Error Cycle Type Scrub 4 7 Error Logging 4 8 Scrub 4 8 Refresh 4 8 Arbitration 4 9 Chip Defaults 4 9 Programming Model 4 10 Chip ID Register 4 13 Chip Revision Register 4 13 Memory Configuration Register 4 14 Base Address Register 4 15 DRAM Control...

Page 15: ... Bits 31 24 4 28 Error Address Bits 23 16 4 28 Error Address Bits 15 8 4 29 Error Address Bits 7 4 4 29 Error Syndrome Register 4 30 Defaults Register 1 4 30 Defaults Register 2 4 32 SDRAM Configuration Register 4 33 Initialization 4 34 Syndrome Decoding 4 36 APPENDIX A Summary of Changes Introduction A 1 APPENDIX B Printer and Serial Port Connections Introduction B 1 Connection Diagrams B 1 APPEN...

Page 16: ...xvi ...

Page 17: ...t with MVME712M B 2 Figure B 2 MVME1X7P Serial Port 1 Configured as DCE B 3 Figure B 3 MVME1X7P Serial Port 2 Configured as DCE B 4 Figure B 4 MVME1X7P Serial Port 3 Configured as DCE B 5 Figure B 5 MVME1X7P Serial Port 4 Configured as DCE B 6 Figure B 6 MVME1X7P Serial Port 1 Configured as DTE B 7 Figure B 7 MVME1X7P Serial Port 2 Configured as DTE B 8 Figure B 8 MVME1X7P Serial Port 3 Configured...

Page 18: ...xviii ...

Page 19: ...1 42 Table 1 14 TOD Clock Memory Map 1 43 Table 1 15 Single Cycle Instructions 1 52 Table 2 1 Features of the VMEchip2 ASIC 2 1 Table 2 2 VMEchip2 Memory Map LCSR Summary Sheet 1 of 2 2 22 Table 2 3 DMAC Command Packet Format 2 53 Table 2 4 Local Bus Interrupter Summary 2 75 Table 2 5 VMEchip2 Memory Map GCSR Summary 2 103 Table 3 1 PCCchip2 Devices Memory Map 3 10 Table 3 2 PCCchip2 Memory Map Co...

Page 20: ...xx ...

Page 21: ...ity to an existing compatible system or works in a lab environment for experimental purposes A basic knowledge of computers and digital logic is assumed To use this manual you may also wish to become familiar with the publications listed in Appendix C Related Documentation Model Number Characteristics MVME167PA 24SE 25MHz MC68040 16MB SDRAM SCSI and Ethernet MVME167PA 25SE 25MHz MC68040 32MB SDRAM...

Page 22: ...bes the ECC DRAM controller ASIC MCECC On the MVME1X7P boards it supplies the interface to a 144 bit wide DRAM memory system Appendix A Summary of Changes lists the modifications that accompanied the introduction of the Petra ASIC on the MVME167P and MVME177P Appendix B Printer and Serial Port Connections contains drawings of the printer and serial port interface connections available with the MVM...

Page 23: ... Used in This Manual The following typographical conventions are used in this document Unless otherwise specified all address references are in hexadecimal An asterisk following the signal name for signals which are level significant denotes that the signal is true or valid when the signal is low An asterisk following the signal name for signals which are edge significant denotes that the actions ...

Page 24: ...ol key Execute control characters by pressing the Ctrl key and the letter simultaneously for example Ctrl d In this manual assertion and negation are used to specify forcing a signal to a particular state In particular assertion and assert refer to a signal that is active or true negation and negate indicate a signal that is inactive or false These terms are used independently of the voltage level...

Page 25: ...that enables the function it controls The term false is used to indicate that the bit is in the state that disables the function it controls In all tables the terms 0 and 1 are used to describe the actual value that should be written to the bit or the value that it yields when read The term status bit is used to describe a bit in a register that reflects a specific condition The status bit can be ...

Page 26: ...xxvi ...

Page 27: ...e chapters devoted to those devices Note The MVME1X7P s new Petra ASIC performs the functions previously implemented in the MCECC chip For ease of use in conjunction with programming models and documentation developed for earlier boards however the structure of this manual preserves the functional distinctions that formerly characterized the MCECC ASIC The Petra ASIC and Second Generation MVME1X7 ...

Page 28: ...e MCECC ASICs used on the MVME167 177 This Programmer s Reference Guide describes the MCECC model in Chapter 4 In the MVME167 177 application there is logic on the Petra chip to prevent you from inadvertently enabling the MC memory controller model The same SDRAM memory array serves both controller models The SDRAM array is 32 data bits wide with 7 checkbits The array architecture is a non interle...

Page 29: ...ace of DRAM Up to 64MB SDRAM is available on MVME167P boards up to 128MB is available on MVME177P boards SRAM 128KB SRAM with battery backup EPROM Four 44 pin JEDEC standard PLCC EPROM sockets Two 44 pin JEDEC standard PLCC EPROM sockets Flash Not available Four Intel 28F008SA Flash memory devices with optional write protection NVRAM and RTC 8K by 8 Non Volatile RAM NVRAM and Real Time Clock RTC w...

Page 30: ...em controller functions VMEbus to local bus interface A32 A24 D32 D16 D8 Local bus to VMEbus interface A16 A24 A32 D8 D16 D32 Programmable interrupter and interrupt handler Global Control Status register for interprocessor communications DMA capability for fast local memory VMEbus transfers A16 A24 A32 D16 D32 D16 D32 D64 BLT Switches Two pushbutton switches ABORT and RESET Status Indicators Eight...

Page 31: ...face EPROM 4 44 pin PLCC 53C710 SCSI Compressor CD2401 Quad Serial I O Controller Centronics Compatible Parallel I O 128KB SRAM Battery Option PETRA Mezzanine Connectors M48T58 Battery Backed 8KB RAM Clock PCCCHIP 2 P2 Up to 128MB ECC DRAM i82696CA Ethernet Controller P1 Port 25 33MHZ MC68040 MPU 16 64MB ECC SDRAM Memory Array ...

Page 32: ...ce EPROM 2 44 pin PLCC 53C710 SCSI Compressor CD2401 Quad Serial I O Controller Centronics Compatible Parallel I O 128KB SRAM Battery Option 4MB FLASH PETRA Mezzanine Connectors M48T58 Battery Backed 8KB RAM Clock PCCCHIP 2 P2 Up to 128MB ECC DRAM i82696CA Ethernet Controller P1 Port 50 60MHZ MC68040 MPU 16 128MB ECC SDRAM Memory Array ...

Page 33: ...to the MC68040 and MC68060 user s manuals for more information Both models are available in various versions with the features listed in Table 1 1 on page 1 3 Data Bus Structure The local bus for all single board computers described in this manual is a 32 bit synchronous bus which is based on an MC68040 compatible bus and which supports burst transfers Throughout this manual this bus is referred t...

Page 34: ...E167P boards use 27C102JK or 27C202JK type EEPROMs The MVME177 boards use SGS Thompson M27C4002 256K x 16 or AMD 27C4096 type EEPROMs The EEPROMs are organized as 32 bit wide banks that support 8 16 and 32 bit read accesses The MVME177 has Flash memory in addition to EEPROM MVME167 The EEPROMs are mapped to Local Bus address 0 following a Local Bus reset This allows the MC68040 to access the stack...

Page 35: ...008SA Flash memory devices The 32 bit wide Flash can support 8 16 and 32 bit accesses The Flash can be used for the onboard debugger firmware which can be downloaded from I O resources such as Ethernet SCSI serial port or VMEbus Flash write protection is programmable by setting a control bit GPIO bit 1 in the VMEchip2 GPIO register after downloading When the Flash memory is used with EEPROM only t...

Page 36: ...r mezzanines The SRAM is under the control of the VMEchip2 ASIC and the access time is programmable Refer to Chapter 2 VMEchip2 for more detail The MVME177P provides for SRAM battery backup The battery backup function is supplied by a Dallas DS1210S nonvolatile controller chip and Panasonic 2032 or equivalent battery FFBFFFFF FF800000 MAP 1 MAP 2 as shipped MAP 3 FLASH MEMORY 4MB FLASH BOTTOM 2MB ...

Page 37: ...RAM In addition to the onboard SDRAM an additional mezzanine of the type used on previous MVME1X7 boards can be plugged in to provide up to 128MB of additional DRAM All DRAM has ECC protection The SDRAM map decoder can be programmed to accommodate different base address es and sizes of mezzanine boards The onboard SDRAM is disabled by a Local Bus reset it must be programmed in order for you to acc...

Page 38: ...imers A watchdog timer Programmable map decoders for the master and slave interfaces A VMEbus to from local bus DMA controller A VMEbus to from local bus non DMA programmed access interface A VMEbus interrupter a VMEbus system controller a VMEbus interrupt handler and a VMEbus requester Processor to VMEbus transfers can be D8 D16 or D32 VMEchip2 DMA transfers to the VMEbus however can be D16 D32 D...

Page 39: ... for drawings of the serial port interface connections All four serial ports use EIA 232 D drivers and receivers located on the main board and all the signal lines are routed to the I O connector The configuration headers are located on the main board and may be on some transition boards An external I O transition board is necessary to convert the I O connector pinout to industry standard connecto...

Page 40: ...w level high to low transition or low to high transition This port may be used as a Centronics compatible parallel printer port or as a general parallel I O port When used as a parallel printer port the five status pins function as Printer Acknowledge ACK Printer Fault FAULT Printer Busy BSY Printer Select SELECT and Printer Paper Error PE while the control pins act as Printer Strobe STROBE and In...

Page 41: ...dress displayed on a label attached to the VMEbus P2 connector In addition the six bytes including the Ethernet address are stored in the configuration area of the BBRAM That is 0001AFxxxxxx is stored in the BBRAM At an address of FFFC1F2C the upper four bytes 0001AFxx can be read At an address of FFFC1F30 the lower two bytes xxxx can be read Refer to the BBRAM TOD Clock memory map description in ...

Page 42: ...SCSI bus ends at the adapter board termination resistors must be installed on the adapter board 5V power to the SCSI bus TERM power line and termination resistors is supplied through a fuse located on the adapter board in the case of the MVME167P or through a fuse on the MVME712 series transition module and a diode on the adapter board in the case of the MVME177P Local Resources The MVME167P and M...

Page 43: ...2 VMEchip2 for detailed programming information Local Bus Timeout The MVME167P and MVME177P single board computers provide a timeout function in the VMEchip2 ASIC for the Local Bus When the timer is enabled and a Local Bus access times out a Transfer Error Acknowledge TEA signal is sent to the Local Bus master The time out value is selectable by software for 8 µsec 64 µsec 256 µsec or infinite The...

Page 44: ...ther the upper or lower Flash addresses are used in shared EPROM Flash mode GPIO0 s function as 12V power status signal is unchanged Petra VMEchip2 Redundant Logic In support of possible future configurations in which the MVME1X7P might be offered as a single board computer without the VMEbus interface certain logic in the VMEchip2 has been duplicated in the Petra chip Table 1 2 shows the location...

Page 45: ... switch is wired to the Petra chip not the VMEchip2 7 The SRAM and EPROM decoder in the VMEchip2 version 2 must be disabled by software before any accesses are made to these address spaces Table 1 2 Functions Duplicated in VMEchip2 and Petra ASICs VMEchip2 Petra Chip Notes Address Bit Address Bit FFF40060 28 24 FFF42044 28 24 1 5 FFF40060 22 19 17 16 FFF42044 22 19 17 16 2 5 FFF4004C 13 8 FFF42044...

Page 46: ...ve multiple MVME1X7P modules on the same VMEbus with different virtual local bus maps as viewed by different VMEbus masters Local Bus Memory Map The local bus memory map is split into different address spaces by the transfer type TT signals The local resources respond to the normal access and interrupt acknowledge codes Normal Address Range The following tables show the memory maps of devices that...

Page 47: ...0 is set to 1 after each reset The ROM0 bit must be cleared before other resources DRAM or SRAM can be mapped in this range Table 1 3 Local Bus Memory Map Address Range Devices Accessed Port Size Size Software Cache Inhibit Notes 00000000 DRAMSIZE User Programmable Onboard SDRAM D32 DRAMSIZE N 1 2 DRAMSIZE FF7FFFFF User Programmable VMEbus D32 D16 3GB 3 4 FF800000 FFBFFFFF ROM 167P D32 4MB N 1 EPR...

Page 48: ...erminated by a TEA signal 6 The Flash and EEPROM configuration is jointly controlled by a configuration switch S4 as described in Chapters 1 and 4 of MVME177P Single Board Computer Installation and Use and by control bit GPIO2 in the VMEchip2 ASIC as described in Chapter 2 VMEchip2 Depending on the setting of S4 this address space may reference 2MB EPROM 1MB EPROM and 2MB Flash or 4MB Flash Table ...

Page 49: ...2 4KB 1 8 FFF47000 FFF47FFF 53C710 SCSI D32 D8 4KB 1 FFF48000 FFF4FFFF Reserved 32KB 5 FFF50000 FFF6FFFF Reserved 128KB 5 FFF70000 FFF76FFF Reserved 28KB 6 FFF77000 FFF77FFF Reserved 4KB 2 FFF78000 FFF7EFFF Reserved 28KB 6 FFF7F000 FFF7FFFF Reserved 4KB 2 FFF80000 FFF9FFFF Reserved 128KB 6 FFFA0000 FFFBFFFF Reserved 128KB 5 FFFC0000 FFFCFFFF M48T58 BBRAM TOD Clock D32 D8 64KB 1 FFFD0000 FFFDFFFF R...

Page 50: ...bus timer is enabled the access times out and is terminated by a TEA signal 4 Writes to the LCSR in the VMEchip2 must be 32 bits LCSR writes of 8 or 16 bits terminate with a TEA signal Writes to the GCSR may be 8 16 or 32 bits Reads to the LCSR and GCSR may be 8 16 or 32 bits 5 This area does not return an acknowledge signal If the local bus timer is enabled the access times out and is terminated ...

Page 51: ...chips listed above by contacting your local Motorola sales representative A non disclosure agreement may be necessary VMEchip2 Table 1 5 PCCchip 2 Table 1 7 Printer Table 1 6 MCECC Internal Register Table 1 8 Cirrus Logic CD2401 Serial Port Table 1 9 82596CA Ethernet LAN chip Table 1 10 53C710 SCSI chip Table 1 11 M48T58 BBRAM TOD Clock Table 1 12 BBRAM Configuration Area Table 1 13 TOD Clock Tabl...

Page 52: ... ADDRESS 4 MASTER ADDRESS TRANSLATION ADDRESS 4 VMEchip2 LCSR Base Address FFF40000 OFFSET 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 MAST D16 EN MAST WP EN MAST D16 EN MAST WP EN MASTER AM 3 MASTER AM 4 GCSR GROUP SELECT GCSR BOARD SELECT MAST 4 EN MAST 3 EN MAST 2 EN MAST 1 EN TICK 2 1 TICK IRQ 1...

Page 53: ...E ADDRESS TRANSLATION SELECT 1 SLAVE ADDRESS TRANSLATION SELECT 2 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 IO2 EN IO2 WP EN IO2 S U IO2 P D IO1 EN IO1 D16 EN IO1 WP EN IO1 S U 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 MASTER AM 2 MASTER AM 1 ROM SIZE ROM BANK B SPEED ROM BANK A SPEED DMA TBL INT DMA LB SNP MODE DMA INC VME DMA INC LB DMA D64 BLK DMA BLK DMA AM 5 DMA ...

Page 54: ...E IRQ IRQ1E IRQ TIC2 IRQ TIC1 IRQ VME IACK IRQ DMA IRQ SIG3 IRQ SIG2 IRQ SIG1 IRQ SIG0 IRQ LM1 IRQ LM0 IRQ ABORT IRQ LEVEL SYS FAIL IRQ LEVEL MST WP ERROR IRQ LEVEL VME IACK IRQ LEVEL DMA IRQ LEVEL SIG 3 IRQ LEVEL SIG 2 IRQ LEVEL SW7 IRQ LEVEL SW6 IRQ LEVEL SW5 IRQ LEVEL SW4 IRQ LEVEL SPARE IRQ LEVEL VME IRQ 7 IRQ LEVEL VME IRQ 6 IRQ LEVEL VME IRQ 5 IRQ LEVEL VECTOR BASE REGISTER 0 VECTOR BASE REG...

Page 55: ... IRQ 0 CLR IRQ 15 CLR IRQ 14 CLR IRQ 13 CLR IRQ 12 CLR IRQ 11 CLR IRQ 10 CLR IRQ 9 CLR IRQ 8 SET IRQ 15 SET IRQ 14 SET IRQ 13 SET IRQ 12 SET IRQ 11 SET IRQ 10 SET IRQ 9 SET IRQ 8 SW7 IRQ SW6 IRQ SW5 IRQ SW4 IRQ SW3 IRQ SW2 IRQ SW1 IRQ SW0 IRQ SPARE VME IRQ7 VME IRQ6 VME IRQ5 VME IRQ4 VME IRQ3 VME IRQ2 VME IRQ1 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 GPIOO P ERROR IRQ LEVEL IRQ1E IRQ LEVEL TIC TIMER ...

Page 56: ...0 0 Chip Revision Chip ID 2 4 L M 3 L M 2 L M 1 L M 0 S I G 3 S I G 2 S I G 1 S I G 0 R S T I S F BF S C O N SYS FL X X X 4 8 General Purpose Control and Status register 0 6 C General Purpose Control and Status register 1 8 10 General Purpose Control and Status register 2 A 14 General Purpose Control and Status register 3 C 18 General Purpose Control and Status register 4 E 1C General Purpose Cont...

Page 57: ...rol Register FFF42032 BIT 15 14 13 12 11 10 9 8 NAME PLTY E L INT IEN ICLR IL2 IL1 IL0 Printer PE Interrupt Control Register FFF42033 BIT 7 6 5 4 3 2 1 0 NAME PLTY E L INT IEN ICLR IL2 IL1 IL0 Printer BUSY Interrupt Control Register FFF42034 BIT 31 30 29 28 27 26 25 24 NAME PLTY E L INT IEN ICLR IL2 IL1 IL0 Printer Input Status Register FFF42036 BIT 15 14 13 12 11 10 9 8 NAME PLTY ACK FLT SEL PE B...

Page 58: ... PLTY D16 D23 D24 D31 CHIP ID CHIP REVISION TIC TIMER 1 TIC TIMER 1 TIC TIMER 2 TIC TIMER 2 PRESCALER COUNT REGISTER PRESCALER CLOCK ADJUST GPI E L GPI INT GPI IEN GPI ICLR GPI IRQ LEVEL GPI GPOE GPO SCC PAR ERR SCC EXT ERR SCC LTO ERR SCC SCLR SCC MDM ERR SCC MDM IEN SCC MDM AVEC SCC MODEM IRQ LEVEL SCC TRANSMIT PIACK LAN PAR ERR LAN EXT ERR LAN LTO ERR LAN SCLR SCSI PAR ERR SCSI EXT ERR SCSI LTO...

Page 59: ...C EN 2 TIC2 IEN TIC2 ICLR TIC1 INT TIC1 IEN TIC1 ICLR SCC TX IRQ SCC TX IEN SCC TX AVEC SCC SC1 SCC SC0 SCC RX IRQ SCC RX IEN SCC RX AVEC SCC MODEM PIACK LAN INT E L LAN INT LAN IEN LAN ICLR LAN INT IRQ LEVEL PRTR SEL PLTY PRTR SEL E L PRTR SEL INT PRTR SEL IEN PRTR SEL ICLR PRTR ANY INT PRTR ACK PRTR FLT PRTR SEL PRTR PE PRTR BSY PRTR SEL IRQ LEVEL PRINTER DATA LAN SC1 LAN SC0 LAN ERR INT LAN ERR...

Page 60: ...ONTROL BAD23 BAD22 RWB5 SWAI T RWB3 NCEIE N NCEB EN RAMEN 1C BCLK FREQUENCY BCK7 BCK6 BCK5 BCK4 BCK3 BCK2 BCK1 BCK0 20 DATA CONTROL 0 0 DERC ZFILL RWCKB 0 0 0 24 SCRUB CONTROL RACO DE RADA TA HITDI S SCRB SCRBEN 0 SBEIE N IDIS 28 SCRUB PERIOD SBPD1 5 SBPD1 4 SBPD1 3 SBPD 12 SBPD11 SBPD1 0 SBPD9 SBPD8 2C SCRUB PERIOD SBPD7 SBPD6 SBPD5 SBPD 4 SBPD3 SBPD2 SBPD1 SBPD0 30 CHIP PRESCALE CPS7 CPS6 CPS5 C...

Page 61: ...E SBE 60 ERROR ADDRESS EA31 EA30E EA29 EA28 EA27 EA26 EA25 EA24 64 ERROR ADDRESS EA23 EA22 EA21 EA20 EA19 EA18 EA17 EA16 68 ERROR ADDRESS EA15 EA14 EA13 EA12 EA11 EA10 EA9 EA8 6C ERROR ADDRESS EA7 EA6 EA5 EA4 0 0 0 0 70 ERROR SYNDROME S7 S6 S5 S4 S3 S2 S1 S0 74 DEFAULTS1 WRHDI S STATC OL FSTR D SELI1 SELI0 RSIZ2 RSIZ1 RSIZ0 78 DEFAULTS2 FRC_O PN XY_FL IP REFDI S TVEC T NOCAC HE RESST 2 RESST 1 RES...

Page 62: ...OR1 10 B R W Channel Option Register 2 COR2 17 B R W Channel Option Register 3 COR3 16 B R W Channel Option Register 4 COR4 15 B R W Channel Option Register 5 COR5 14 B R W Channel Option Register 6 COR6 18 B R W Channel Option Register 7 COR7 07 B R W Special Character Register 1 SCHR1 1F B R W Async Special Character Register 2 SCHR2 1E B R W Async Special Character Register 3 SCHR3 1D B R W Asy...

Page 63: ...OR C0 B R W Channel Command and Status Registers Channel Command Register CCR 13 B R W Special Transmit Command Register STCR 12 B R W Channel Status Register CSR 1A B R Modem Signal Value Registers MSVR RTS DE B R W MSVR DTR DF B R W Interrupt Registers Local Interrupt Vector Register LIVR 09 B R W Interrupt Enable Register IER 11 B R W Local Interrupting Channel Register LICR 26 B R W Stack Regi...

Page 64: ...upt Register TEOIR 85 B W Modem Interrupt Registers Modem Priority Interrupt Level Register MPILR E3 B R W Modem Interrupt Register MIR EF B R Modem Timer Interrupt Status Register MISR 8B B R Modem End Of Interrupt Register MEOIR 86 B W DMA Registers DMA Mode Register write only DMR F6 B W Bus Error Retry Count BERCNT 8E B R W DMA Buffer Status DMABSTS 19 B R DMA Receive Registers A Receive Buffe...

Page 65: ...per BTBADRU 54 W R W A Transmit Buffer Byte Count ATBCNT 5A W R W B Transmit Buffer Byte Count BTBCNT 58 W R W A Transmit Buffer Status ATBSTS 5F B R W B Transmit Buffer Status BTBSTS 5E B R W Transmit Current Buffer Address Lower TCBADRL 3A W R Transmit Current Buffer Address Upper TCBADRU 38 W R Timer Registers Timer Period Register TPR DA B R W Receive Time out Period Register RTPR 24 W R W Asy...

Page 66: ...on Pointer must be upper word first lower word second General Timer 1 low GT1l 2B B R Sync General Timer 1 high GT1h 2A B R Sync General Timer 2 GT2 29 B R Sync Transmit Timer Register TTR 29 B R Async Table 1 10 82596CA Ethernet LAN Memory Map 82596CA Ethernet LAN Directly Accessible Registers Data Bits Address D31 D16 D15 D0 FFF46000 Upper Command Word Lower Command Word FFF46004 MPU Channel Att...

Page 67: ... data The second area is used by Motorola networking software The third area may be used by an operating system The fourth area is Table 1 11 53C710 SCSI Memory Map Base Address is FFF47000 Big Endian Mode 53C710 Register Address Map SCRIPTs Mode and Little Endian Mode 00 SIEN SDID SCNTL1 SCNTL0 00 04 SOCL SODL SXFER SCID 04 08 SBCL SBDL SIDL SFBR 08 0C SSTAT2 SSTAT1 SSTAT0 DSTAT 0C 10 DSA 10 14 C...

Page 68: ...rking Area 256 FFFC1100 FFFC16F7 Operating System Area 1528 FFFC16F8 FFFC1EF7 Debugger Area 2048 FFFC1EF8 FFFC1FF7 Configuration Area 256 FFFC1FF8 FFFC1FFF TOD Clock 8 Table 1 13 BBRAM Configuration Area Memory Map Address Range Description Size Bytes FFFC1EF8 FFFC1EFB Version 4 FFFC1EFC FFFC1F07 Serial Number 12 FFFC1F08 FFFC1F17 Board ID 16 FFFC1F18 FFFC1F27 PWA 16 FFFC1F28 FFFC1F2B Speed 4 FFFC...

Page 69: ...WB 8 FFFC1F56 FFFC1F5D Mezz Board 2 Serial Number 8 FFFC1F5E FFFC1FF6 Reserved 153 FFFC1FF7 Checksum 1 Table 1 14 TOD Clock Memory Map Address Data Bits Function D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 FFFC1FF8 W R S Calibration Control FFFC1FF9 ST Seconds 00 FFFC1FFA x Minutes 00 FFFC1FFB x x Hour 00 FFFC1FFC x FT x x x Day 01 FFFC1FFD x x Date 01 FFFC1FFE x x x Month 01 FFFC1FFF Year 00 Table 1 13 BBRAM...

Page 70: ...rs and the last two bytes being the minor version numbers For example if the version of this structure is 1 0 this field contains 0100 2 Twelve bytes are reserved for the serial number of the board in ASCII format For example this field could contain 000000470476 3 Sixteen bytes are reserved for the board ID in ASCII format For example for a 16 MB 25 MHz MVME167 board this field contains MVME167P ...

Page 71: ...is stored in ASCII format 9 Eight bytes are reserved for the systems serial ID for boards used in a system 10 Eight bytes are reserved for the printed wiring board PWB number assigned to the first mezzanine board in ASCII format This does not include the 01 W prefix For example for a 16MB parity mezzanine at revision E the PWB field contains 3690B03E 11 Eight bytes are reserved for the serial numb...

Page 72: ... is being acknowledged using TM2 TM0 The interrupt handler selects which device within that level is being acknowledged VMEbus Memory Map This section describes the mapping of local resources as viewed by VMEbus masters Default addresses for the slave master and GCSR address decoders are provided by the ENV command VMEbus Accesses to the Local Bus The VMEchip2 includes a user programmable map deco...

Page 73: ...istinguishes interrupt acknowledge cycles from other cycles by placing the binary value 11 on TT1 TT0 It also specifies the level that is being acknowledged using TM2 TM0 The interrupt handler selects which device within that level is being acknowledged Example VMEchip2 Tick Timer 1 Periodic Interrupt This section describes the use of interrupts on MVME167P and MVME177P single board computers The ...

Page 74: ...o to clear the register 4 Tick Timer 1 Control register FFF40060 8 bits Write 07 to this register set bits 0 1 and 2 This enables the Tick Timer 1 counter to increment resets the count to zero on compare and clears the overflow counter Step Register and Address Action and Reference 5 Vector Base register FFF40088 8 of 32 bits If not already initialized by the debugger set Interrupt Base register 0...

Page 75: ... following features 1 Be sure the MC680x0 Vector Base register is set up Set the proper MC680x0 exception vector location so the processor vectors to your interrupt handler location You can determine the proper exception vector location to set from the MC680x0 Vector Base register the VMEchip2 Base register and Table 2 4 Local Bus Interrupter Summary in Chapter 2 from which you can determine the a...

Page 76: ...xternal memory systems To maintain cache coherency the MC68060 provides automatic snoop invalidation when it is not the bus master When an external cycle is marked as snoopable the bus snooper checks the caches and invalidates the matching data Unlike the MC68040 the MC68060 cannot source or sink cache data during alternate bus master accesses Therefore the MVME177 uses a single snoop control line...

Page 77: ...hort such as the time to access onboard memory Therefore it is recommended this timer be set to a small value such as 8 µsec The next timer to take over when one single board computer accesses another is the VMEbus access timer This measures the time from when the VMEbus has been address decoded and hence a VMEbus request has been made to when VMEbus mastership has been granted Because experience ...

Page 78: ...is given This translates into a DTACK signal on the VMEbus which is then translated into a TA signal to the first requesting processor and the transfer is complete If the VMEbus global timer expires on a legitimate transfer the VMEbus to Local Bus controller in the VMEchip2 may become confused and the VMEchip2 may misbehave Therefore the bus timer values must be set correctly The correct settings ...

Page 79: ...M68000 based systems aligned CAS and all TAS cycles are always single address RMW operations while misaligned CAS and CAS2 operations and operations in the MMU can be multiple address RMW cycles The VMEbus does not support multiple address RMW cycles and there is no defined protocol for supporting multiple address RMW cycles that start onboard and then access offboard resources Because it is not p...

Page 80: ... only happen if software accesses a non existent location within the onboard address range VMEbus Access Timeout A VMEbus Access Timeout occurs whenever a VMEbus bound transfer does not receive a VMEbus bus grant within the programmed time This is usually caused by another bus master holding the bus for an excessive period of time VMEbus BERR A VMEbus BERR occurs when the BERR signal line is asser...

Page 81: ...an interrogate the status bits and proceed with the result However an interrupt may occur during the execution of the bus error handler before an instruction can write to the status register to raise the interrupt mask If the interrupt service routine causes a second bus error the status that indicates the source of the first bus error may be lost Application software must take this possibility in...

Page 82: ... MPU was attempting to access an offboard resource MPU Notification TEA is asserted during offboard access Status Bit 8 of the MPU Status and DMA Interrupt Count register Address FFF40048 Comments This can be caused by a VMEbus timeout a VMEbus BERR or a single board computer VMEbus access timeout The latter is the time from when the VMEbus has been requested to when it is granted Description An e...

Page 83: ...e Otherwise it indicates a hardware problem Description The DMAC experienced a VMEbus error during an attempted transfer MPU Notification DMAC interrupt when enabled Status The VME bit is set in the DMAC Status register address FFF40048 bit 1 Comments This indicates the DMAC attempted to access a VMEbus address at which there was no resource or the VMEbus slave returned a BERR signal Description P...

Page 84: ...with a Local Bus address that maps to the VMEbus If the TBL bit is set address FFF40048 bit 2 the error occurred during a command table access otherwise the error occurred during a data access Description A Local Bus time out LTO occurred while the DMAC was Local Bus master MPU Notification DMAC interrupt when enabled Status The DLTO bit is set in the DMAC Status register address FFF40048 bit 3 Co...

Page 85: ...le access otherwise the error occurred during a data access Description Local Bus Retry occurred due to VMEbus Dual Port Lock or LAN wanted Bus while the SCC was Local Bus master MPU Notification SCC Transmit Interrupt or SCC Receive Interrupt Status SCC Transmit Interrupt Status register SCC Transmit Current Buffer Address register SCC Receive Interrupt Status register High SCC Receive Current Bu...

Page 86: ...ter PCCchip2 SCC Error Status register FFF4201C Comments SCC Transmit and Receive interrupt enables are controlled in the SCC and in the PCCchip2 Description Error encountered while the SCC was attempting to go to the VMEbus MPU Notification SCC Transmit Interrupt or SCC Receive Interrupt Status SCC Transmit Interrupt Status register SCC Transmit Current Buffer Address register SCC Receive Interru...

Page 87: ...the PCCchip2 Description Parity error while the LANCE was reading DRAM MPU Notification PCCchip2 Interrupt LAN ERROR IRQ Status PCCchip2 LAN Error Status register FFF42028 Comments The LANCE has no ability to respond to TEA so the error interrupt and status are provided in the PCCchip2 Control for the interrupt is in the PCCchip2 LAN Error Interrupt Control register FFF4202B Description Error enco...

Page 88: ...AN Error Interrupt Control register FFF4202B Description Parity error detected while the 53C710 was reading DRAM MPU Notification 53C710 Interrupt Status 53C710 DMA Status register 53C710 DMA Interrupt Status register PCCchip2 SCSI Error Status register FFF4202C Comments 53C710 interrupt enables are controlled in the 53C710 and in the PCCchip2 Description Error encountered while the 53C710 was att...

Page 89: ...cal Bus Time out occurred while the 53C710 was Local Bus master MPU Notification 53C710 Interrupt Status 53C710 DMA Status register 53C710 DMA Interrupt Status register PCCchip2 SCSI Error Status register FFF4202C Comments 53C710 interrupt enables are controlled in the 53C710 and in the PCCchip2 ...

Page 90: ...1 64 Computer Group Literature Center Web Site Programming Issues 1 ...

Page 91: ...IC Table 2 1 Features of the VMEchip2 ASIC Function Features Local Bus to VMEbus Interface Programmable local bus map decoder Programmable short standard and extended VMEbus addressing Programmable AM codes Programmable 16 bit and 32 bit VMEbus data width Software enabled write posting mode Write post buffer one cache line or one four byte Automatically performs dynamic bus sizing for VMEbus cycle...

Page 92: ...MEbus data width Programmable short standard and extended VMEbus addressing Programmable AM code Programmable local bus snoop enable 16 four byte FIFO data buffer Up to 4 GB of data per DMA request Automatically adjustment of transfer size to optimize bus utilization DMA complete interrupt DMAC command chaining supported by a singly linked list of DMA commands VMEbus DMA controller requester with ...

Page 93: ...on monitors Global control of locally detected failures Global control of local reset Four global attention interrupt bits A chip ID and revision register Four 16 bit dual ported general purpose registers Interrupt Handler All interrupts level programmable All interrupts maskable All interrupts providing a unique vector Software and external interrupts Watchdog timer Control and status bits 4 bit ...

Page 94: ...A16 A24 A32 Data transfer capabilities D08 D16 D32 The local bus slave includes six local bus map decoders for accessing the VMEbus The first four map decoders are general purpose programmable decoders while the other two are fixed and are dedicated for I O decoding The first four map decoders compare local bus address lines A31 through A16 with a 16 bit start address and a 16 bit end address When...

Page 95: ...DMA CONTROL DATA CONTROL ADDRESS CONTROL DATA CONTROL CONTROL DATA CONTROL ADDRESS DATA CONTROL ADDRESS DATA CONTROL ADDRESS DATA CONTROL ADDRESS DATA CONTROL ADDRESS LOCAL BUS LOCAL BUS SLAVE FIFO VMEBUS MASTER VMEBUS DATA DATA DATA DATA DATA DATA CONTROL CONTROL CONTROL CONTROL CONTROL CONTROL CONTROL CONTROL FIFO ADDRESS CONTROL FIFO GCSR DATA CONTROL ADDRESS DATA CONTROL ADDRESS CONTROL LOCAL ...

Page 96: ...r one cache line four quad bytes form Write posting should only be enabled when bus errors are not expected If a bus error is returned on a write posted cycle and the interrupt is enabled the local processor is interrupted The address of the error is not saved Normal memory never returns a bus error on a write cycle However some VMEbus ECC memory cards perform a read modify write operation and the...

Page 97: ...rror signal after 64 µs 1 ms or 32 ms The VMEchip2 includes a software controlled VMEbus write post timer It starts ticking when a data transfer to the VMEbus is write posted The timer stops ticking once the chip has started the data transfer on the VMEbus If this does not happen before the timer times out the chip aborts the write posted cycle and sends an interrupt to the local bus interrupter I...

Page 98: ...operation is complete the DWB pin is negated the DWB bit in the LCSR is negated and the bus is not being held by a lock cycle The requester releases the bus as follows 1 When the chip is configured in release when done RWD mode the requester releases the bus when the above conditions are satisfied 2 When the chip is configured in release on request ROR mode the requester releases the bus when the ...

Page 99: ...rite transfer by asserting DTACK The chip then requests control of the local bus and independently accesses the local resource after it has been granted the local bus The write posting pipeline is two deep in non block transfer mode and 16 deep in block transfer mode To significantly improve the access time of the slave when it responds to a VMEbus block read cycle the VMEchip2 contains a 16 four ...

Page 100: ...tion with the local bus master the VMEbus master and a 16 four byte FIFO buffer The DMA controller has a 32 bit local address counter 32 bit table address counter a 32 bit VMEbus address counter a 32 bit byte counter and control and status registers The Local Control and Status register LCSR provides software with the ability to control the operational modes of the DMAC Software can program the DM...

Page 101: ...se the DMAC automatically adjusts the size of individual data transfers until 64 bit transfers D64 BLT mode 32 bit transfers D32 mode or 16 bit transfers D16 mode can be executed Based on the address of the first byte the DMAC transfers single bytes double bytes or a mixture of both and then continues to execute transfer cycles based on the programmed data width Based on the address of the last by...

Page 102: ... the bus maintain mastership for a specific amount of time and then after relinquishing it refrain from requesting it for another specific amount of time No Address Increment DMA Transfers During normal memory to memory DMA transfers the DMA controller is programmed to increment the local bus and VMEbus address This allows a block of data to be transferred between VMEbus memory and local bus memor...

Page 103: ... are used to define the transfer size and byte lanes During D16 transfers the VMEbus address line VA 1 toggles If the VMEbus port size is D64 then VA 2 1 LWORD and DS 1 0 are used to define the transfer size and byte lanes Local bus address LA 3 0 and SIZ 1 0 are used to define the transfer size and byte lanes on local bus During local bus transfers LA 3 2 count The DMA controller internally incre...

Page 104: ...ation process the DMAC requester executes an early release of the bus If it is about to release the bus and it is executing a VMEbus cycle the requester releases BBSY before its associated VMEbus master completes the cycle This allows the arbiter to arbitrate any pending requests and grant the bus to the next requester at the same time that the DMAC completes its cycle Tick and Watchdog Timers The...

Page 105: ...tick timer interrupt is enabled by the local bus interrupter The overflow counter can be cleared by writing a 1 to the overflow clear bit Tick timer 1 or 2 can be programmed to generate a pulse on the VMEbus IRQ1 interrupt line at the tick timer period This provides a broadcast interrupt function which allows several VME boards to receive an interrupt at the same time In certain applications this ...

Page 106: ...d environment The VMEbus interrupter has an additional feature not defined in the VMEbus specification The VMEchip2 supports a broadcast mode on the IRQ1 signal line When this feature is used the normal IRQ1 interrupt to the local bus interrupter should be disabled and the edge sensitive IRQ1 interrupt to the local bus interrupter should be enabled All boards in the system which are not participat...

Page 107: ...bitration timer preventing a bus lockup when no requester assumes control of the bus after the arbiter has issued a grant Using a control bit this timer can be enabled or disabled When enabled it assumes control of the bus by driving the BBSY signal after 256 µsecs releasing it after satisfying the requirements of the VMEbus specification and then re arbitrating any pending bus requests IACK Daisy...

Page 108: ...p reset a watch dog timeout or by a control bit in the LCSR SYSRESET remains asserted for at least 200 msec as required by the VMEbus specification Similarly the chip provides an input signal and a control bit to initiate a local reset operation The local reset driver is enabled even when the chip is not the system controller A local reset may be generated by the RESET switch a power up reset a wa...

Page 109: ... When this interrupt is acknowledged the vector is provided by the VMEchip2 and a VMEbus interrupt acknowledge is not generated When this interrupt is enabled the VMEbus IRQ1 level sensitive interrupter should be disabled The VMEchip2 VMEbus interrupter acknowledge interrupter is an edge sensitive interrupter connected to the acknowledge output of the VMEbus interrupter An interrupt is generated w...

Page 110: ...C includes a set of registers that are accessible from both the VMEbus and the local bus These registers are provided to aid in interprocessor communications over the VMEbus These registers are fully described in a later section LCSR Programming Model This section defines the programming model for the Local Control and Status registers LCSR in the VMEchip2 ASIC The local bus map decoder for the LC...

Page 111: ...s bit is a read only status bit R W This bit is readable and writable W AC This bit can be set and it is automatically cleared This bit can also be read C Writing a 1 to this bit clears this bit or another bit This bit reads 0 S Writing a 1 to this bit sets this bit or another bit This bit reads 0 P The bit is affected by powerup reset S The bit is affected by SYSRESET L The bit is affected by loc...

Page 112: ...G ADDRESS 4 MASTER ADDRESS TRANSLATION ADDRESS 4 VMEchip2 LCSR Base Address FFF40000 OFFSET 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 MAST D16 EN MAST WP EN MAST D16 EN MAST WP EN MASTER AM 3 MASTER AM 4 GCSR GROUP SELECT GCSR BOARD SELECT MAST 4 EN MAST 3 EN MAST 2 EN MAST 1 EN TICK 2 1 TICK IRQ ...

Page 113: ...T 1 SLAVE ADDRESS TRANSLATION SELECT 2 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 IO2 EN IO2 WP EN IO2 S U IO2 P D IO1 EN IO1 D16 EN IO1 WP EN IO1 S U 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 MASTER AM 2 MASTER AM 1 ROM SIZE ROM BANK B SPEED ROM BANK A SPEED DMA TBL INT DMA LB SNP MODE DMA INC VME DMA INC LB DMA D64 BLK DMA BLK DMA AM 5 DMA AM 4 DMA WRT DMA D16 DMA AM...

Page 114: ...PE IRQ IRQ1E IRQ TIC2 IRQ TIC1 IRQ VME IACK IRQ DMA IRQ SIG3 IRQ SIG2 IRQ SIG1 IRQ SIG0 IRQ LM1 IRQ LM0 IRQ ABORT IRQ LEVEL SYS FAIL IRQ LEVEL MST WP ERROR IRQ LEVEL VME IACK IRQ LEVEL DMA IRQ LEVEL SIG 3 IRQ LEVEL SIG 2 IRQ LEVEL SW7 IRQ LEVEL SW6 IRQ LEVEL SW5 IRQ LEVEL SW4 IRQ LEVEL SPARE IRQ LEVEL VME IRQ 7 IRQ LEVEL VME IRQ 6 IRQ LEVEL VME IRQ 5 IRQ LEVEL VECTOR BASE REGISTER 0 VECTOR BASE RE...

Page 115: ... 1 EN IRQ 0 CLR IRQ 15 CLR IRQ 14 CLR IRQ 13 CLR IRQ 12 CLR IRQ 11 CLR IRQ 10 CLR IRQ 9 CLR IRQ 8 SET IRQ 15 SET IRQ 14 SET IRQ 13 SET IRQ 12 SET IRQ 11 SET IRQ 10 SET IRQ 9 SET IRQ 8 SW7 IRQ SW6 IRQ SW5 IRQ SW4 IRQ SW3 IRQ SW2 IRQ SW1 IRQ SW0 IRQ SPARE VME IRQ7 VME IRQ6 VME IRQ5 VME IRQ4 VME IRQ3 VME IRQ2 VME IRQ1 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 GPIOO P ERROR IRQ LEVEL IRQ1E IRQ LEVEL TIC T...

Page 116: ...dress modifier select register and attribute register The tables on the following pages list the addresses and bit definitions of these registers The VMEbus slave map decoders described in this section are disabled by local reset SYSRESET or power up reset Use caution when enabling the map decoders or when modifying their registers after they are enabled The safest time to enable or modify the map...

Page 117: ...f address translation is not desired then the address translation registers should be programmed to 0 The address translation address register and the address translation select register operate in the following way If you set a bit in the address translation select register then the corresponding bit in the address translation address register drives the appropriate local bus address line If you ...

Page 118: ... attribute register The snoop bits in the attribute register are driven on to the local bus when the VMEbus to local bus interface is local bus master VMEbus Slave Ending Address Register 1 This register is the ending address register for the first VMEbus to local bus map decoder VMEbus Slave Starting Address Register 1 This register is the starting address register for the first VMEbus to local b...

Page 119: ...s Translation Address Offset Register 1 This register is the address translation address register for the first VMEbus to local bus map decoder It should be programmed to the local bus starting address When the adder is engaged this register is the offset value ADR SIZ FFF40004 16 bits of 32 BIT 31 16 NAME Ending Address Register 2 OPER R W RESET 0 PS ADR SIZ FFF40004 16 bits of 32 BIT 15 0 NAME S...

Page 120: ... between the VMEbus starting and ending addresses If the segment size is between the sizes shown in the table below assume the larger size ADR SIZ FFF40008 16 bits of 32 BIT 15 0 NAME Address Translation Select Register 1 OPER R W RESET 0 PS Segment Size Address Translation Select Value Segment Size Address Translation Select Value 64KB FFFF 32MB FE00 128KB FFFE 64MB FC00 256KB FFFC 128MB F800 512...

Page 121: ...der The address translation select register value is based on the segment size the difference between the VMEbus starting and ending addresses If the segment size is between the sizes shown in the table below assume the larger size ADR SIZ FFF4000C 16 bits of 32 BIT 31 16 NAME Address Translation Address Offset Register 2 OPER R W RESET 0 PS ADR SIZ FFF4000C 16 bits of 32 BIT 15 0 NAME Address Tra...

Page 122: ...ontrol the snoop enable lines to the local bus for the address range defined by the second VMEbus slave map decoder The snooping functions differ according to processor type as shown ADDER2 When this bit is high the adder is used for address translation When this bit is low the adder is not used for address translation ADR SIZ FFF40010 8 bits 4 used of 32 BIT 31 30 29 28 27 26 25 24 NAME ADDER 2 S...

Page 123: ...ram access cycles When this bit is low the second map decoder does not respond to VMEbus program access cycles BLK When this bit is high the second map decoder responds to VMEbus block access cycles When this bit is low the second map decoder does not respond to VMEbus block access cycles D64 When this bit is high the second map decoder responds to VMEbus D64 block access cycles When this bit is l...

Page 124: ...d to VMEbus A32 access cycles USR When this bit is high the second map decoder responds to VMEbus user non privileged access cycles When this bit is low the second map decoder does not responded to VMEbus user access cycles SUP When this bit is high the second map decoder responds to VMEbus supervisory access cycles When this bit is low the second map decoder does not respond to VMEbus supervisory...

Page 125: ...e bits control the snoop enable lines to the local bus for the address range defined by the first VMEbus slave map decoder The snooping functions differ according to processor type as shown ADDER1 When this bit is high the adder is used for address translation When this bit is low the adder is not used for address translation ADR SIZ FFF40010 8 bits 4 used of 32 BIT 15 14 13 12 11 10 9 8 NAME ADDE...

Page 126: ...ogram access cycles When this bit is low the first map decoder does not respond to VMEbus program access cycles BLK When this bit is high the first map decoder responds to VMEbus block access cycles When this bit is low the first map decoder does not respond to VMEbus block access cycles D64 When this bit is high the first map decoder responds to VMEbus D64 block access cycles When this bit is low...

Page 127: ...GCSR base address registers The local bus to VMEbus interface allows onboard local bus masters access to off board VMEbus resources The address of the VMEbus resources as viewed from the local bus is controlled by the local bus slave map decoders which are part of the local bus to VMEbus interface Four of the six local bus to VMEbus map decoders are programmable while the two I O map decoders are ...

Page 128: ...p may support write posting while others do not The VMEbus area in question may be mapped to two local bus addresses one with write posting enabled and one with write posting disabled The address translation registers allow local bus address bits A31 through A16 to be modified The address translation register should be programmed with the translated address and the address translation select regis...

Page 129: ... decoder provides support for the other I O map of the VMEbus This decoder maps the local bus address range F0000000 to F0FFFFFF to the A24 map of the VMEbus and the address range F1000000 to FF7FFFFF to the A32 map of the VMEbus The transfer size is always D16 This segment may be enabled using the enable bit Write posting may be enabled using the write post enable bit The local bus map decoders s...

Page 130: ... address register for the second local bus to VMEbus map decoder Local Bus Slave VMEbus Master Starting Address Register 2 This register is the starting address register for the second local bus to VMEbus map decoder ADR SIZ FFF40014 16 bits of 32 BIT 15 0 NAME Starting Address Register 1 OPER R W RESET 0 PS ADR SIZ FFF40018 16 bits of 32 BIT 31 16 NAME Ending Address Register 2 OPER R W RESET 0 P...

Page 131: ...e starting address register for the third local bus to VMEbus map decoder Local Bus Slave VMEbus Master Ending Address Register 4 This register is the ending address register for the fourth local bus to VMEbus map decoder ADR SIZ FFF4001C 16 bits of 32 BIT 31 16 NAME Ending Address Register 3 OPER R W RESET 0 PS ADR SIZ FFF4001C 16 bits of 32 BIT 15 0 NAME Starting Address Register 3 OPER R W RESE...

Page 132: ...ister for the fourth local bus to VMEbus bus map decoder Local Bus Slave VMEbus Master Address Translation Select Register 4 This register is the address translation select register for the fourth local bus to VMEbus bus map decoder ADR SIZ FFF40020 16 bits of 32 BIT 15 0 NAME Starting Address Register 4 OPER R W RESET 0 PS ADR SIZ FFF40024 16 bits of 32 BIT 31 16 NAME Address Translation Address ...

Page 133: ...ace does not support block transfers the block transfer address modifier codes should not be used WP When this bit is high write posting is enabled to the segment defined by map decoder 4 When this bit is low write posting is disabled to the segment defined by map decoder 4 D16 When this bit is high D16 data transfers are performed to the segment defined by map decoder 4 When this bit is low D32 d...

Page 134: ... not support block transfers the block transfer address modifier codes should not be used WP When this bit is high write posting is enabled to the segment defined by map decoder 3 When this bit is low write posting is disabled to the segment defined by map decoder 3 D16 When this bit is high D16 data transfers are performed to the segment defined by map decoder 3 When this bit is low D32 data tran...

Page 135: ...ace does not support block transfers the block transfer address modifier codes should not be used WP When this bit is high write posting is enabled to the segment defined by map decoder 2 When this bit is low write posting is disabled to the segment defined by map decoder 2 D16 When this bit is high D16 data transfers are performed to the segment defined by map decoder 2 When this bit is low D32 d...

Page 136: ...does not support block transfers the block transfer address modifier codes should not be used WP When this bit is high write posting is enabled to the segment defined by map decoder 1 When this bit is low write posting is disabled to the segment defined by map decoder 1 D16 When this bit is high D16 data transfers are performed to the segment defined by map decoder 1 When this bit is low D32 data ...

Page 137: ...y the group address and the board address Once enabled the GCSR register should not be reprogrammed unless the VMEchip2 ASIC is VMEbus master GCSR Group These bits define the group portion of the GCSR address These bits are compared with VMEbus address lines A8 through A15 The recommended group address for the MVME1x7P is D2 ADR SIZ FFF4002C 8 bits of 32 BIT 31 24 NAME GCSR Group Address Register ...

Page 138: ...he GCSR board address register disables the map decoder The map decoder is enabled when the board address is not F GCSR Board These bits define the board number portion of the GCSR address These bits are compared with VMEbus address lines A4 through A7 The GCSR is enabled by values 0 through E The address XXFY in the VMEbus A16 space is reserved for the location monitors LM0 through LM3 Note that ...

Page 139: ...2 When this bit is high the second local bus to VMEbus map decoder is enabled When this bit is low the second local bus to VMEbus map decoder is disabled EN3 When this bit is high the third local bus to VMEbus map decoder is enabled When this bit is low the third local bus to VMEbus map decoder is disabled EN4 When this bit is high the fourth local bus to VMEbus map decoder is enabled When this bi...

Page 140: ...the VMEbus short I O segment When this bit is low D32 data transfers are performed to the VMEbus short I O segment I1EN When this bit is high the VMEbus short I O map decoder is enabled When this bit is low the VMEbus short I O map decoder is disabled I2PD When this bit is high the VMEchip2 drives a program address modifier code when the F page is accessed When this bit is low the VMEchip2 drives ...

Page 141: ...status register and local bus to VMEbus requester register The VMEchip2 features a local bus to VMEbus DMA controller DMAC The DMAC has two modes of operation command chaining and direct In direct mode the local bus address the VMEbus address the byte count and the control register of the DMAC are programmed and the DMAC is enabled The DMAC transfers data as programmed until the byte count is zero...

Page 142: ...ed in the local bus interrupter the local bus is interrupted The DMAC control is divided into two registers The first register is only accessible by the processor The second register can be loaded by the processor in direct mode and by the DMAC in command chaining mode Once the DMAC is enabled the counter and control registers should not be modified by software When you use the command chaining mo...

Page 143: ...ister This register controls the snoop control bits used by the DMAC when it is accessing table entries SRAMS These VMEchip2 bits are not used on the MVME1x7P Table 2 3 DMAC Command Packet Format Entry Function 0 bits 0 15 Control Word 1 bits 0 31 Local Bus Address 2 bits 0 31 VMEbus Address 3 bits 0 31 Byte Count 4 bits 0 31 Address of Next Command Packet ADR SIZ FFF40030 8 bits 6 used of 32 BIT ...

Page 144: ... request level The request level can only change while the VMEchip2 is bus master The VMEchip2 always requests at the old level until it becomes bus master and the new level takes effect If the VMEchip2 is bus master when the level is changed the new level does not take effect until the bus has been released and re requested at the old level The requester always requests the VMEbus at level 3 the ...

Page 145: ...low the VMEchip2 releases the VMEbus according to the release mode programmed in the LVRWD bit When the VMEbus has been acquired the DHB bit is set DHB When this bit is high the VMEbus has been acquired in response to the DWB bit being set When the DWB bit is cleared this bit is cleared ROBN When this bit is high the VMEbus arbiter operates in round robin mode When this bit is low the arbiter oper...

Page 146: ...bus 0 Release when the time on timer has expired and a BRx signal is active on the VMEbus 1 Release when the time on timer has expired 2 Release when a BRx signal is active on the VMEbus 3 Release when a BRx signal is active on the VMEbus or the time on timer has expired DFAIR When this bit is high the DMAC requester operates in fair mode It waits until its request level is inactive before request...

Page 147: ...s transferred to the VMEbus When it is low data is transferred to the local bus LINC When this bit is high the local bus address counter is incremented during DMA transfers When this bit is low the counter is not incremented This bit should normally be set high In special situations such as transferring data to or from a FIFO it may be desirable to not increment the counter VINC When this bit is h...

Page 148: ...ter 2 bits 0 7 This portion of the control register is loaded by the processor or the DMAC when it loads the command word from the command packet Because this byte is loaded from the command packet in command chaining mode the descriptions here also apply to the control word in the command packet VME AM These bits define the address modifier codes the DMAC drives on the VMEbus when it is bus maste...

Page 149: ...2 block transfer cycles on the VMEbus In block transfer mode the DMAC may execute byte and two byte cycles at the beginning and ending of a transfer in non block transfer mode If the D16 bit is set the DMAC executes D16 block transfers 2 Block transfers disabled 3 The DMAC executes D64 block transfer cycles on the VMEbus In block transfer mode the DMAC may execute byte two byte and four byte cycle...

Page 150: ...chaining mode this counter should be loaded by the processor with the starting address of the list of commands This register gets reloaded by the DMAC with the starting address of the current command The last command in a list should have bits 0 and 1 set in the next command pointer ADR SIZ FFF4003C 32 bits BIT 31 0 NAME DMAC VMEbus Address Counter OPER R W RESET 0 PS ADR SIZ FFF40040 32 bits BIT ...

Page 151: ...s bit is the VMEbus interrupt clear bit When this bit is set high the VMEbus interrupt is removed This feature is only used when the IRQ1 broadcast mode is used Normal VMEbus interrupts should never be cleared This bit always reads 0 writing a 0 to it has no effect IRQ1S These bits control the function of the IRQ1 signal line on the VMEbus 0 The IRQ1 signal from the interrupter is connected to the...

Page 152: ...U received a TEA and the status indicated a parity error during a DRAM data transfer This bit is cleared by writing a 1 to the MCLR bit in this register MLBE When this bit is set the MPU received a TEA and no additional status was provided This bit is cleared by writing a 1 to the MCLR bit in this register MCLR Writing a 1 to this bit clears the MPU status bits 7 8 9 and 10 MLTO MLOB MLPE and MLBE...

Page 153: ...et This bit is cleared when the DMAC is enabled VME If this bit is set the DMAC has received a VMEbus BERR during a data transfer This bit is cleared when the DMAC is enabled TBL If this bit is set the DMAC has received an error on the local bus while it was reading commands from the command packet Additional information is provided in bits 3 6 DLTO DLOB DLPE and DLBE This bit is cleared when the ...

Page 154: ...tchdog Timers The VMEchip2 has two 32 bit tick timers and one watchdog timer This section provides addresses and bit level descriptions of the prescaler tick timer watchdog timer registers and various other timer registers VMEbus Arbiter Time Out Control Register This register controls the VMEbus arbiter time out timer ARBTO When this bit is high the VMEbus grant time out timer is enabled When thi...

Page 155: ...strobes are removed a BERR signal is sent to the VMEbus The global time out timer is disabled when the VMEchip2 is not system controller 0 8 µs 1 64 µs 2 256 µs 3 The timer is disabled TIME ON These bits define the maximum time the DMAC spends on the VMEbus 0 16 µs 4 256 µs 1 32 µs 5 512 µs 2 64 µs 6 1024 µs 3 128 µs 7 When done or no data TIME OFF These bits define the minimum time the DMAC spend...

Page 156: ...o the VMEbus and the VMEchip2 is not the current VMEbus master the access timer begins timing If the VMEchip2 has not received bus mastership before the timer times out and the transaction is not write posted a TEA signal is sent to the local bus If the transaction is write posted a write post error interrupt is sent to the local bus interrupter ADR SIZ FFF4004C 8 bits of 32 BIT 15 14 13 12 11 10 ...

Page 157: ...ion at 25MHz the prescaler value is E7 and at 32MHz it is E0 Non integer local bus clocks introduce an error into the specified times for the various counters and timers This is most notable in the tick timers The tick timer clock can be derived by the following equation tick timer clock Bclock 256 prescaler value If the prescaler is not correctly programmed the bus timers do not generate their sp...

Page 158: ... T compare register value T µs When programming the tick timer for periodic interrupts the counter should be cleared to zero by software and then enabled If the counter does not initially start at 0 the time to the first interrupt may be longer or shorter than expected Remember the rollover time for the counter is 71 6 minutes Tick Timer 1 Counter This is the tick timer 1 counter When enabled it i...

Page 159: ...c period compare register value T µs When programming the tick timer for periodic interrupts the counter should be cleared to zero by software and then enabled If the counter does not initially start at 0 the time to the first interrupt may be longer or shorter than expected Remember the rollover time for the counter is 71 6 minutes Tick Timer 2 Counter This is the tick timer 2 counter When enable...

Page 160: ...This bit is set by a powerup reset It is cleared by a write to the CPURS bit BRFLI When this status bit is high the BRDFAIL signal pin on the VMEchip2 is asserted When this status bit is low the BRDFAIL signal pin on the VMEchip2 is not asserted The BRDFAIL pin may be asserted by an external device the BDFLO bit in this register or a watchdog time out SFFL When this status bit is high the SYSFAIL ...

Page 161: ... watchdog timer has timed out and the watchdog reset enable WDRSE bit in this register is high an LRESET signal is generated on the local bus WDBFE When this bit is high and the watchdog timer has timed out the VMEchip2 asserts the BRDFAIL signal pin When this bit is low the watchdog timer does not contribute to the BRDFAIL signal on the VMEchip2 WDTO When this status bit is high a watchdog time o...

Page 162: ...unter does not increment COC When this bit is high the counter is reset to 0 when it compares with the compare register When this bit is low the counter is not reset COVF The overflow counter is cleared when a 1 is written to this bit OVF These bits are the output of the overflow counter The overflow counter is incremented each time the tick timer sends an interrupt to the local bus interrupter Th...

Page 163: ...Prescaler Counter The VMEchip2 has a 32 bit prescaler that provides the clocks required by the various timers in the chip Access to the prescaler is provided for test purposes The counter is described here because it may be useful in other applications The lower 8 bits of the prescaler counter increment to FF at the local bus clock rate and then they are loaded from the prescaler adjust register W...

Page 164: ...interrupter There are two base registers one for the first 16 interrupters and one for the next 8 interrupters The VMEbus interrupters provide their own vectors A summary of the interrupts appears in Table 2 4 The status bit of an interrupter is affected by the enable bit If the enable bit is low the status bit is also low Interrupts may be polled by setting the enable bit and programming the leve...

Page 165: ...terrupts VMEbus IRQ1 External Lowest VMEbus IRQ2 External VMEbus IRQ3 External VMEbus IRQ4 External VMEbus IRQ5 External VMEbus IRQ6 External VMEbus IRQ7 External Spare Y7 Software 0 Y8 Software 1 Y9 Software 2 YA Software 3 YB Software 4 YC Software 5 YD Software 6 YE Software 7 YF GCSR LM0 X0 GCSR LM1 X1 GCSR SIG0 X2 GCSR SIG1 X3 GCSR SIG2 X4 GCSR SIG3 X5 ...

Page 166: ... later in this chapter for recommended Vector Base register values DMAC X6 VMEbus Interrupter Acknowledge X7 Tick Timer 1 X8 Tick Timer 2 X9 VMEbus IRQ1 Edge Sensitive XA Not used on MVME1x7P XB VMEbus Master Write Post Error XC VMEbus SYSFAIL XD Not used on MVME1x7P XE VMEbus ACFAIL XF Highest Table 2 4 Local Bus Interrupter Summary Continued Interrupt Vector Priority for Simultaneous Interrupts ...

Page 167: ...w a local interrupt is not being generated The interrupt status bits are TIC1 Tick timer 1 interrupt TIC2 Tick timer 2 interrupt VI1E VMEbus IRQ1 edge sensitive interrupt PE Not used on MVME1x7P MWP VMEbus master write post error interrupt SYSF VMEbus SYSFAIL interrupt AB Not used on MVME1x7P ACF VMEbus ACFAIL interrupt ADR SIZ FFF40068 8 bits of 32 BIT 31 30 29 28 27 26 25 24 NAME ACF AB SYSF MWP...

Page 168: ...us bit is low a local interrupt is not being generated The interrupt status bits are LM0 GCSR LM0 interrupt LM1 GCSR LM1 interrupt SIG0 GCSR SIG0 interrupt SIG1 GCSR SIG1 interrupt SIG2 GCSR SIG2 interrupt SIG3 GCSR SIG3 interrupt DMA DMAC interrupt VIA VMEbus interrupter acknowledge interrupt ADR SIZ FFF40068 8 bits of 32 BIT 23 22 21 20 19 18 17 16 NAME VIA DMA SIG3 SIG2 SIG1 SIG0 LM1 LM0 OPER R...

Page 169: ...interrupt status bit is low a local interrupt is not being generated The interrupt status bits are SW0 Software 0 interrupt SW1 Software 1 interrupt SW2 Software 2 interrupt SW3 Software 3 interrupt SW4 Software 4 interrupt SW5 Software 5 interrupt SW6 Software 6 interrupt SW7 Software 7 interrupt ADR SIZ FFF40068 8 bits of 32 BIT 15 14 13 12 11 10 9 8 NAME SW7 SW6 SW5 SW4 SW3 SW2 SW1 SW0 OPER R R...

Page 170: ...tatus bit is low a local interrupt is not being generated The interrupt status bits are VME1 VMEbus IRQ1 Interrupt VME2 VMEbus IRQ2 Interrupt VME3 VMEbus IRQ3 Interrupt VME4 VMEbus IRQ4 Interrupt VME5 VMEbus IRQ5 Interrupt VME6 VMEbus IRQ6 Interrupt VME7 VMEbus IRQ7 Interrupt SPARE Not used ADR SIZ FFF40068 8 bits of 32 BIT 7 6 5 4 3 2 1 0 NAME SPARE VME7 VME6 VME5 VME4 VME3 VME2 VME1 OPER R R R R...

Page 171: ...set If necessary edge sensitive interrupters should be cleared to remove any old interrupts and then re enabled ETIC1 Enable tick timer 1 interrupt ETIC2 Enable tick timer 2 interrupt EVI1E Enable VMEbus IRQ1 edge sensitive interrupt EPE Not used on MVME1x7P EMWP Enable VMEbus master write post error interrupt ESYSF Enable VMEbus SYSFAIL interrupt EAB Not used on MVME1x7P EACF Enable VMEbus ACFAIL...

Page 172: ...m being set If necessary edge sensitive interrupters should be cleared to remove any old interrupts and then re enabled ELM0 Enable GCSR LM0 interrupt ELM1 Enable GCSR LM1 interrupt ESIG0 Enable GCSR SIG0 interrupt ESIG1 Enable GCSR SIG1 interrupt ESIG2 Enable GCSR SIG2 interrupt ESIG3 Enable GCSR SIG3 interrupt EDMA Enable DMAC interrupt EVIA VMEbus interrupter acknowledge interrupt ADR SIZ FFF40...

Page 173: ...op from being set If necessary edge sensitive interrupters should be cleared to remove any old interrupts and then re enabled ESW0 Enable software 0 interrupt ESW1 Enable software 1 interrupt ESW2 Enable software 2 interrupt ESW3 Enable software 3 interrupt ESW4 Enable software 4 interrupt ESW5 Enable software 5 interrupt ESW6 Enable software 6 interrupt ESW7 Enable software 7 interrupt ADR SIZ FF...

Page 174: ...om being set If necessary edge sensitive interrupters should be cleared to remove any old interrupts and then re enabled EIRQ1 Enable VMEbus IRQ1 interrupt EIRQ2 Enable VMEbus IRQ2 interrupt EIRQ3 Enable VMEbus IRQ3 interrupt EIRQ4 Enable VMEbus IRQ4 interrupt EIRQ5 Enable VMEbus IRQ5 interrupt EIRQ6 Enable VMEbus IRQ6 interrupt EIRQ7 Enable VMEbus IRQ7 interrupt SPARE SPARE ADR SIZ FFF4006C 8 bit...

Page 175: ...errupt SSW7 Set software 7 interrupt Interrupt Clear Register bits 24 31 This register is used to clear the edge sensitive interrupts An interrupt is cleared by writing a 1 to its clear bit The clear bits are defined below CTIC1 Clear tick timer 1 interrupt CTIC2 Clear tick timer 2 interrupt ADR SIZ FFF40070 8 bits of 32 BIT 15 14 13 12 11 10 9 8 NAME SSW7 SSW6 SSW5 SSW4 SSW3 SSW2 SSW1 SSW0 OPER S...

Page 176: ...ar the edge sensitive interrupts An interrupt is cleared by writing a 1 to its clear bit The clear bits are defined below CLM0 Clear GCSR LM0 interrupt CLM1 Clear GCSR LM1 interrupt CSIG0 Clear GCSR SIG0 interrupt CSIG1 Clear GCSR SIG1 interrupt CSIG2 Clear GCSR SIG2 interrupt CSIG3 Clear GCSR SIG3 interrupt CDMA Clear DMA controller interrupt CVIA Clear VMEbus interrupter acknowledge interrupt AD...

Page 177: ...4 interrupt CSW5 Clear software 5 interrupt CSW6 Clear software 6 interrupt CSW7 Clear software 7 interrupt Interrupt Level Register 1 bits 24 31 This register is used to define the level of the abort interrupt and the ACFAIL interrupt AB LEVEL Not used on MVME1x7P ACF LEVEL These bits define the level of the ACFAIL interrupt ADR SIZ FFF40074 8 bits of 32 BIT 15 14 13 12 11 10 9 8 NAME CSW7 CSW6 C...

Page 178: ...e SYSFAIL interrupt Interrupt Level Register 1 bits 8 15 This register is used to define the level of the VMEbus IRQ1 edge sensitive interrupt and the level of the external interrupt IRQ1E LEVEL These bits define the level of the VMEbus IRQ1 edge sensitive interrupt PE LEVEL Not used on MVME1x7P ADR SIZ FFF40078 8 bits 6 used of 32 BIT 23 22 21 20 19 18 17 16 NAME SYSF LEVEL WPE LEVEL OPER R W R W...

Page 179: ...rupt Interrupt Level Register 2 bits 24 31 This register is used to define the level of the DMA controller interrupt and the VMEbus acknowledge interrupt DMA LEVEL These bits define the level of the DMA controller interrupt VIA LEVEL These bits define the level of the VMEbus interrupter acknowledge interrupt ADR SIZ FFF40078 8 bits 6 used of 32 BIT 7 6 5 4 3 2 1 0 NAME TICK2 LEVEL TICK1 LEVEL OPER...

Page 180: ...nterrupt Interrupt Level Register 2 bits 8 15 This register is used to define the level of the GCSR SIG0 interrupt and the GCSR SIG1 interrupt SIG0 LEVEL These bits define the level of the GCSR SIG0 interrupt SIG1 LEVEL These bits define the level of the GCSR SIG1 interrupt ADR SIZ FFF4007C 8 bits 6 used of 32 BIT 23 22 21 20 19 18 17 16 NAME SIG3 LEVEL SIG2 LEVEL OPER R W R W RESET 0 PSL 0 PSL AD...

Page 181: ... LM1 interrupt Interrupt Level Register 3 bits 24 31 This register is used to define the level of the software 6 interrupt and the software 7 interrupt SW6 LEVEL These bits define the level of the software 6 interrupt SW7 LEVEL These bits define the level of the software 7 interrupt ADR SIZ FFF4007C 8 bits 6 used of 32 BIT 7 6 5 4 3 2 1 0 NAME LM1 LEVEL LM0 LEVEL OPER R W R W RESET 0 PSL 0 PSL ADR...

Page 182: ... interrupt Interrupt Level Register 3 bits 8 15 This register is used to define the level of the software 2 interrupt and the software 3 interrupt SW2 LEVEL These bits define the level of the software 2 interrupt SW3 LEVEL These bits define the level of the software 3 interrupt ADR SIZ FFF40080 8 bits 6 used of 32 BIT 23 22 21 20 19 18 17 16 NAME SW5 LEVEL SW4 LEVEL OPER R W R W RESET 0 PSL 0 PSL ...

Page 183: ...t Level Register 4 bits 24 31 This register is used to define the level of the VMEbus IRQ7 interrupt and the spare interrupt The VMEbus level 7 IRQ7 interrupt may be mapped to any local bus interrupt level VIRQ7 LEVEL These bits define the level of the VMEbus IRQ7 interrupt SPARE LEVEL Not used on the MVME1x7P ADR SIZ FFF40080 8 bits 6 used of 32 BIT 7 6 5 4 3 2 1 0 NAME SW1 LEVEL SW0 LEVEL OPER R...

Page 184: ...Q6 interrupt Interrupt Level Register 4 bits 8 15 This register is used to define the level of the VMEbus level 3 IRQ3 interrupt and the VMEbus level 4 IRQ4 interrupt The IRQ3 and IRQ4 interrupts may be mapped to any local bus interrupt level VIRQ3 LEVEL These bits define the level of the VMEbus IRQ3 interrupt VIRQ4 LEVEL These bits define the level of the VMEbus IRQ4 interrupt ADR SIZ FFF40084 8 ...

Page 185: ...interrupt base vectors VBR 1 These bits define the interrupt base vector 1 VBR 0 These bits define the interrupt base vector 0 Note Refer to Table 2 4 Local Bus Interrupter Summary for further information A suggested setting for the VMEchip2 Vector Base register is VBR0 6 VBR1 7 i e setting the Vector Base register at address FFF40088 to 67xxxxxx This produces a Vector Base0 of 60 corresponding to...

Page 186: ...e status of the ABORT switch When this bit is high the ABORT switch is depressed When this bit is low the ABORT switch is not depressed ACFL This bit indicates the status of the ACFAIL signal line on the VMEbus When this bit is high the ACFAIL signal line is active When this bit is low the ACFAIL signal line is not active SYSFL This bit indicates the status of the SYSFAIL signal line on the VMEbus...

Page 187: ...Remote Status and Control register GPIOI1 Not used GPIOI2 Not used GPIOI3 Not used I O Control Register 3 This function is not used on the MVME1x7P ADR SIZ FFF40088 8 bits of 32 BIT 15 14 13 12 11 10 9 8 NAME GPIOO3 GPIOO2 GPIOO1 GPIOO0 GPIOI3 GPIOI2 GPIOI1 GPIOI0 OPER R W R W R W R W R R R R RESET 0 PSL 0 PS 0 PS 0 PS X X X X ADR SIZ FFF40088 8 bits of 32 BIT 7 6 5 4 3 2 1 0 NAME GPI7 GPI6 GPI5 G...

Page 188: ...cess the local bus a deadlock is created The VMEchip2 detects this condition and requests the local bus master to give up the local bus and retry the cycle This allows the VMEbus master to complete the cycle to the local bus If the VMEchip2 receives VMEbus mastership the local master has not returned from the retry and this bit is high VMEchip2 drives VMEbus BBSY for the minimum time about 90 ns a...

Page 189: ...l Bus Busy When this bit is low the VME LED on the MVME1x7P illuminates on assertion of Local Bus Reset when the VMEchip2 is driving Local Bus Busy or when the VMEchip2 is driving the VMEbus address strobe The signal is also available at J2 the Remote Reset connector behind the front panel This connector allows the Reset Abort and LED functions to be extended to the exterior of the enclosure conta...

Page 190: ... the group are cleared The signal interrupts SIG0 SIG3 should be used to signal individual boards The location monitors are located in the VMEbus short I O space and the specific address is determined by the VMEchip2 group address The location monitors LM0 LM3 are located at addresses XXF1 XXF3 XXF5 and XXF7 respectively A location monitor cycle on the VMEbus is generated by a read or write to VME...

Page 191: ...t clear register The Board Control register allows a VMEbus master to reset the local bus prevent the VMEchip2 from driving the SYSFAIL signal line and detect if the VMEchip2 wants to drive the SYSFAIL signal line The six General Purpose registers can be read and written from both the local bus and the VMEbus These registers are provided to allow local bus masters to communicate with VMEbus master...

Page 192: ...y this table 3 The name of the register or the name of the bits in the register 4 The operations possible on the register bits defined as follows 5 The state of the bit following a reset defined as follows R This bit is a read only status bit R W This bit is readable and writable S R Writing a 1 to this bit sets it Reading it returns its current status P This bit is affected by power up reset S Th...

Page 193: ...ress FFF40100 Offsets Bit Numbers VM E bus Loca l Bus 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 Chip Revision Chip ID 2 4 LM 3 LM 2 LM 1 LM 0 SI G3 SI G2 SI G1 SI G0 RS T IS F B F SCO N SYSF L X X X 4 8 General Purpose Control and Status Register 0 6 C General Purpose Control and Status Register 1 8 10 General Purpose Control and Status Register 2 A 14 General Purpose Control and Status Register 3...

Page 194: ...1 to it When the SIG1 bit is set an interrupt is sent to the local bus interrupter The SIG1 bit is cleared when the local processor writes a 1 to the SIG1 bit in this register or the CSIG1 bit in the local interrupt clear register SIG2 The SIG2 bit is set when a VMEbus master writes a 1 to it When the SIG2 bit is set an interrupt is sent to the local bus interrupter The SIG2 bit is cleared when th...

Page 195: ...l processor or a VMEbus master writes a 1 to the LM0 bit in this register or the CLM0 bit in local interrupt clear register LM1 This bit is cleared by an LM1 cycle on the VMEbus When this bit is cleared an interrupt is set to the local bus interrupter This bit is set when the local processor or a VMEbus master writes a 1 to the LM1 bit in this register or the CLM1 bit in local interrupt clear regi...

Page 196: ...rives SYSFAIL if the inhibit SYSFAIL bit is not set ISF When this bit is set the VMEchip2 is prevented from driving the VMEbus SYSFAIL signal line When this bit is cleared the VMEchip2 is allowed to drive the VMEbus SYSFAIL signal line RST This bit allows a VMEbus master to reset the local bus Refer to the note on local reset in the GCSR Programming Model section earlier in this chapter When this ...

Page 197: ...master The function of this register is not defined by the hardware specification General Purpose Register 2 This register is a general purpose register that allows a local bus master to communicate with a VMEbus master The function of this register is not defined by the hardware specification ADR SIZ Local Bus FFF40108 VMEbus XXY4 16 bits BIT 15 0 NAME General Purpose Register 0 OPER R W RESET 0 ...

Page 198: ...The function of this register is not defined by the hardware specification General Purpose Register 5 This register is a general purpose register that allows a local bus master to communicate with a VMEbus master The function of this register is not defined by the hardware specification ADR SIZ Local Bus FFF40114 VMEbus XXYA 16 bits BIT 15 0 NAME General Purpose Register 3 OPER R W RESET 0 PS ADR ...

Page 199: ...is section lists the major features of the PCCchip2 BBRAM interface with dynamic sizing support 8 bit parallel I O port Master and slave interface for CD2401 Intelligent Multi Protocol Peripheral Host interface to Intel 82596CA LAN Coprocessor Host interface to NCR SCSI I O Processor Two 32 bit tick timers Interrupt handler for tick timers and all peripherals All interrupts are level programmable ...

Page 200: ... bus to the local peripherals on the Single Board Computers including battery backed RAM Serial Communications Controller CL CD2401 LAN controller 82596CA and SCSI controller NCR53C710 The PCCchip2 also provides two 32 bit timers and a parallel I O port The block diagram of the PCCchip2 is shown as Figure 3 1 Figure 3 1 PCCchip2 Block Diagram BBRAM PARALLEL I O PORT CD2401 SCC TICK TIMER 1 TICK TI...

Page 201: ...MC68040 compatible Local Bus master to communicate directly with the Intel 82596CA LAN Coprocessor by providing a map decoder and required control and timing logic Two types of direct access are feasible with the 82596CA MPU Port and MPU Attention MPU Port access enables the MPU to write to an internal 32 bit 82596CA command register This allows the MPU to do four things 1 Write an alternate Syste...

Page 202: ...odifiers TM2 TM0 With the value of 101 Transfer Acknowledge TA if Transfer Error Acknowledge TEA is detected LANC Bus Error The 82596CA does not provide a way to terminate a bus cycle with an error indication The interface to the 82596CA on the Single Board Computers provides several ways of processing bus errors that occur while the 82596CA is local bus master These options are controlled by regi...

Page 203: ...is updated and a LANC bus error interrupt is generated if it is enabled in the PCCchip2 In this case the 82596CA continues to operate and because the cycle was terminated with an error the 82596CA may transmit bad data or corrupt memory LANC Interrupt When the PCCchip2 detects a high level on the INT signal from the 82596CA if such interrupts are enabled it generates an interrupt to the MPU If the...

Page 204: ... port All eight or sixteen bits of the port must be either inputs or outputs no individual selection In addition to the 8 16 bits of data there are two control pins and five status pins Each of the status pins can generate an interrupt to the MPU in any of the following programmable conditions high level low level high to low transition or low to high transition This port may be used as a parallel...

Page 205: ...equester The base address for the CL CD2401 is FFF45000 It has 8 and 16 bit registers only Consequently it does not respond when accessed with a size of 4 bytes SIZ1 0 00 or with a size of 16 bytes SIZ1 0 11 There are three interrupts sources from the SCC receive interrupt transmit interrupt and modem interrupt The PCCchip2 provides the ability to individually program the priority level of each of...

Page 206: ...arts a normal read cycle to one of the three PIACK registers in the PCCchip2 The three PIACK registers correspond to modem transmit and receive interrupts respectively 3 The PCCchip2 upon detecting the start of the read performs an interrupt acknowledge cycle to the CD2401 The PCCchip2 drives the CD2401 A7 through A0 pins with a value that corresponds to the PIACK register that is being read If th...

Page 207: ...ation for these timers free running and clear on compare In free running mode the timers have a resolution of 1 µs and roll over after the count reaches the maximum value FFFFFFFF The rollover period for the timers is 71 6 minutes When the counter is enabled in the clear on compare mode it increments every 1 µs until the counter value matches the value in the compare register When a match occurs t...

Page 208: ...cesses on the Local Bus Table 3 1 PCCchip2 Devices Memory Map Address Range Selected Device Comments FFF42000 FFF4203F PCCchip2 Registers See Programming Model FFF42040 FFF42FFF PCCchip2 Registers Repeated FFF43000 FFF43FFF MCECC Memory Controller External Device FFF45000 FFF450FF CD2401 SCC External Device FFF45100 FFF45FFF CD2401 SCC Repeated FFF46000 FFF46FFF 82596CA LANC External Device FFF470...

Page 209: ...d power up reset are as defined below A summary of the PCCchip2 CSR is shown in Table 6 2 R This bit is a read only status bit R W This bit is readable and writable W AC This bit can be set and it is automatically cleared This bit can also be read C Writing a one to this bit clears this bit or another bit This bit reads zero S Writing a one to this bit sets this bit or another bit This bit reads z...

Page 210: ...0 24 28 2C 30 34 38 3C PRTR ACK IRQ LEVEL GPI PLTY D16 D23 D24 D31 CHIP ID CHIP REVISION TIC TIMER 1 TIC TIMER 1 TIC TIMER 2 TIC TIMER 2 PRESCALER COUNT REGISTER PRESCALER CLOCK ADJUST GPI E L GPI INT GPI IEN GPI ICLR GPI IRQ LEVEL GPI GPOE GPO SCC PAR ERR SCC EXT ERR SCC LTO ERR SCC SCLR SCC MDM ERR SCC MDM IEN SCC MDM AVEC SCC MODEM IRQ LEVEL SCC TRANSMIT PIACK LAN PAR ERR LAN EXT ERR LAN LTO ER...

Page 211: ...ISTER OVERFLOW COUNTER 1 COC EN 2 TIC EN 2 TIC2 IEN TIC2 ICLR TIC1 INT TIC1 IEN TIC1 ICLR SCC TX IRQ SCC TX IEN SCC TX AVEC SCC SC1 SCC SC0 SCC RX IRQ SCC RX IEN SCC RX AVEC SCC MODEM PIACK LAN INT E L LAN INT LAN IEN LAN ICLR LAN INT IRQ LEVEL PRTR SEL PLTY PRTR SEL E L PRTR SEL INT PRTR SEL IEN PRTR SEL ICLR PRTR ANY INT PRTR ACK PRTR FLT PRTR SEL PRTR PE PRTR BSY PRTR SEL IRQ LEVEL PRINTER DATA...

Page 212: ...er is located at FFF42001 It is an 8 bit read only register that is hard wired to reflect the revision level of the PCCchip2 ASIC The current value of this register is 00 Writes to this register are ignored however the PCCchip2 always terminates the cycles properly with TA ADR SIZ FFF42000 8 bits BIT 31 30 29 28 27 26 25 24 NAME CID7 CID6 CID5 CID4 CID3 CID2 CID1 CID0 OPER R R R R R R R R RESET 0 ...

Page 213: ...evices that have access times of 200 ns or faster It is not allowed to use devices slower than 360 ns 9 CLK cycles at 25 MHz When operating at 33 MHz the FAST bit should be cleared for devices with access times longer than 150 ns 5 CLK cycles The bit can be set for devices that have access times 150 ns or faster It is not allowed to use devices slower than 270 ns 9 CLK cycles at 33 MHz MIEN Master...

Page 214: ...access after the reset then the PCCchip2 sets DR0 This causes the DROM to respond to the memory access and all memory accesses thereafter until software clears DR0 Note V 1 if no other device responds to the first memory access after Power up or Local Reset Otherwise V 0 Vector Base Register The Interrupt Vector Base Register is located at FFF42003 It is an 8 bit read write register that is used t...

Page 215: ...e AVEC bit in the following registers SCC Modem Interrupt Control Register SCC Transmit Interrupt Control Register and SCC Receive Interrupt Control Register If this mode is disabled by setting the AVEC bits to 0 then the PCCchip2 obtains the vector from the SCC and passes it to the MPU Using the auto vector mode is NOT recommended ADR SIZ FFF42003 8 bits BIT 7 6 5 4 3 2 1 0 NAME IV7 IV6 IV5 IV4 I...

Page 216: ...ocal Bus interrupter and the overflow counter is incremented If the clear on compare mode is enabled the counter is also cleared For periodic interrupts the following equation should be used to determine the compare register value for a specific period compare register value T µs When programming the tick timer for periodic interrupts the counter should be cleared to zero by software and then enab...

Page 217: ...he overflow counter is incremented If the clear on compare mode is enabled the counter is also cleared For periodic interrupts the following equation should be used to determine the compare register value for a specific period compare register value T µs When programming the tick timer for periodic interrupts the counter should be cleared to zero by software and then enabled If the counter does no...

Page 218: ...ess FFF42014 It increments to FF at the BCLK frequency then it is loaded from the Prescaler Clock Adjust Register Prescaler Clock Adjust Register Note The PCCchip2 runs at half the MPU speed on the MVME177P For example an MVME177P with a 50 MHz MPU will run the PCCchip2 at 25 MHz The Prescaler Clock Adjust Register is an 8 bit read write register located at address FFF42015 It is required to adjus...

Page 219: ...on integer Local Bus clocks introduce an error into the specified times for the tick timers The tick timer clock can be derived by the following equation tick timer clock BCLK 256 prescaler value The maximum clock frequency for the tick timers is the BCLK frequency divided by two The value 255 FF is not allowed to be programmed into this register If a write with the value of FF occurs to this regi...

Page 220: ... compares with the compare register When this bit is low the counter is not reset COVF Clear Overflow Counter The overflow counter is cleared when a one is written to this bit OVF3 OVF0 These four bits are the outputs of the overflow counter The overflow counter is incremented each time the tick timer sends an interrupt to the Local Bus interrupter The overflow counter can be cleared by writing a ...

Page 221: ...when it compares with the compare register When this bit is low the counter is not reset COVF Clear Overflow Counter The overflow counter is cleared when a one is written to this bit OVF3 OVF0 These four bits are the outputs of the overflow counter The overflow counter is incremented each time the tick timer sends an interrupt to the Local Bus interrupter The overflow counter can be cleared by wri...

Page 222: ...grammed in IL2 IL0 if nonzero E L When this bit is high the interrupt is edge sensitive The interrupt is level sensitive when this bit is low PLTY When this bit is low the interrupt is activated by either a rising edge on the GPIO pin or a high level on the GPIO pin depending on the E L bit When this bit is high the interrupt is activated by either a falling edge on the GPIO pin or a low level of ...

Page 223: ...w On the Single Board Computers the PCCGPIO1 pin is connected to the remote reset connector pin 19 Tick Timer 2 Interrupt Control Register IL2 IL0 Interrupt Request Level These three bits select the interrupt level for Tick Timer 2 Level 0 does not generate an interrupt ICLR Writing a logic 1 into this bit clears the INT status bit This bit is always read as zero IEN Interrupt Enable When this bit...

Page 224: ... Level 0 does not generate an interrupt ICLR Writing a logic 1 into this bit clears the INT status bit This bit is always read as zero IEN Interrupt Enable When this bit is high the interrupt is enabled The interrupt is disabled when this bit is low INT Interrupt Status When this bit is high a Tick Timer 1 interrupt is being generated at the level programmed in IL2 IL0 if nonzero This bit is edge ...

Page 225: ...e assertion of TEA When the SCC receives TEA if the source of the error is local time out then LTO is set and EXT PRTY and RTRY are cleared If the source of the TEA is due to an error in going to the VMEbus then EXT is set and the other three status bits are cleared If the source of the error is DRAM parity check error then PRTY is set and the other three status bits are cleared If the source of t...

Page 226: ...ses it to the MPU The use of the AVEC mode is not recommended IEN Interrupt Enable When this bit is high the interrupt is enabled The interrupt is disabled when this bit is low IRQ Interrupt Status This status bit reflects the state of the SCC IRQ1 pin of the CD2401 qualified by the IEN bit When this bit is high an SCC modem interrupt is being generated at the level programmed in IL2 IL0 if nonzer...

Page 227: ...C and passes it to the MPU The use of the AVEC mode is not recommended IEN Interrupt Enable When this bit is high the interrupt is enabled The interrupt is disabled when this bit is low IRQ Interrupt Status This status bit reflects the state of the SCC IRQ2 pin of the CD2401 qualified by the IEN bit When this bit is high an SCC Transmit interrupt is being generated at the level programmed in IL2 I...

Page 228: ...IRQ3 pin of the CD2401 qualified by the IEN bit When this bit is high an SCC receive interrupt is being generated at the level programmed in IL2 IL0 if nonzero This status bit does not need to be cleared because it is not edge sensitive SC1 SC0 Snoop Control These control bits determine the value that the PCCchip2 drives onto the local MC68040 bus SC1 and SC0 pins when the CL CD2401 SCC performs D...

Page 229: ...01 onto the local data bus and asserts TA Reads to this register are termed pseudo interrupt acknowledge cycles because they are normal read cycles on the Local Bus side but they are interrupt acknowledge cycles on the CD2401 side of the PCCchip2 They are necessary to support polled mode operation with the CD2401 Note If this register is read when an interrupt is not present the interrupt acknowle...

Page 230: ... the local data bus and asserts TA Reads to this register are termed pseudo interrupt acknowledge cycles because they are normal read cycles on the Local Bus side but they are interrupt acknowledge cycles on the CD2401 side of the PCCchip2 They are necessary to support polled mode operation with the CD2401 Note If this register is read when an interrupt is not present the interrupt acknowledge cyc...

Page 231: ...401 onto the local data bus and asserts TA Reads to this register are termed pseudo interrupt acknowledge cycles because they are normal read cycles on the Local Bus side but they are interrupt acknowledge cycles on the CD2401 side of the PCCchip2 They are necessary to support polled mode operation with the CD2401 Note If this register is read when an interrupt is not present the interrupt acknowl...

Page 232: ...Local Bus A Local Bus error condition is flagged by the assertion of TEA When the LANC receives TEA If the source of the error is local time out then LTO is set and EXT and PRTY are cleared If the source of the TEA is due to an error in going to the VMEbus then EXT is set and the other two status bits are cleared If the source of the error is DRAM parity check error then PRTY is set and the other ...

Page 233: ...he IEN bit When this bit is high a LANC INT interrupt is being generated at the level programmed in IL2 IL0 if nonzero E L Edge or Level When this bit is high the interrupt is edge sensitive The interrupt is level sensitive when this bit is low PLTY Polarity When this bit is low interrupt is activated by a rising edge high level of the LANC INT pin When this bit is high interrupt is activated by a...

Page 234: ...t is being generated at the level programmed in IL2 IL0 if nonzero SC1 SC0 Snoop Control These control bits determine the value that the PCCchip2 drives onto the local MC68040 bus SC1 and SC0 pins when the 82596CA LANC performs DMA accesses During LANC DMA if bit SC0 is 0 Local Bus pin SC0 is low and when bit SC0 is 1 pin SC0 is high The same relationship holds true for bit and pin SC1 See the M68...

Page 235: ...to the Local Bus A Local Bus error condition is flagged by the assertion of TEA When the SCSI processor receives TEA If the source of the error is local time out then LTO is set and EXT and PRTY are cleared If the source of the TEA is due to an error in going to the VMEbus then EXT is set and the other two status bits are cleared If the source of the error is DRAM parity check error then PRTY is s...

Page 236: ...interrupt is disabled when this bit is low IRQ Interrupt Status This status bit reflects the state of the IRQ pin of the SCSI Processor qualified by the IEN bit When this bit is high a SCSI processor interrupt is being generated at the level programmed in IL2 IL0 if nonzero This status bit does not need to be cleared because it is not edge sensitive ADR SIZ FFF4202F 8 bits BIT 7 6 5 4 3 2 1 0 NAME...

Page 237: ...d when this bit is low INT When this bit is high a printer ACK interrupt is being generated at the level programmed in IL2 IL0 if nonzero E L When this bit is high the interrupt is edge sensitive The interrupt is level sensitive when this bit is low PLTY When this bit is low interrupt is activated by a falling edge low level on the PRACKI pin When this bit is high interrupt is activated by a risin...

Page 238: ... being generated at the level programmed in IL2 IL0 if nonzero E L When this bit is high the interrupt is edge sensitive The interrupt is level sensitive when this bit is low PLTY When this bit is low interrupt is activated by a falling edge low level of the PRFAULTI pin When this bit is high interrupt is activated by a rising edge high level of the PRFAULTI pin Note that if this bit is changed wh...

Page 239: ...rrupt is being generated at the level programmed in IL2 IL0 if nonzero E L When this bit is high the interrupt is edge sensitive The interrupt is level sensitive when this bit is low PLTY When this bit is low interrupt is activated by a rising edge high level of the SEL pin When this bit is high interrupt is activated by a falling edge low level of the SEL pin Note that if this bit is changed whil...

Page 240: ...rupt is being generated at the level programmed in IL2 IL0 if nonzero E L When this bit is high the interrupt is edge sensitive The interrupt is level sensitive when this bit is low PLTY When this bit is low interrupt is activated by a rising edge high level of the PE pin When this bit is high interrupt is activated by a falling edge low level of the PE pin Note that if this bit is changed while t...

Page 241: ...rupt is being generated at the level programmed in IL2 IL0 if nonzero E L When this bit is high the interrupt is edge sensitive The interrupt is level sensitive when this bit is low PLTY When this bit is low interrupt is activated by a rising edge high level of the BUSY pin When this bit is high interrupt is activated by a falling edge low level of the BUSY pin Note that if this bit is changed whi...

Page 242: ... and 0 when SELECT is low FLT This bit reflects the state of the Printer Fault input pin It is 1 when FAULT is low and 0 when FAULT is high ACK This bit reflects the state of the Printer Acknowledge input pin It is 1 when ACK is low and 0 when ACK is high PINT Printer Interrupt Status When this bit is high an interrupt is being generated at the level programmed in one or more of the Printer Interr...

Page 243: ... 50 BCLK periods 2 5 µs at 20MHz 2 µs at 25MHz and 1 5 µs at 33MHz Note that the strobe time is the width of the low going pulse generated on the STB pin Also note that after a write to the Printer Data Register the PCCchip2 delays about one strobe time before issuing the STB pulse This bit is not used in manual mode Note The PCCchip2 runs at half the MPU speed on the MVME177P For example an MVME1...

Page 244: ...g of the printer input prime signal DOEN Printer Data Output Enable This bit controls the external data buffer for the printer port When this bit is high the external printer data buffer is enabled When this bit is low the external printer data buffer is disabled For normal connection to a printer DOEN should be set to 1 Chip Speed Register CS31 CS16 This read only register is for factory test pur...

Page 245: ...ation FFF4203B or PD15 PD0 can be accessed as a 16 bit register at location FFF4203A In auto mode writing these bits also generates the strobe for the printer Reading these bits causes the PCCchip2 to read the data from the printer data signal lines no strobe is generated When the DOEN bit is set the printer data signal lines are driven by the external printer data buffer When the DOEN bit is clea...

Page 246: ...C040 bit is cleared external devices can drive EIPL2 EIPL0 with their interrupt requests When C040 is set the PCCchip2 drives EIPL2 EIPL0 with its interrupt requests In this case C040 set IPL2 IPL0 only reflect PCCchip2 interrupt requests The IPL bits are encoded as shown below ADR SIZ FFF4203E 8 bits BIT 15 14 13 12 11 10 9 8 NAME IPL2 IPL1 IPL0 OPER R R R R R R R R RESET 0 0 0 0 0 X X X IPL2 IPL...

Page 247: ...vel which must be exceeded by IPL2 IPL0 in order for the PCCchip2 to assert its INT pin The MSK bits are encoded as follows ADR SIZ FFF4203F 8 bits BIT 7 6 5 4 3 2 1 0 NAME MSK2 MSK1 MSK0 OPER R R R R R R W R W R W RESET 0 0 0 0 0 1 PL 1 PL 1 PL MSK2 MSK1 MSK0 Priority Level Comments 0 0 0 0 Lowest Level 0 0 1 1 0 1 0 2 0 1 1 3 1 0 0 4 1 0 1 5 1 1 0 6 1 1 1 7 Highest Level ...

Page 248: ...3 50 Computer Group Literature Center Web Site PCCchip2 3 ...

Page 249: ...tion developed for earlier boards the structure of this manual preserves the functional distinctions that formerly characterized the MCECC ASIC This chapter describes the Petra chip as used in the MVME1x7 MCECC implementation The MCECC ASICs used in a set of two provided the interface to a 144 bit wide DRAM memory array The Petra implementation provides an interface to a 40 bit SDRAM memory array ...

Page 250: ...ccesses sustained for burst reads 5 1 1 1 with BERR on or when FSTRD is cleared Support for byte two byte four byte and cache line read or write transfers Programmable base address for DRAM Built in refresh timer and refresh controller Programmable period automatic scrub operation Error Handling ECC Single Bit Error Detect and Correct Software enabled Interrupt on Single Bit Error Double Bit Error...

Page 251: ...orrects the error This prevents soft single bit errors from becoming double bit errors Performance The Petra MCECC sector maintains tags for each internal bank of SDRAM Each bank may be in an active or idle state SDRAM access time is a function of the state of the bank of memory being addressed If the bank addressed is active performance is additionally a function of the page of memory being refer...

Page 252: ...in applications Cache Coherency The MCECC sector supports the MC680x0 caching scheme on the local bus by always providing 32 bits of valid data during DRAM read cycles regardless of the number of bytes requested by the local bus master for the cycle It also supports cache coherency by monitoring the memory inhibit MI signal For a write or read cycle the MCECC sector always waits for MI to be negat...

Page 253: ...ead modify write accesses but longword write accesses require no read cycle Error Reporting The Petra MCECC sector generates ECC check bits for write cycles It also checks read data from the DRAM and corrects the data if it contains a single bit error If a non correctable error occurs within the read data the Petra MCECC sector so indicates by asserting its non correctable error NCE pin The follow...

Page 254: ...led the same as a double bit error The rest may show up as no error or single bit error both of which are incorrect Cycle Type Burst Write Because all of the bits are written during a burst write no checking is done Single Bit Error Cycle Type Non Burst Write 1 Correct the data read from the DRAM merge with the write data and write the correct merged data to the DRAM 2 Terminate the cycle normally...

Page 255: ... corrected data to the DRAM 2 Log the error if not already logged 3 Notify the local MPU via interrupt if so enabled Double Bit Error Cycle Type Scrub 1 Do not perform the write portion of the cycle This causes the location to continue to indicate a non correctable error when accessed 2 Log the error if not already logged 3 Notify the local MPU via interrupt if so enabled Triple or Greater Bit Err...

Page 256: ...ing function Programmable registers determine how often the entire DRAM is scrubbed During a scrub the scrubber holds the memory for a programmable amount of time and then releases it for the local bus or for a refresher if one of them is requesting local bus mastership The scrubber then refrains from using the DRAM again for a programmable amount of time Each scrub cycle is made up of a full 39 b...

Page 257: ...perates on a priority basis it also performs a pseudo round robin algorithm in order to prevent starving any of the requesting entities Chip Defaults Certain parameters in the Petra MCECC sector have to be configured These include DRAM size DRAM speed Control and Status register selection etc The configuration parameters are loaded into the Defaults 1 Defaults 2 and SDRAM Configuration registers o...

Page 258: ...t were also defined as to their original intent This specification entirely omits those bit definitions The possible operations for each bit in the CSR are as follows The possible states of the bits after local software and power up reset are as defined below R The bit is a read only status bit R W The bit is readable and writable R C This status bit is cleared by writing a 1 to it C Writing a 0 t...

Page 259: ...BASE ADDRESS BAD31 BAD30 BAD29 BAD28 BAD27 BAD26 BAD25 BAD24 18 DRAM CONTROL BAD23 BAD22 RWB5 RWB4 RWB3 NCEIEN NCEBEN RAMEN 1C BCLK FREQUENCY BCK7 BCK6 BCK5 BCK47 BCK3 BCK2 BCK1 BCK0 20 DATA CONTROL 0 0 DERC ZFILL RWCKB 0 0 0 24 SCRUB CONTROL 0 0 0 SCRB SCRBEN 0 SBEIEN RWB0 28 SCRUB PERIOD SBPD15 SBPD14 SBPD13 SBPD12 SBPD11 SBPD10 SBPD9 SBPD8 2C SCRUB PERIOD SBPD7 SBPD6 SBPD5 SBPD4 SBPD3 SBPD2 SBP...

Page 260: ...1 SAC10 SAC9 SAC8 58 SCRUB ADDR CNTR SAC7 SAC6 SAC5 SAC4 07 0 0 0 5C ERROR LOGGER ERRLOG ERD ESCRB ERA EALT 0 MBE SBE 60 ERROR ADDRESS EA31 EA30 EA29 EA28 EA27 EA26 EA25 EA24 64 ERROR ADDRESS EA23 EA22 EA21 EA20 EA19 EA18 EA17 EA16 68 ERROR ADDRESS EA15 EA14 EA13 EA12 EA11 EA10 EA9 EA8 6C ERROR ADDRESS EA7 EA6 EA5 EA4 07 0 0 0 70 ERROR SYNDROME S7 S6 S5 S4 S3 S2 S1 S0 74 DEFAULTS1 RWB7 RWB6 FSTRD ...

Page 261: ...ctor always terminates the cycles properly with TA Chip Revision Register The Chip Revision register is hard wired to reflect the revision level of the Petra MCECC ASIC The current value of the register is 01 Although writes to this register are ignored the MCECC sector pair always terminates the cycles properly with TA ADR SIZ 1st FFF43000 2nd FFF43100 8 bits BIT 31 30 29 28 27 26 25 24 NAME CID7...

Page 262: ...ng models For the actual SDRAM device and size options now applicable to the MVME1x7P boards refer to Table 1 1 FSTRD FSTRD reflects the state of the FSTRD bit in Defaults Register 1 When 1 this bit indicates that DRAM reads are operating at full speed When 0 it indicates that DRAM read accesses are slowed by one clock cycle ADR SIZ 1st FFF43008 2nd FFF43108 8 bits BIT 31 30 29 28 27 26 25 24 NAME...

Page 263: ...s control bit is used to enable the local bus to perform read write accesses to the memory Accesses are enabled when this bit is set and are disabled when this bit is cleared This bit should only be set after BAD31 BAD22 have been initialized ADR SIZ 1st FFF43014 2nd FFF43114 8 bits BIT 31 30 29 28 27 26 25 24 NAME BAD31 BAD30 BAD29 BAD28 BAD27 BAD26 BAD25 BAD24 OPER R W R W R W R W R W R W R W R ...

Page 264: ...WB5 Read Write Bit 5 is a general purpose read write bit BAD22 BAD23 These are the lower two bits of the DRAM base address described in the previous register BCLK Frequency Register The Bus Clock BCLK Frequency register should be programmed with the hexadecimal value of the operating clock frequency in MHz i e 19 for 25MHz and 21 for 33MHz The MCECC sector pair uses the value programmed in this re...

Page 265: ...unction the scrubber may correct the location before the test software gets a chance to check for the single bit error at that location This can be avoided by disabling scrubbing and making sure that all previous scrubs have completed before performing the test Also note that writing bad checkbits can set the ERRLOG bit in the Error Logger register ADR SIZ 1st FFF4301C 2nd FFF4311C 8 bits BIT 31 3...

Page 266: ...red testing related to the location locations that have had their checkbits altered 6 Allow the scrubber to proceed by restoring the STON and STOFF bits to their original state ZFILL ZERO FILL memory when set forces all zeros to be written to the DRAM during any kind of write cycle or scrub cycle It is intended for use with the zero fill function refer to the section on Initialization at the end o...

Page 267: ...re DRAM array When the scrub is complete if software has cleared SCRBEN then scrubbing is not done again until software sets the SCRBEN bit If software has not cleared the SCRBEN bit then when the amount of time indicated in the Scrub Period SBPD register expires the MCECC sector scrubs the DRAM array again It continues to perform scrubs of the entire DRAM array at the frequency indicated in the S...

Page 268: ...ed into the Scrub Period register The scrub period can be programmed from once every four seconds to once every 36 hours This register contains bits 15 8 of the Scrub Period register Scrub Period Register Bits 7 0 This register contains bits 7 0 of the Scrub Period register ADR SIZ 1st FFF43028 2nd FFF43128 8 bits BIT 31 30 29 28 27 26 25 24 NAME SBPD15 SBPD14 SBPD13 SBPD12 SBPD11 SBPD10 SBPD9 SBP...

Page 269: ...me On Time Off Register STOFF2 STOFF0 STOFF2 STOFF0 control the amount of time that the scrubber refrains from requesting use of the DRAM each time it gives it up during a scrub They control the off time as follows ADR SIZ 1st FFF43030 2nd FFF43130 8 bits BIT 31 30 29 28 27 26 25 24 NAME CPS7 CPS6 CPS57 CPS4 CPS3 CPS2 CPS1 CPS0 OPER R W R W R W R W R W R W R W R W RESET 0 P 0 P 0 P 0 P 0 P 0 P 0 P...

Page 270: ... 16 BCLK cycles 0 1 0 Request DRAM after 32 BCLK cycles 0 1 1 Request DRAM after 64 BCLK cycles 1 0 0 Request DRAM after 128 BCLK cycles 1 0 1 Request DRAM after 256 BCLK cycles 1 1 0 Request DRAM after 512 BCLK cycles 1 1 1 Request DRAM never STON2 STON1 STON0 Scrubber Time On 0 0 0 Keep DRAM for 1 memory cycle 0 0 1 Keep DRAM for 16 BCLK cycles 0 1 0 Keep DRAM for 32 BCLK cycles 0 1 1 Keep DRAM ...

Page 271: ...aler The ability to read and write to the scrub prescaler is provided for test purposes Programming this counter is not recommended This register reflects the current value in the scrub prescaler bits 21 16 Scrub Prescaler Counter Bits 15 8 This register reflects the current value in the scrub prescaler bits 15 8 ADR SIZ 1st FFF43038 2nd FFF43138 8 bits BIT 31 30 29 28 27 26 25 24 NAME 0 0 SPS21 S...

Page 272: ... Writes to this address update the Scrub Timer counter and reads to this address yield the counter s value The ability to read and write this register is provided for test purposes Programming this counter is not recommended This register reflects the current value in the Scrub Timer counter bits 15 8 ADR SIZ 1st FFF43040 2nd FFF43140 8 bits BIT 31 30 29 28 27 26 25 24 NAME SPS7 SPS6 SPS5 SPS4 SPS...

Page 273: ... reads to this address yield the value in the counter The ability to read and write this counter is provided for test purposes Note that if scrubbing is in process the Scrub Time On Time Off register should be set for the minimum time on and the maximum time off during any writes to this register This register reflects the current value in the Scrub Address counter bits 26 24 ADR SIZ 1st FFF43048 ...

Page 274: ... 7 4 ADR SIZ 1st FFF43050 2nd FFF43150 8 bits BIT 31 30 29 28 27 26 25 24 NAME SAC23 SAC22 SAC21 SAC20 SAC19 SAC18 SAC17 SAC16 OPER R W R W R W R W R W R W R W R W RESET 0 PLS 0 PLS 0 PLS 0 PLS 0 PLS 0 PLS 0 PLS 0 PLS ADR SIZ 1st FFF43054 2nd FFF43154 8 bits BIT 31 30 29 28 27 26 25 24 NAME SAC15 SAC14 SAC13 SAC12 SAC11 SAC10 SAC9 SAC8 OPER R W R W R W R W R W R W R W R W RESET 0 PLS 0 PLS 0 PLS 0...

Page 275: ...MCECC sector EALT EALT indicates that the last logging of an error occurred on a DRAM access by an alternate MI not asserted local bus master ESCRB ESCRB indicates the entity that was accessing DRAM at the last logging of a single or double bit error If ESCRB is 1 it indicates that the scrubber was accessing DRAM If ESCRB is 0 it indicates that the local MC680x0 bus master was accessing DRAM ERD E...

Page 276: ... in either MCECC should be recovered before clearing ERRLOG Error Address Bits 31 24 This register reflects the value that was on bits 31 24 of the local MC680x0 address bus at the last logging of an error Error Address Bits 23 16 This register reflects the value that was on bits 23 16 of the local MC680x0 address bus at the last logging of an error ADR SIZ 1st FFF43060 2nd FFF43160 8 bits BIT 31 ...

Page 277: ...ster reflects the value that was on bits 7 4 of the local MC680x0 bus at the last logging of an error ADR SIZ 1st FFF43068 2nd FFF43168 8 bits BIT 31 30 29 28 27 26 25 24 NAME EA15 EA14 EA13 EA12 EA11 EA10 EA9 EA8 OPER R R R R R R R R RESET 0 PLS 0 PLS 0 PLS 0 PLS 0 PLS 0 PLS 0 PLS 0 PLS ADR SIZ 1st FFF4306C 2nd FFF4316C 8 bits BIT 31 30 29 28 27 26 25 24 NAME EA7 EA6 EA5 EA4 0 0 0 0 OPER R R R R ...

Page 278: ...efaults Register 1 It is not recommended that non test software write to this register RSIZ2 RSIZ0 Bits RSIZ2 RSIZ0 determine the size of the DRAM array that is assumed by the MCECC They control the size as follows ADR SIZ 1st FFF43070 2nd FFF43170 16 bits BIT 31 30 29 28 27 26 25 24 NAME 0 S6 S5 S4 S3 S2 S1 S0 OPER R R R R R R R R RESET 0 PLS 0 PLS 0 PLS 0 PLS 0 PLS 0 PLS 0 PLS 0 PLS ADR SIZ 1st ...

Page 279: ...re initialized by hardware after a power up soft or local reset Their initialized state is determined by board level configuration resistors FSTRD The FSTRD control bit determines the speed at which SDRAM reads occur When it is 1 SDRAM reads happen at full speed When it is 0 SDRAM reads are slowed by one clock unless they are already slowed by NCEBEN RSIZ2 RSIZ1 RSIZ0 DRAM Array Size 0 0 0 4MB 0 0...

Page 280: ...al purpose read write bit Defaults Register 2 It is not recommended that non test software write to this register RESST2 RESST0 These general purpose read write bits are initialized by a power up soft or local reset to match the RESST2 RESST0 bits from the reset serial bit stream ADR SIZ 1st FFF43078 2nd FFF43178 8 bits BIT 31 30 29 28 27 26 25 24 NAME 0 0 0 0 0 RESST2 RESST1 RESST0 OPER R W R W R...

Page 281: ...PLS V PLS V PLS SDCFG2 SDCFG1 SDCFG0 DRAM Array Size 0 0 0 SDRAM device is 64MBit x 16 data with one bank composed of 3 devices 0 0 1 SDRAM device is 64MBit x 8 data with one bank composed of 5 devices 0 1 0 SDRAM device is 64MBit x 8 data with two banks composed of 5 devices each 0 1 1 SDRAM device is 64MBit x 8 data with four banks composed of 5 devices each 1 0 0 SDRAM device is 128MBit x 8 dat...

Page 282: ...the DRAM to consume too much power at full speed 1 Make sure that the scrubber is disabled by clearing the SCRBEN bit in the Scrub Control register Clear bit 27 of offset 24 2 Make sure that the scrubber is done with any old scrub cycles by waiting for the SCRB bit in the Scrub Control register to be cleared Wait for bit 28 of offset 24 0 3 Discontinue all accesses from the MC680x0 bus to the DRAM...

Page 283: ...10 Wait for the zero fill to complete by waiting for the SCRB bit in the Scrub Control register to be cleared Wait for bit 28 of offset 24 0 11 Clear the ZFILL bit in the MCECC pair Clear Bit 28 of offset 20 12 The entire DRAM that is controlled by this MCECC is now zero filled The software can now program the appropriate scrubbing mode and other desired initialization and enable DRAM for operatio...

Page 284: ... table Table 4 4 Syndrome Bit Encoding Bit in Error Syndrome Code Bit in Error Syndrome Code Bit 0 4F Bit 16 0E Bit 1 4A Bit 17 0B Bit 2 52 Bit 18 13 Bit 3 54 Bit 19 15 Bit 4 57 Bit 20 16 Bit 5 58 Bit 21 19 Bit 6 5B Bit 22 1A Bit 7 5D Bit 23 1C Bit 8 23 Bit 24 62 Bit 9 25 Bit 25 64 Bit 10 26 Bit 26 67 Bit 11 29 Bit 27 68 Bit 12 2A Bit 28 6B Bit 13 2C Bit 29 6D Bit 14 31 Bit 30 70 Bit 15 34 Bit 31 ...

Page 285: ...k where the error originated Table 4 5 Identifying SDRAM Bank in Error SDCFG2 SDCFG1 SDCFG0 DRAM Array Size and Bank with the Error 0 0 0 Device is 64Mbit x 16 data with one bank composed of 3 devices 0 0 1 Device is 64Mbit x 8 data with one bank composed of 5 devices 0 1 0 Device is 64Mbit x 8 data with two banks composed of 5 devices each If EA24 0 Bank 0 If EA24 1 Bank 1 0 1 1 Device is 64Mbit ...

Page 286: ...4 38 Computer Group Literature Center Web Site MCECC Functions 4 ...

Page 287: ...mplementation MVME1x2P2 Implementation MCECC memory control MCECC ASIC revision 00 Petra ASIC revision 02 page 3 12 DRAM DRAM with parity or ECC protection MVME167 DRAM with ECC protection MVME177 SDRAM with ECC protection page 1 2 Ethernet interface N82C501AD device LXT901 device software transparent EEPROM sockets Through hole 44 pin PLCC Surface mount 44 pin PLCC Serial interface MC14506 device...

Page 288: ...A 2 Computer Group Literature Center Web Site Summary of Changes A ...

Page 289: ...or the MVME712M Connection Diagrams The following figures illustrate the connection diagrams for the MVME712M transition module Figure Number Name Figure B 1 MVME167P 177P Printer Port with MVME712M Figure B 2 MVME167P 177P Serial Port 1 Configured as DCE Figure B 3 MVME167P 177P Serial Port 2 Configured as DCE Figure B 4 MVME167P 177P Serial Port 3 Configured as DCE Figure B 5 MVME167P 177P Seria...

Page 290: ...03 MVME167P MVME177P LS244 ENBA LEBA OEAB ENAB LEAB ENBA OEBA A A A A A A A A SAD 0 SAD 1 SAD 2 SAD 3 SAD 4 SAD 5 SAD 6 SAD 7 B B B B B B B B LS244 LS244 LS244 LS244 LS244 LS244 2 3 4 5 6 7 8 9 1 31 13 10 11 12 32 PCCCHIP2 9P F543 PRRE PDEN PRWE PRSTB PRINP PRSEL PRACK PRBSY PRPE PRFLT P2 ADAPTER BOARD 64 COND CABLE MVME712M 36 PIN RIBBON ...

Page 291: ...erial Port 1 Configured as DCE 1348 9403 MVME167P MVME177P P2 ADAPTER BOARD 64 COND CABLE DB25 CD2401 DTR0 RXD0 CD0 CTS0 TXD0 34 85 54 1 5K MC145406 D D MC145406 C23 C25 MC145406 MC145406 C24 C26 55 39 R R MVME712 TRANSITION BOARD 1 5K 1 5K 12V 12V 3 8 5 6 7 2 4 RXD DCD CTS DSR GND TXD RTS ...

Page 292: ...ort 2 Configured as DCE MC145406 D C27 40 3 RXD MC145406 D C31 60 8 DCD MC145406 D C29 59 5 CTS 1349 9403 MVME167P MVME177P P2 ADAPTER BOARD 64 COND CABLE DB25 CD2401 RXD1 35 MC145406 C28 R MVME712 TRANSITION BOARD 1 5K 12V 6 7 2 4 DSR GND TXD RTS CD1 11 MC145406 C32 R 20 DTR CTS1 58 MC145406 C30 R DTR1 RTS1 TXD1 ...

Page 293: ...nfigured as DCE MC145406 D A19 41 3 RXD MC145406 D A23 65 8 DCD MC145406 D A21 64 5 CTS 1350 9403 MVME167P MVME177P P2 ADAPTER BOARD 64 COND CABLE DB25 CD2401 RXD2 36 MC145406 A20 R MVME712 TRANSITION BOARD 1 5K 12V 6 7 2 4 DSR GND TXD RTS CD2 18 MC145406 A24 R 20 DTR CTS2 63 MC145406 A22 R DTR2 RTS2 TXD2 ...

Page 294: ...8 DCD MC145406 D A27 68 5 CTS 1351 9403 MVME167P MVME177P P2 ADAPTER BOARD 64 COND CABLE DB25 CD2401 RXD3 38 MC145406 A26 R MVME712 TRANSITION BOARD 1 5K 12V 6 7 2 4 DSR GND TXD RTS CD3 22 MC145406 A31 R 20 DTR CTS3 67 MC145406 A29 R DTR3 RTS3 TXD3 A32 15 RTXC A28 RRXC TTXC J15 1 TRXC4 RTXC4 MC145406 D D R R MC145406 MC145406 MC145406 J6 J7 1 1 TXCO3 RXCI3 TXCI3 47 51 52 17 24 ...

Page 295: ...1X7P Serial Port 1 Configured as DTE 1352 9403 MVME167P MVME177P P2 ADAPTER BOARD 64 COND CABLE DB25 CD2401 DTR0 RXD0 CD0 CTS0 TXD0 34 85 54 1 5K MC145406 D D MC145406 C23 C25 MC145406 MC145406 C24 C26 55 39 R R MVME712 TRANSITION BOARD 1 5K 12V 2 20 4 7 3 5 TXD DTR RTS GND RXD CTS 9P ...

Page 296: ...ial Port 2 Configured as DTE MC145406 D C27 40 2 TXD MC145406 D C31 60 20 DTR MC145406 D C29 59 4 RTS 1353 9403 MVME167P MVME177P P2 ADAPTER BOARD 64 COND CABLE DB25 CD2401 RXD1 35 MC145406 C28 R MVME712 TRANSITION BOARD 7 3 5 GND RXD CTS CD1 11 MC145406 C32 R 8 DCD CTS1 58 MC145406 C30 R DTR1 RTS1 TXD1 11P ...

Page 297: ...t 3 Configured as DTE MC145406 D A19 41 2 TXD MC145406 D A23 65 20 DTR MC145406 D A21 64 4 RTS 1354 9403 MVME167P MVME177P P2 ADAPTER BOARD 64 COND CABLE DB25 CD2401 RXD2 36 MC145406 A20 R MVME712 TRANSITION BOARD 7 3 5 GND RXD CTS CD2 18 MC145406 A24 R 8 DCD CTS2 63 MC145406 A22 R DTR2 RTS2 TXD2 9P ...

Page 298: ... A30 69 20 DTR MC145406 D A27 68 4 RTS 1355 9403 MVME167P MVME177P P2 ADAPTER BOARD 64 COND CABLE DB25 CD2401 RXD3 38 MC145406 A26 R MVME712 TRANSITION BOARD 7 3 5 GND RXD CTS CD3 22 MC145406 A31 R 8 DCD CTS3 67 MC145406 A29 R DTR3 RTS3 TXD3 A32 15 RTXC A28 RRXC TTXC J15 1 TRXC4 RTXC4 MC145406 D D R R MC145406 MC145406 MC145406 J6 J7 1 1 TXCO3 RXCI3 TXCI3 47 51 52 17 24 ...

Page 299: ...Motorola Computer Group Documents Document Title Motorola Publication Number MVME167P Single Board Computer Installation and Use V167PA IH MVME177P Single Board Computer Installation and Use V177PA IH MVME167Bug Debugging Package User s Manual MVME167BUG MVME177Bug Debugging Package User s Manual MVME177BUG Debugging Package for Motorola 68K CISC CPUs User s Manual Parts 1 and 2 68KBUG1 D 68KBUG2 ...

Page 300: ...5 2150 E mail ldcformotorola hibbertco com Web http www mot com SPS M68000FR M68060UM 82596CA Local Area Network Coprocessor Data Sheet 82596CA Local Area Network Coprocessor User s Manual 28F016SA Flash Memory Data Sheet Intel Corporation Web http developer intel com design 290218 296853 209435 SYM 53C710 was NCR 53C710 SCSI I O Processor Data Manual SYM 53C710 was NCR 53C710 SCSI I O Processor P...

Page 301: ...pbell CA 95008 6609 Web http www zilog com products Z85230pb pdf Table C 3 Related Specifications Document Title and Source Publication Number VME64 Specification VITA VMEbus International Trade Association 7825 E Gelding Drive Suite 104 Scottsdale AZ 85260 Telephone 602 951 8866 Web http www vita com ANSI VITA 1 1994 NOTE An earlier version of the VME specification is available as Versatile Backp...

Page 302: ...98X Revision 10c Global Engineering Documents 15 Inverness Way East Englewood CO 80112 5704 X3 131 198X Rev 10c Interface Between Data Terminal Equipment and Data Circuit Terminating Equipment Employing Serial Binary Data Interchange EIA 232 D Global Engineering Documents Suite 400 1991 M Street NW Washington DC 20036 Telephone 1 800 854 7179 Telephone 303 397 7956 Web http global ihs com ANSI EIA...

Page 303: ...20 VMEbus resources 2 37 address counter VMEbus 2 13 address modifier codes 2 43 2 44 codes DMAC 2 58 register VMEbus slave 2 38 select bits 2 33 2 36 address range devices 1 20 local bus 2 39 address translation address register 2 38 address register slave map decoder 2 27 registers 2 38 registers slave map decoder 2 27 select register 2 38 select register slave map decoder 2 27 address translati...

Page 304: ...FAIL signal pin VMEchip2 ASIC 2 70 2 71 broadcast interrupt function VMEchip2 timers 2 15 broadcast mode VMEbus 2 16 BSY signal and arbitration timer 2 17 burst read cycle type 4 5 burst write cycle type 4 6 bus error 3 4 processing 1 55 sources 1 54 status SCSI 3 37 bus map decoder LCSR 2 20 bus sizing VMEchip2 ASIC 2 6 bus timer local 1 17 bus timer enable disable VMEbus 2 17 bus timers example ...

Page 305: ...s normal address range 1 20 DFAIR bit 2 14 differences from previous boards A 1 direct mode DMAC 2 51 PCCchip2 ASIC 3 7 DMA and serial interface 1 14 transfers no address increment 2 12 DMA Controller DMAC VMEchip2 ASIC 2 10 2 51 DMAC command packets 2 52 interrupter VMEbus 2 19 LTO error 1 58 offboard error 1 58 parity error 1 57 TEA cause unidentified 1 59 VMEbus error 1 57 VMEbus requester 2 13...

Page 306: ...s VMEbus 2 34 2 37 F fair mode VMEchip2 2 8 2 14 fast read bit status 4 14 features MCECC sector 4 1 MVME1X7P 1 3 PCCchip2 ASIC 3 1 VMEchip2 ASIC 2 1 Flash memory devices 1 8 1 9 functional description 1 17 VMEchip2 ASIC 2 4 G GCSR base address registers programming 2 37 board address 2 48 group address 2 47 map decoder 1 46 programming model 2 100 SIG3 0 interrupters VMEbus 2 19 GCSR global contr...

Page 307: ...t 3 40 printer paper error 3 42 printer select 3 41 tick timer 1 3 26 tick timer 2 3 25 interrupt acknowledge map 1 46 base vectors VMEbus 2 95 control register VMEchip2 2 101 counter DMAC 2 62 handler routine how to set up 1 49 mask level 3 49 interrupt enable GPIO 3 24 LANC bus error 3 36 LANC interrupt 3 35 printer acknowledge 3 39 printer busy 3 43 printer fault 3 40 printer paper error 3 42 p...

Page 308: ...74 hardware 1 17 how to use 1 47 LANC 3 5 masked 2 96 tick timer example 1 47 IRQ1 interrupter VMEbus 2 19 IRQ7 1 interrupters VMEbus 2 19 L LAN controller interface 3 3 interface 1 14 LTO error 1 62 offboard error 1 61 parity error 1 61 LANC bus error 3 4 Bus Error Interrupt Control register PCCchip2 ASIC 3 36 Error Status register PCCchip2 ASIC 3 34 interrupts 3 5 LCSR base address 2 20 memory m...

Page 309: ...and status segisters LCSRs VMEbus 2 7 local I O devices memory map 1 22 local reset driver VMEbus 2 18 local reset VMEbus 2 18 local SCSI ID 1 45 local bus to VMEbus Enable Control register 2 49 I O Control register 2 50 interface 1 18 interface VMEchip2 2 4 map decoders programming 2 37 requester 2 7 requester register programming 2 51 location monitor interrupters VMEbus 2 19 status register VME...

Page 310: ...ible 1 52 memory devices used on board 1 3 memory maps 82596CA Ethernet LAN coprocessor 1 40 BBRAM configuration area 1 42 BBRAM TOD clock 1 41 Cirrus Logic CD2401 serial controller chip 1 36 interrupt acknowledge 1 46 local bus 1 20 local I O devices 1 22 M48T58 BBRAM TOD Clock 1 42 MCECC internal register 1 34 MCECC sector internal registers 4 11 PCCchip2 1 32 PCCchip2 ASIC 3 10 printer 1 31 SCS...

Page 311: ...rs 3 18 SCC Error Status register and Interrupt Control registers 3 27 SCSI controller interface 3 6 tick timer support 1 16 3 9 Vector Base register 3 16 periodic interrupt example 1 47 periodic interrupts PCCchip2 ASIC 3 18 Petra ASIC functionality of 1 2 redundancies with VMEchip2 1 18 PIACK register modem 3 31 polarity GPIO 3 24 LANC interrupt 3 35 printer acknowledge 3 39 printer busy 3 43 pr...

Page 312: ...51 tick and watchdog timers VMEchip2 2 64 tick timers PCCchip2 ASIC 3 18 VMEbus interrupter 2 51 VMEbus slave map decoders 2 26 programming issues 1 2 programming model MCECC sector 4 10 PCCchip2 ASIC 3 11 VMEchip2 GCSR 2 100 VMEchip2 LCSR 2 20 PROM EPROM sockets 1 3 pseudo interrupt acknowledge PIACK cycles 3 8 3 32 3 33 R receive interrupt SCC 3 30 vector bits 3 33 Receive PIACK register PCCchip...

Page 313: ... 4 5 size VMEbus segment 2 30 2 31 slave map decoders VMEbus 2 26 snoop control 3 4 SCC receive 3 30 snoop control bits 2 53 snoop control register 2 32 snoop control LANC bus error 3 36 snoop function enabling 2 28 2 32 2 35 snoop signal lines DMAC 2 58 snooping definition of 1 49 2 10 software 7 0 interrupters VMEbus 2 19 software interrupts 1 3 specifications applicable industry standards 1 4 M...

Page 314: ... 2 68 Tick Timer 2 Compare register 2 69 Tick Timer 2 Control register 2 72 Tick Timer 2 counter 2 69 VME Access Local Bus and Watchdog Time Out Control register 2 66 VMEbus Arbiter Time Out Control register 2 64 VMEbus global time out timer 2 65 Watchdog Timer Control register 2 71 timers 1 3 local bus 1 51 VMEbus 2 7 transfer mode VMEbus 2 12 Transfer Type TT signals 1 20 transfer types PCCchip2...

Page 315: ...Address Register 2 48 GCSR Group Address Register 2 47 Starting Address Register 1 2 28 Starting Address Register 2 2 29 Write Post and Snoop Control Register 1 2 35 Write Post and Snoop Control Register 2 2 32 VMEbus to local bus interface 1 18 2 9 VMEchip2 ASIC 1 12 BERR signal 1 55 block diagram 2 5 features 2 1 functional blocks 2 4 functional description 2 4 GCSR programming model 2 100 progr...

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Motorola MVME1X7P, Programmer'S Reference Manual, Page: 89 / 316

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