
Memory Maps
http://www.motorola.com/computer/literature
1-37
1
Bit Rate and Clock Option Registers
Receive Frame Address Register1
RFAR1
1F
B
R/W Sync
Receive Frame Address Register2
RFAR2
1E
B
R/W Sync
Receive Frame Address Register3
RFAR3
1D
B
R/W Sync
Receive Frame Address Register4
RFAR4
1C
B
R/W Sync
CRC Polynomial Select Register
CPSR
D6
B
R/W Sync
Receive Baud Rate Period Register
RBPR
CB
B
R/W
Receive Clock Option Register
RCOR
C8
B
R/W
Transmit Baud Rate Period Register
TBPR
C3
B
R/W
Transmit Clock Option Register
TCOR
C0
B
R/W
Channel Command and Status Registers
Channel Command Register
CCR
13
B
R/W
Special Transmit Command Register
STCR
12
B
R/W
Channel Status Register
CSR
1A
B
R
Modem Signal Value Registers
MSVR-
RTS
DE
B
R/W
MSVR-
DTR
DF
B
R/W
Interrupt Registers
Local Interrupt Vector Register
LIVR
09
B
R/W
Interrupt Enable Register
IER
11
B
R/W
Local Interrupting Channel Register
LICR
26
B
R/W
Stack Register
STK
E2
B
R
Receive Interrupt Registers
Receive Priority Interrupt Level Register
RPILR
E1
B
R/W
Receive Interrupt Register
RIR
ED
B
R
Receive Interrupt Status Register
RISR
88
W
(NOTE)
R/W
Table 1-9. Cirrus Logic CD2401 Serial Port Memory Map (Continued)
Base Address = $FFF45000
Register Description
Register
Name
Offsets
Size
Access
Summary of Contents for MVME1X7P
Page 16: ...xvi ...
Page 18: ...xviii ...
Page 20: ...xx ...
Page 26: ...xxvi ...
Page 90: ...1 64 Computer Group Literature Center Web Site Programming Issues 1 ...
Page 248: ...3 50 Computer Group Literature Center Web Site PCCchip2 3 ...
Page 286: ...4 38 Computer Group Literature Center Web Site MCECC Functions 4 ...
Page 288: ...A 2 Computer Group Literature Center Web Site Summary of Changes A ...
Page 316: ...Index IN 14 Computer Group Literature Center Web Site I N D E X ...