Mitsubishi MELSEC QJ71C24, User Manual

Page: 333 / 442

11 - 17 11 - 17
MELSEC-Q
11 TROUBLESHOOTING
(4) Executing the programmable controller CPU information clear
request
(a) Executing from GX Developer
1) On the Device test screen, set "4C43
H
" to buffer memory address 80
H
.
2) On the Buffer Memory Batch monitor screen, check that the value in
buffer memory address 80
H
is "0000
H
".
(b) Executing from GX Configurator-SC
1) Select "Requested" for the PLC CPU information clear request on the
monitor/test others screen, and click Execute test .
2) Confirm that the present value for the PLC CPU information clear
request is "No request".
(c) Executing from sequence program
In the following program, turning on the clear request command clears the
programmable controller CPU information of the Q series C24 that is
mounted in the position corresponding to I/O signal X/Y00 to X/Y1F.
Data communication processing
Clear
request
command
Programmable controller CPU information
clear request
Turns ON the interlock signal for
communication stop during clear
processing.
1
After completing clear processing, turns
OFF the interlock signal for communication
stop.
1
Interlock signal
for communication
stop
\
\
( 1)
1 Create a program in which data communication processing will not be
performed while the interlock signal for communication stop (M100) is ON.
(5) Precautions
(a) Execute the programmable controller CPU information clear after
communication with the external device is stopped.
And, do not perform communication with the external device during the
programmable controller CPU information clear processing. (If any data are
received from the external device during the clear processing, the data will
be discarded.)
(b) When a modem is connected, cut off the line linked with the external device
before executing the programmable controller CPU information clear. (The
line is cut off at execution of the programmable controller CPU information
clear.)
(c) Do not execute the UINI instruction during the programmable controller CPU
information clear.
If the programmable controller CPU information clear is attempted during
execution of the UINI instruction, the clear processing will be executed after
completion of the UINI instruction.