Mallinckrodt NELLCOR NPB-4000, Service Manual

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Section 14: Main Color Board Digital Theory of Operation
14-12
Since the boot flash is for booting up and executing the software program, most
accesses to the boot flash are reads. Only when a new program is downloaded
will a write to the boot flash occur.
14.7.3 TREND FLASH
The trend flash is different. Its purpose is to store the patients data. It has both
read and write accesses occurring at regular intervals. The flash chosen for this
purpose interfaces with the 386EX easily, and writing data consists of
transferring 64 bytes at a time. The flash takes care of any erasing and writing
operations internally. Typical worst case write/erase times for 64 bytes is less
than 1 second.
14.8 LCD DISPLAY
The LCD panel is a color 640x3(RGB)x480 pixel TFT (Thin Film Transistor)
display. The 1354 drives the display through some translation buffers
(74HCT244: U506, U507, U508) because the 1354 operates from the 3.3 volts
DC and the LCD display operates from 5 volts DC.
The LCD display is a single panel display constructed of 640x3x480 dots, which
equals a total of 921,600 pixels. We wanted 4 bits per pixel, therefor we needed
3,686,400 bits of memory to support the display. A 1MX16 EDO DRAM was
chosen because it allowed us to expand to 8 or 16 bits per pixel and it was very
inexpensive. The SED1354 supports either a 50 ns or 60 ns access time DRAM.
The 60 ns access time is used.
The LCD display interfaces to the S-MOS LCD controller chip, SED1354F0A
through some 74HCT244 buffers. This controller chip is connected to the
386EX and one 1MX16 EDO DRAM. The LCD controller has control registers
which must be setup by software before writing to the memory and display. It
also has configuration inputs that will determine the mode of operation at
powerup or reset. The SED1354 is configured in the following. These values
could be changed by adding or removing 10k ohm pull-up resistors on the main
board. (The 1354 has 100k ohm pull-down resistors built inside the chip.)
Pin Name Value of this pin at rising edge of RESET#
MD[0] 0 16 bit CPU data bus interface
MD[3:1] 011 Generic CPU interface
MD[4] 1 Little Endian
MD[5] 0 Active Low Wait
MD[7:6] 01 Symmetric DRAM
MD[8] 1 General Purpose I/O pins
MD[9] 1 General Purpose Output
MD[10] 0 Active high LCDPWR polarity
MD[15:11] Not Used
14.8.1 LCD CONTROL
There are 2 chip selects assigned to the LCD display chip, one for the control
registers inside the chip, and one for the display memory space. The chip itself
has a state machine controller inside, and generates the necessary signals to store
and retrieve data from the memory when requested. It also takes care of driving
the LCD display directly, with the data from the display DRAM.