Mallinckrodt NELLCOR NPB-4000, Service Manual

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Section 14: Main Color Board Digital Theory of Operation
14-10
14.6.2 DRAM FPGA CIRCUITS
The DRAM control circuits in the FPGA must decode the various 386EX control
signals and generate the DRAM signals. This is done by using CS6# to set a flip
flop when ADS# and PH2 are true. When this is true, a flip flop is set, which is
output as RAS#. The output of this flip flop is RAS# which is 75 ns long. This
signal is generated for all DRAM accesses and refresh. The DRAM output is
enabled when either BLE# or BHE# is true, which means a read is occurring.
Since the DRAM outputs are bi-directional, we need to disable the DRAMOE#
signal if a write is taking place. The WR# signal being false allows DRAMOE#
to occur, and if it is true, then the DRAMWR# signal occurs. The BLE# and
BHE# signals are also used to generate the UCAS# and LCAS# signals during a
read or write operation. Since we are using RAS only for refresh, the CAS
signals must be inhibited for refresh.
14.7 FLASH CONTROL
The flash memory and control consists of 2 flash chips, a bootable flash, also
called the executable flash, and a trend flash. The control consists of the random
logic in the FPGA. The bootable flash is a 512Kx16 Intel) flash with the boot in
the top section (T), and is preprogrammed on the data I/O or some other unit
with the boot program. The executable program can also be programmed this
way or by downloading it to the 386EX via the RS-232 connection. The trend
flash consists of Atmel AT29LV256 32kx8 devices which stores the trend data
and which writes 64 bytes at a time. It takes 1 wait state for reading the
executable, 2 wait states for reading the trend, and 4 wait states to write either of
these flashes.
14.7.1 EXECUTABLE FLASH
The executable flash is a word oriented flash, i.e., reading and writing is done on
a word basis, and byte reads and writes are not allowed. The trend flash is byte
oriented and all reads and writes are done on a byte basis.
The chip select unit has UCS* assigned to the executable flash and CS2* is
assigned to the trend flash. Typically, the executable flash is assigned the upper
512 k words, or 1 Megabyte in the system. The word address space is 00000-
7FFFF, which is 00000-FFFFF in bytes. This is the upper portion of the space.
The trend flash is assigned to the 32 k byte space above the video ram, that is,
84000-8FFFF words, or 11000-14000 bytes. The software, however, has the
ability to overlap the trend flash address with the executable flash address. The
design gives priority to the trend flash address over the executable flash.
The read cycle time for the executable flash is 90 ns. The write cycle time must
be at least 100 ns. Refer to the timing diagrams for the flash for minimum
timing parameters.
The executable flash has a delay time of 4 wait states for writing to it.