Mallinckrodt NELLCOR NPB-4000, Service Manual

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Section 13: Microprocessor Computer and Control –Theory of Operation
13-16
13.9.2 Flash FPGA Control Circuit
The FPGA decodes the boot flash and trend flash select signals and generates the
boot flash (FLSH1CE#) signal whenever the trend flash is not being accessed.
Since the trend flash address space may overlap the boot flash space, the trend
flash has priority.
The flash outputs are enabled for a read cycle. During a write cycle, the data bus
inputs data to the flash.
Since the boot flash is for booting up and executing the software program, most
accesses to the boot flash are reads. Only when a new program is downloaded
will a write to the boot flash occur.
13.9.3 Trend Flash
The purpose of the trend flash is to store the patient’s data. It has both read and
write accesses occurring at regular intervals. The flash chosen for this purpose
interfaces with the 386EX easily, and writing data consists of transferring
64 bytes at a time. The flash takes care of any erasing and writing operations
internally. Typical worst-case write/erase times for 64 bytes is less than
1 second.
13.10 LCD Display
The LCD display is a black and white (B&W) 640x480 pixel display, used as a
1-bit/pixel B&W display. Gray shading is not used in this display. It is a dual
panel, dual drive unit and the 1351 drives the display directly. It operates from
3.3 volts.
The LCD display is divided into two sections: each section is 640x240 pixels,
which equals a total of 153,600 pixels per section. A 32Kx8 SRAM has
256,000 bits, thus one SRAM is used for each of the display sections. Only one
bit is available to drive each pixel. For shading or color, more memory is
needed.
The SRAM access time is defined by the 1351FLB as one over the frequency
minus 20 nanoseconds.
tacc = 1/fosc - 20 nanoseconds
Our system uses an oscillator frequency (FOSC) = 10 MHz, therefore,
80 nanoseconds access time on the SRAM is needed. Using this SRAM and
10 MHz, the worst-case access time is 4 TOSC + TCLK = 500 nanoseconds.
The LCD display interfaces to the S-MOS LCD controller chip, SF1351FLB.
This controller chip is connected to the 386EX and two 32kx8 SRAMs. The
LCD controller has control registers that must be set up by software before
writing to the memory and display.