Mallinckrodt NELLCOR NPB-4000, Service Manual

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Section 14: Main Color Board Digital Theory of Operation
14-13
The processor interface consists of the following signals.
CS# is the chip select for the SED1354. It connects directly from the FPGA pin
53 to the SED1345. This signal will go low whenever there is an access by the
386EX to CS0# or CS1#. CS0# relates to the internal registers and CS1# relates
the display DRAM.
M/R# is the signal that distinguishes between a memory or register access.
When M/R# is low, the 386EX is accessing a register. When M/R# is high, the
386EX is accessing the display memory. This pin is connected directly to the
M/IO signal of the 386EX.
RD#, RD/WR#, WE0#, and WE1# are used to read and write to/from the control
registers and the display memory. The 2 read signals (RD# and RD/WR#) are
connected directly from the FPGA. The 2 write signals (WE0#, and WE1# ) are
connected directly from the FPGA. When RD# is low, it indicates that Data Bits
[7:0] are being read from the 1354. When RD/WR# is low, it indicates that Data
Bits [15:8] are being read from the 1354. When both RD# and RD/WR# are
low, it indicates that Data Bits [15:0] are being read from the 1354. When
WE0# is low, it indicates that Data Bits [7:0] are being written to the 1354.
When WE1# is low, it indicates that Data Bits [15:8] are being written to the
1354. When both WE0# and WE1# are low, it indicates that Data Bits [15:0] are
being written to the 1354. RD# is generated by “anding” BLE# and RD# of the
386EX, and it comes out of the FPGA pin 59. RD/WR# is generated by
“anding” BHE# and RD# of the 386EX, and it comes of the FPGA pin 60.
WE0# is generated by “anding” BLE# and WR# of the 386EX, it then gets
synchronized with a flip flop. WE0# is on pin 56 of the FPGA. WE1# is
generated by “anding” BHE# and WR# of the 386EX, it then gets synchronized
with a flip flop. WE1# is on pin 58 of the FPGA.
The CLKI signal is connected to the 40 MHz clock generated by the crystal
oscillator X3. This signal provides the pixel clock and the memory clock The
40 MHz frequency allows the software to vary the LCD refresh rate from 80 Hz
to 120 Hz
The BUSCLK signal is connected to the 40 MHz clock generated by the crystal
oscillator X3. It is the CPU bus clock.
RESET# is connected directly with the RESET# signal from U12 pin 3.
The BS# signal is tied to 3.3 volts DC via a resistor. This pin is suppose to be
pulled up in order to operate in Generic CPU mode.
AB0 of the 1354 is connected to BLE# of the 386EX. AB1-AB20 is connected
to the address bus of the 386EX.
DB0-DB15 is connected to the bi-directional data bus BD0-BD15.
WAIT# is connected to the FPGA pin 141. When this signal is low, it indicates
to the CPU to wait. When this signal goes high data is valid. This signal will be
used by the 386EX. The 386EX will insert 2 wait states automatically and end
the cycle only when WAIT# returns high.