Mallinckrodt NELLCOR NPB-4000, Service Manual

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Section 14: Main Color Board Digital Theory of Operation
14-27
The speaker circuit consists of a software programmable digital potentiometer
chip, U28, which is a Dallas DS1666s-10. The software sets the tone frequency
by setting the high register with a value, the low register with a value, then
programming the digital potentiometer up/down according to the timing
specified in the requirement specification.
14.17.1 FPGA THEORY OF OPERATION
The Actel FPGA is a 3.3 volt, 9000 gate device which contains miscellaneous
control and glue logic for the NPB-4000C. It is packaged in a 176 pin TQFP.
The FPGA contains the following control circuits.
1. DRAM control
2. FLASH control
3. PUSH BUTTON detect
4. RESET/CLOCK PHASE control
5. BIDIRECTIONAL DATA BUFFER control
6. CONTROL REGISTER control
7. READY/ control
8. RTC/DUART state machine/control
9. READ-BACK multiplexer
10. PUMP/VALVE PWM
11. CONTRAST PWM (not used)
12. SPEAKER FREQUENCY generator
13. KNOB detect
14. POWER SUPPLY SYNC ALARM control
15. A/D CONVERTER SERIAL CLOCK control
16. LCD control
14.17.2 DRAM CONTROL CIRCUIT
The DRAM control circuits consist of a small state machine to generate RAS/,
LCAS/, UCAS/,DRAMOE/, WRITE/, CASADREN/, FDRRD, and
ENDTABFR. The process of reading, writing, and refreshing the DRAM is
controlled by these circuits. Each portion of the circuit is described below.
RAS/ (Row Address Strobe) is a 75 ns signal which strobes the row address into
the DRAM. Next, a 50 ns signal called LCAS/ (Lower Column Address Strobe)
and/or UCAS/ (Upper Column Address Strobe) is/are generated which strobes
the column address into the DRAM. Once RAS/ and LCAS/ and/or UCAS/ have
occurred, either a read of the DRAM takes place if DRAMOE/ is true, or a write
to the DRAM takes place if WRITE/ is true. Only one of these last 2 signals can
be true at one time. 25 ns before CAS/ occurs, CASADREN is generated. When
this signal is high the row address is enabled to the DRAM and when it is low
the column address is enabled to the DRAM. The signal ENDTABFR is a low
true signal and enables the data bus buffer on the Mother Board (D5-18055) to
transfer data to or from the 386EX.