Mallinckrodt NELLCOR NPB-4000, Service Manual

Page: 127 / 219

Section 13: Microprocessor Computer and Control –Theory of Operation
13-13
13.8.2 DRAM Timing
T1 T2W T2 T1
25ns 25ns
75ns
50ns
50ns
75ns
75ns
RAS#
RAS#
CLK2
CASADREN
U/LCAS
DRAMWR#
DRAMOE#
Figure 13-8: DRAM Timing
See Figure 13-8. The DRAM requires 130 nanoseconds total time, read/write
and precharge for each cycle. There is one wait state for each DRAM access and
a total of three T states, which is 150 nanoseconds. Since the DRAM minimum
access time is 130 nanoseconds, we have 20 nanoseconds of margin. The
Hitachi HM51W4260AL has a RAS* time of 70 nanoseconds, a precharge time
of 50 nanoseconds, a CAS* time of 20 nanoseconds, and a WE* time of 15
nanoseconds. The BLE* and BLH* signals are used to select byte-oriented
reads and writes. There are two CAS* lines that are used to implement the byte
writes.
The RAS# and CAS# requirements are shown in Figure 13-9.