Mallinckrodt NELLCOR NPB-4000, Service Manual

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Section 14: Main Color Board Digital Theory of Operation
14-31
14.17.9 FLASH WRITE STATE MACHINE
The FLASH write state machine consists of 5 flip flops and is set into action
when CS2/ or UCS/ is low, CLK_PH1 is high ( which indicates the first phase of
the T2 state), WRB/ is low, and BLEORBHE is high indicating a byte or word
transfer. The FLSHWRFF1 signal is set true at the midpoint of T2, which
generates FLASHWRT and WRITE/ on pin 2. The state machine flip flops are
clocked on CLK_PH1 which occurs at the beginning of each T2 state. There are
4 flip flops which gives a 200 ns time, and the FLSHWRT signal gets turned off
at the mid point of the last T2 state, generating a total WRITE/ low pulse of 250
ns. Minimum for either FLASH is 200 ns.
14.17.10 RESET/CLOCK PHASE CLOCK CIRCUITS
When power is turned on, a reset signal is enters on pin 104. The RESETFF is
set true on the next CLK_40MHZ rising clock edge and RESET exits on pin 63.
This is the master reset signal for the whole board and the 386EX. At the same
time it is required to make sure that the control circuits are in sync with the
386EX, and this is done by generating our own phase 1 (CLK_PH1) and phase 2
(CLK_PH2) signals. The CLK_PH1 signal starts as soon as RESET goes low,
and CLK_PH2 always follows CLK_PH1 and is the inverse of CLK_PH1.
These clocks are 50 percent duty cycle clocks running at 20 MHz (50 ns period).
Each T state of the processor is composed of 2 phases or clock states, first
CLK_PH1, then CLK_PH2, and is 50 ns long.
14.17.11 READY/ CIRCUIT
The READY/ circuit is complicated by the fact that either the processor or an
external peripheral can generate the READY/ signal. There are 2 conditions
under which an external READY/ signal can be generated. First was any access
to the LCD controller or memory, and second, when a HALT instruction is
executed. The software programs 2 wait states for any access to the LCD
controller and each access is terminated after the WAIT# signal from the 1354
returns high. The WAIT# signal is connected to pin 141 of the FPGA. The
other remaining circuit requiring and external READY/ is when a HALT
instruction is executed. The HALT AND gate ands D_CB/ low, M_IOB/high,
and W_RB/ high to generate a READY/. The HALT READY/ and LCD WAIT#
are connected through a multiplexer which connects to the 386 READY/. This
READY/ signal comes out on pin 47 of the FPGA.
14.17.12 MICELLANEOUS CLOCK CIRCUITS
The master clock from the 40 MHz oscillator enters the FPGA on pin 154 and
75. The CLK2_40MHZ is the 40 MHz internal clock for the FPGA. A 20 MHz
clock enters the FPGA on pin 158, this signal is generated by the 386EX. This
signal called PHI1-FPGA will be used in the LCD control circuit.