COMe-mAL10 – User Guide, Rev. 1.3
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Pin
COMe Signal
Description
Type
Termination
Comment
B61
P
PCI Express receive lane 2
DP-I
B62
PCIE_RX2-
B63
GPO3
General purpose output 3
O-3.3
PD 20 K
Ω
B64
P
PCI Express receive lane 1
DP-I
B65
PCIE_RX1-
B66
WAKE0#
PCI Express Wake Event, wake
up signal
I-3.3
PU 10 K
Ω
, 3.3 V
(S5)
B67
WAKE1#
General purpose Wake Event
wake up signal, to implement
wake-up on PS2 keyboard or
mouse
I-3.3
PU 10 K
Ω
, 3.3 V
(S5)
B68
P
PCI Express receive lane 0
DP-I
B69
PCIE_RX0-
B70
GND
Power Ground
PWR GND
B71
DDI
DDIO data pair 0
DP-O
B72
DDI0_PAIR0-
B73
DDI
DDIO data pair 1
DP-O
B74
DDI0_PAIR1-
B75
DDI
DDIO data pair 2
DP-O
B76
DDI0_PAIR2-
B77
DDI
DDIO data pair 4
NC
Not supported on
Apollo Lake SoC
B78
DDI0_PAIR4-
B79
LVDS/BKLT_EN
LVDS or EDP panel backlight
enable (ON)
0-3.3
PD 100 k
Ω
B80
GND
Power Ground
PWR GND
B81
DDI
DDIO data pair 3
DP-O
B82
DDI0_PAIR3-
B83
LVDS/BKLT_CTRL
LVDS or EDP panel backlight
brightness control
O-3.3
B84
VCC_5V_SBY
5V Standby
PWR 5 V (S5)
Optional, not necessary
in single supply mode
B85
VCC_5V_SBY
B86
VCC_5V_SBY
B87
VCC_5V_SBY
B88
BIOS_DIS1#
BIOS selection strap to
determine BIOS boot device
I-3.3
PU 10 K
Ω
, 3.3 V
(S5)
B89
DDO_HPD
DDIO hot plug detect
I-3.3
PD 100 k
Ω
B90
GND
Power Ground
PWR GND
B91
DDI
DDIO data pair 5
NC
Not supported on
Apollo lake SoC
B92
DDI0_PAIR5-
B93
DDI
DDIO data pair 6
NC
Not supported on
Apollo lake SoC
B94
DDI0_PAIR6-
Optional connection to
USB2_OTG_ID
B95
DDI0_DCC_AUX_SEL
DDIO DCC/ Aux select
I-3.3
PD 1 M
Ω
B96
USB_HOST_PRSNT
USB host preset
I-3.3
PD 100 k
Ω
Internal connection to
USB2_VBUS_SNS
B97
SPI_CS#
Chip select for carrier board SPI
0-3.3
B98
DDI0_CTRL
DDIO auxiliary clock control
signal
I/O-3.3 v
PD 100 k
Ω