Keysight N9038A, Service Manual, Page: 394 / 745

394 Keysight N9038A MXE Service Guide
Optional Assemblies
A26 Wideband Digital IF Assembly Description
Clock Generator
The clock generator takes the 10 MHz reference input from the A8
Motherboard and phase locks a local 100 MHz VCO to it. Phase coherent
copies of the 100 MHz reference signal are sent to the DSP ASIC, FPGA, and
CPLD. Each copy goes to only one destination and all copies are length
matched. There is a separate very low jitter 100 MHz clock that is provided for
the PCIe interface.
Power PC
The Power PC serves as the local PCI bus master and controller of the
assembly. PCI communication from the A4 Processor host generally comes to
the Power PC. The Power PC then controls the local hardware.
The Power PC has two main busses, the PCI bus and the memory bus. The
memory bus connects to 128 MB of SDRAM at 100 MHz. The Power PC
BootROM is 8 MB of flash memory. The Power PC clocks are derived from the
33 MHz PCI clock. The internal clock runs at 250 MHz.
At power up the Power PC transfers two images from flash memory to the
SRAM. Either image can then be written into the FPGA by the CPLD (under
Power PC control) over a dedicated 16 bit 100MHz programming bus.
CPLD
The CPLD generates local reset signals, and has a register based interface to
the Power PC CPU memory bus.
The Power PC CPU to CPLD interface has two parts. The first is an 8 bit wide
interface that is always available and allows for such things as diagnostics,
reset control, and FPGA reprogramming control. The second is a 32 bit wide
path that allows access to the FPGA Flash and SRAM. This 32 bit path allows
setup of FPGA reprogramming and writing/reading of Flash and SRAM
contents, and is only available to the Power PC while the FPGA is not being
reprogrammed. During FPGA reprogramming the CPLD takes over this bus,
isolates it from the CPU and uses it to DMA the SRAM contents into the FPGA.
Non-Transparent PCI to PCI Bridge
The Non-Transparent PCI to PCI Bridge is used to isolate the local PCI bus from
the instrument PCI bus, allowing the Power PC to master the local PCI bus.
This is important because it allows the Power PC to control and re-enumerate
the local PCI bus whenever necessary without causing problems for the rest of
the instrument. The local PCI bus connects to the Non-Transparent PCI Bridge,
the FPGA, and the PCI to PCIe Bridge. Both PCI busses are 32 bit running at 33
MHz.