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ESMT
M12L64164A
Elite Semiconductor Memory Technology Inc.
Publication Date: May 2008
Revision: 3.3
39/46
Read interrupted by Precharge Command & Read Burst Stop Cycle @ Burst Length = Full page
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C L O C K
C K E
C S
R A S
C A S
A D D R
W E
D Q
D Q M
A 1 0 / A P
R A a
C A a
C A b
R A a
Q A a 0 Q A a 1
Q A b 1
Q A b 0
Q A b 2
* N o t e 1
R o w A c t i v e
( A - B a n k )
R e a d
( A - B a n k )
B u r s t S t o p
R e a d
( A - B a n k )
: D o n ' t C a r e
H I G H
C L = 2
C L = 3
Q A a 2 Q A a 3 Q A a 4
Q A b 3 Q A b 4 Q A b 5
Q A a 0 Q A a 1
Q A b 1
Q A b 0
Q A b 2
Q A a 2 Q A a 3 Q A a 4
Q A b 3 Q A b 4 Q A b 5
1
1
2
2
P r e c h a r g e
( A - B a n k )
BA0
BA1
*Note : 1. About the valid DQs after burst stop, it is same as the case of
RAS
interrupt.
Both cases are illustrated above timing diagram. See the label 1,2 on them.
But at burst write, Burst stop and
RAS
interrupt should be compared carefully.
Refer the timing diagram of “Full page write burst stop cycles”.
2. Burst stop is valid at every burst length.