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ESMT
M12L64164A
Elite Semiconductor Memory Technology Inc.
Publication Date: May 2008
Revision: 3.3
38/46
Clock Suspension & DQM Operation Cycle @ CAS Letency = 2 , Burst Length = 4
C L O C K
C K E
C S
R A S
C A S
A D D R
W E
D Q
D Q M
A 1 0 / A P
R a
C a
C b
C c
R a
Q a 0
Q a 1
Q a 2
Q a 3
t
S H Z
Q b 1
Q b 0
t
S H Z
D c 0
D c 2
* N o t e 1
R o w A c t i v e
R e a d
C l o c k
S u p e n s i o n
R e a d
R e a d D Q M
W r i t e
W r i t e
D Q M
C l o c k
S u s p e n s i o n
W r i t e
D Q M
: D o n ' t C a r e
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
BA0
BA1
*Note : 1. DQM is needed to prevent bus contention