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ESMT
M12L64164A
Elite Semiconductor Memory Technology Inc.
Publication Date: May 2008
Revision: 3.3
19/46
3. CAS Interrupt (I)
*Note : 1. By “interrupt” is meant to stop burst read/write by external before the end of burst.
By ” CAS interrupt ”, to stop burst read/write by CAS access; read and write.
2. t
CCD
: CAS to CAS delay. (=1CLK)
3. t
CDL
: Last data in to new column address delay. (=1CLK)
C L K
C M D
A D D
D Q ( CL 2 )
DQ ( C L 3 )
R D
Q B 0
Q B 2
Q A 0
CL K
C M D
A D D
D Q
W R
DA 0 D B 0
DB 1
RD
A
B
Q B 1
Q B 3
Q B 0
Q B 2
Q A 0
Q B 3
Q B 1
t
C C D
* N o t e 2
W R
t
C C D * N o t e 2
A
B
t
C D L
* N o t e 3
W R
RD
t
C C D * N o t e 2
A
B
D A 0
D B 0
D B 1
t
C D L
* N o t e 3
D A 0
DB 0
D B 1
DQ ( C L 3 )
D Q ( CL 2 )
1 ) R e a d i n t e r r u p t e d b y R e a d ( B L = 4 )
2 ) W r i t e i n t e r r u p t e d b y W r i t e ( B L = 2 )
3 ) W r i t e i n t e r r u p t e d b y R e a d ( B L = 2 )
* N o t e 1