ESMT
M12L64164A
Elite Semiconductor Memory Technology Inc.
Publication Date: May 2008
Revision: 3.3
36/46
Read & Write Cycle at Different Bank @ Burst Length = 4
C L O C K
C K E
C S
R A S
C A S
A D D R
W E
D Q
D Q M
A 1 0 / A P
C L = 2
C L = 3
Row Active
(A-Bank)
R e a d
( B - B a n k )
: D o n ' t C a r e
Q A a 1 Q A a 2 Q A a 3
D d b 1 D D b 2 D D d 3
D D b 0
Q A a 0
R A a
C B c
R A a
C A a
Q A a 1 Q A a 2 Q A a 3
D d b 1 D D b 2 D D d 3
D D b 0
Q A a 0
W r i t e
( D - B a n k )
H I G H
R D b
C D b
R B c
R B b
R A c
Q B c 0 Q B c 1 Q B c 2
Q B c 0 Q B c 1
Read
(A-Bank)
Row Active
(D-Bank)
Precharge
(A-Bank)
Row Active
(B-Bank)
t
C D L
* N o t e 1
1
9
2
1 0
3
4
5
6
7
8
1 1
1 2
1 3
1 4
1 7
1 5
1 8
1 6
1 9
0
BA0
BA1
*Note : 1. t
CDL
should be met to complete write.