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ESMT
M12L64164A
Elite Semiconductor Memory Technology Inc.
Publication Date: May 2008
Revision: 3.3
7/46
AC OPERATING TEST CONDITIONS
(VDD = 3.3V
±
0.3V
,
TA = 0 to 70 C
°
)
PARAMETER VALUE UNIT
Input levels (Vih/Vil)
2.4/0.4
V
Input timing measurement reference level
1.4
V
Input rise and fall-time
tr/tf = 1/1
ns
Output timing measurement reference level
1.4
V
Output load condition
See Fig. 2
(Fig. 1) DC Output Load Circuit
(Fig. 2) AC Output Load Circuit
OPERATING AC PARAMETER
(AC operating conditions unless otherwise noted)
VERSION
PARAMETER SYMBOL
-5 -6 -7
UNIT NOTE
Row active to row active delay
t
RRD(min)
10 12 14 ns
1
RAS to CAS delay
t
RCD(min)
15 18 20 ns
1
Row precharge time
t
RP(min)
15 18 20 ns
1
t
RAS(min)
38 40 42 ns
1
Row active time
t
RAS(max)
100 us
@ Operating
t
RC(min)
53 58 63 ns
1
Row cycle time
@ Auto refresh
t
RFC(min)
55 60 70 ns
1,5
Last data in to col. address delay
t
CDL(min)
1 CLK
2
Last data in to row precharge
t
RDL(min)
2 CLK
2
Last data in to burst stop
t
BDL(min)
1 CLK
2
Col. address to col. address delay
t
CCD(min)
1 CLK
3
CAS latency = 3
2
Number of valid
Output data
CAS latency = 2
1
ea 4
Note : 1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then
rounding off to the next higher integer.
2. Minimum delay is required to complete with.
3. All parts allow every cycle column address change.
4. In case of row precharge interrupt, auto precharge and read burst stop.
5. A new command may be given t
RFC
after self refresh exit.
Output
870
V
OH
(DC) =2.4V , I
OH
= -2 mA
V
OL
(DC) =0.4V , I
OL
= 2 mA
Output
50pF
Z0 =50
50pF
50
Vtt = 1.4V
3.3V
1200
Ω
Ω
Ω
Ω