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ESMT
M12L64164A
Elite Semiconductor Memory Technology Inc.
Publication Date: May 2008
Revision: 3.3
22/46
6. Precharge
.
7. Auto Precharge
*Note
:
1. t
RDL
: Last data in to row precharge delay.
2. Number of valid output data after row precharge : 1,2 for CAS Latency = 2,3 respectively.
3. The row active command of the precharge bank can be issued after t
RP
from this point.
The new read/write command of other activated bank can be issued from this point.
At burst read/write with auto precharge, CAS interrupt of the same/another bank is illegal.
C L K
C M D
D Q
D 0
D 1
D 2
D 3
W R
t
R D L
* N o t e 1
C L K
C M D
C M D
D Q ( C L 2 )
Q0
Q1
Q2
Q3
R D
P R E
D Q ( C L 3 )
Q0
Q1
Q2
Q3
P R E
1 ) N o r m a l W r i t e ( B L = 4 )
2 ) N o r m a l R e a d ( B L = 4 )
C L = 2
P R E C L = 3
* N o t e 2
* N o t e 2
C L K
C M D
D Q
D 0
D 1
D 2
D 3
W R
C L K
C M D
D Q ( C L 2 )
D 0
D 1
D 2
D 3
R D
D Q ( C L 3 )
* N o t e 3
A u t o P r e c h a r g e s t a r t s
D 0
D 1
D 2
D 3
* N o t e 3
A u t o P r e c h a r g e s t a r t s
1 ) N o r m a l W r i t e ( B L = 4 )
2 ) N o r m a l R e a d ( B L = 4 )
t
R D L ( m i n )