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ESMT
M12L64164A
Elite Semiconductor Memory Technology Inc.
Publication Date: May 2008
Revision: 3.3
26/46
FUNCTION TURTH TABLE (TABLE 1)
Current
State
CS RAS CAS
WE
BA ADDR
ACTION
Note
H
X
X
X
X X
NOP
L
H
H
H
X X
NOP
L
H
H
L
X X
ILLEGAL
2
IDLE L H L X BA CA,
A10/AP
ILLEGAL
2
L
L
H
H
BA
RA
Row (&Bank) Active ; Latch RA
L
L
H
L
BA
A10/AP
NOP
4
L
L
L
H
X
X
Auto Refresh or Self Refresh
5
L
L
L
L
OP code
OP code
Mode Register Access
5
H
X
X
X
X X
NOP
L
H
H
H
X X
NOP
L
H
H
L
X X
ILLEGAL
2
Row
L
H
L
H
BA
CA, A10/AP Begin Read ; latch CA ; determine AP
Active
L
H
L
L
BA
CA, A10/AP Begin Write ; latch CA ; determine AP
L
L
H
H
BA RA
ILLEGAL
2
L
L
H
L
BA
A10/AP
Precharge
L
L
L
X
X X
ILLEGAL
H
X
X
X
X
X
NOP (Continue Burst to End
Æ
Row Active)
L
H
H
H
X
X
NOP (Continue Burst to End
Æ
Row Active)
L
H
H
L
X X
Term
burst
Æ
Row active
Read
L
H
L
H
BA
CA, A10/AP Term burst, New Read, Determine AP
L
H
L
L
BA
CA, A10/AP Term burst, New Write, Determine AP
3
L
L
H
H
BA RA
ILLEGAL
2
L
L
H
L
BA
A10/AP
Term burst, Precharge timing for Reads
L
L
L
X
X X
ILLEGAL
H
X
X
X
X
X
NOP (Continue Burst to End
Æ
Row Active)
L
H
H
H
X
X
NOP (Continue Burst to End
Æ
Row Active)
L
H
H
L
X X
Term
burst
Æ
Row active
Write
L
H
L
H
BA
CA, A10/AP Term burst, New Read, Determine AP
3
L
H
L
L
BA
CA, A10/AP Term burst, New Write, Determine AP
3
L
L
H
H
BA RA
ILLEGAL
2
L
L
H
L
BA
A10/AP
Term burst, Precharge timing for Writes
3
L
L
L
X
X X
ILLEGAL
H
X
X
X
X
X
NOP (Continue Burst to End
Æ
Row Active)
Read with
L
H
H
H
X
X
NOP (Continue Burst to End
Æ
Row Active)
Auto L
H
H
L X
X
ILLEGAL
Precharge L H L X BA CA,
A10/AP
ILLEGAL
L
L
H
X
BA
RA,
RA10
ILLEGAL
2
L
L
L
X
X X
ILLEGAL
H
X
X
X
X
X
NOP (Continue Burst to End
Æ
Row Active)
Write with
L
H
H
H
X
X
NOP (Continue Burst to End
Æ
Row Active)
Auto L
H
H
L X
X
ILLEGAL
Precharge L H L X BA CA,
A10/AP
ILLEGAL
L
L
H
X
BA
RA,
RA10
ILLEGAL
2
L
L
L
X
X X
ILLEGAL