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ESMT
M12L64164A
Elite Semiconductor Memory Technology Inc.
Publication Date: May 2008
Revision: 3.3
35/46
Page Write Cycle at Different Bank @ Burst Length = 4
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C L O C K
C K E
C S
R A S
C A S
A D D R
W E
D Q
D Q M
A 1 0 / A P
B A 0
B A 1
: D o n ' t c a r e
* N o t e 1
R A a
R B b
C A a
C B b
R D d
C C c
R C c
C D d
* N o t e 2
D A a 1
D A a 0
D B b 0 D B b 1
D B b 3
D D d 0 D D d 1
D A a 2
D B b 2
D C c 0 D C c 1
R A a
R B b
R C c
R D d
D A a 3
C D d 2
t
C D L
R o w A c t i v e
( A - Bank )
R o w A c t i v e
( B - B a n k )
W r i t e
( A - B a n k )
W r i t e
( B - B a n k )
R o w A c t i v e
( C - B a n k )
W r i t e
( C - B a n k )
P r e c h a r g e
( A l l B a n k s )
R o w A c t i v e
( D - B a n k )
W r i t e
( D - B a n k )
H I G H
t
R D L
*Note : 1. To interrupt burst write by Row precharge , DQM should be asserted to mask invalid input data.
2. To interrupt burst write by Row precharge , both the write and the precharge banks must be the same.