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This Data Sheet may be revised by subsequent versions ©2004 Eon Silicon Solution, Inc., www.eonssi.com
or modifications due to changes in technical specifications.
23
EN25F16
Rev. F, Issue Date: 2009/03/16
Figure 20. Enter OTP Mode
Power-up Timing
Figure 21. Power-up Timing
Table 8. Power-Up Timing and Write Inhibit Threshold
Symbol
Parameter
Min.
Max.
Unit
t
VSL
(1)
V
CC
(min) to CS# low
10
µs
t
PUW
(1)
Time delay to Write instruction
1
10
ms
VWI(1)
Write Inhibit Voltage
1
2 .5
V
Note:
1.The parameters are characterized only.
2. VCC (max.) is 3.6V and VCC (min.) is 2.7V
INITIAL DELIVERY STATE
The device is delivered with the memory array erased: all bits are set to 1 (each byte contains FFh). The
Status Register contains 00h (all Status Register bits are 0).