ESMT
M12L64164A
Elite Semiconductor Memory Technology Inc.
Publication Date: May 2008
Revision: 3.3
37/46
Read & Write cycle with Auto Precharge @ Burst Length = 4
0
1
2
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C L O C K
C K E
C S
R A S
C A S
A D D R
W E
D Q
D Q M
A 1 0 / A P
C L = 2
C L = 3
Row Act ive
( A - Ba nk )
R ow A ctiv e
( D - B ank )
Auto Precharge
Start Point
Read with
Auto Precharge
( A - Bank )
Auto Precharge
Start Point
(D-Bank)
: D o n ' t C a r e
Q A a 1 Q A a 2 Q A a 3
D d b 1 D D b 2 D D d 3
D D b 0
Q A a 0
R a
C b
R a
C a
R b
R b
Q A a 1 Q A a 2 Q A a 3
D d b 1 D D b 2 D D d 3
D D b 0
Q A a 0
W rite with
Auto Precharge
(D-Bank)
H I G H
BA0
BA1
*Note : 1. t
CDL
should be controlled to meet minimum t
RAS
before internal precharge start.
(In the case of Burst Length = 1 & 2)