HP 8560A, Service Manual

Page: 341 / 450

Frequency Counter
See function block of A2 Controller Schematic Diagram (sheet 4 of 4) in the
Component-Level Information binder.
The frequency counter counts the frequency of the last IF and provides accurate timing signals
for digital zero-spans. The circuit also provides timing signals to the A3 Interface assembly’s
ADC (Analog to Digital Converter). The nominal input frequency is 5.35 MHz (10.7 MHz
divided by 2). The circuit’s frequency reference is the 10 MHz reference from the Al5 RF
assembly.
In the frequency count mode, prescales the 10 MHz reference by 5 to generate, a 2 MHz
timebase. This feeds through MUX to programmable-timer
input. Programmable-timer output (OUT2) is the gating signal (HBKT-PULSE)
for performing the frequency count. The gating time interval is a function of the counter
resolution which may be set between 10 Hz and 1 MHz. Table 9-2 lists the Gate Time for
each setting of COUNTER RES. The gate time is the period during which U511 pin 3 is high.
The FREQ COUNT input, is gated in by HBKT-PULSE. The gated signal
clocks divide-by-16 counters and These counters are cascaded to form a
divide-by-256 counter. The MSB of this counter, CD7, clocks the CLKO input of The
frequency of CD7 is a function of COUNTER RES as shown in Table 9-2. If Timer
overflows,
will be set and clocked, generating CNTOVFLIRQ, which will
interrupt the CPU.
If IRQAK2 is high, HBKT_PULSE will clock generating FREQCNTLIRQ. Upon
receiving the FREQCNTLIRQ interrupt, the CPU latches the to CD7 onto the BID
bus by setting LCDRD (1ow counter data read) low and reading the counter data from the
BID bus. The CPU will also read the data from the timer,
by setting and
LCNTLRD low, placing-the timer data on the BID bus. The CPU resets by setting
low via the BID bus and latch
Table 9-2. Gate Times
Counter Res Gate Time*
(U511 pin 3 high state)
200
ms
20 ms
10 Hz 2 MHz 4.18
100 Hz 2 MHz 418 Hz
1 2
ms 2 MHz 41.8 Hz
10
2
ms
2 MHz 41.8 Hz
100
2 ms 2 MHz 41.8 Hz
1 MHz
2 ms 2 MHz 41.8 Hz
* TP15 = (FREQ COUNT input x Gate Time)/256
9-14 Controller Section