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Holtek HT32F54231 User Manual Download Page 426

Rev. 1.00 

426 of 576

January 28, 2022

32-Bit Arm

®

 Cortex

®

-M0+ MCU

HT32F54231/HT32F54241/HT32F54243/HT32F54253

20  Inter-Integrated Circuit (I2C)

Close / Continue Transmission

After transmitting the last data byte, the STOP bit in the I2CCR register can be set to terminate the 

transmission or re-assign another slave device by configuring the I2CTAR register to restart a new 

transfer.

S

STA

Address

A

ADRS TXDE

Data1

A

TXDE

Data2

A

...

TXDE

DataN

TXDE

P

7-bit Master Transmitter

S

STA

Header

A

Data1

A

TXDE

Data2

A

...

TXDE

DataN

TXDE

P

10-bit Master Transmitter

Address

A

ADRS TXDE

A

A

BEH1

BEH1 BEH2

BEH3

BEH1

BEH1

BEH3

BEH2

BEH2

BEH2

BEH2

BEH2

BEH1: Cleared by reading I2CSR register
BEH2: Cleared by writing I2CDR register
BEH3: Cleared by HW automatically by sending STOP condition

Figure 149.  Master Transmitter Timing Diagram

Master Receiver Mode

Start Condition

The target slave device address and communication direction must be written into the I2CTAR 

register. The STA flag in the I2CSR register is set by hardware after a start condition occurs. In 

order to send the following address frame, the STA flag must be cleared to 0 if it has been set to 1.The 

STA flag is cleared by reading the I2CSR register.

Address Frame

In the 7-bit addressing mode: The ADRS flag is set after the address frame is sent by the master 

device and the acknowledge signal from the address matched slave device is received. In order 

to receive the following data frame, the ADRS bit must be cleared to 0 if it has been set to 1. The 

ADRS bit is cleared after reading the I2CSR register.
In the 10-bit addressing mode: The ADRS bit in the I2CSR register will be set twice in the 10-bit 

addressing mode. The first time the ADRS bit is set is when the first header byte and the second 

address byte are sent and the acknowledge signals from the slave device are received. The second 

time the ADRS bit is set is when the second header byte is sent and the slave acknowledge signal 

is received. In order to receive the following data frame, the ADRS bit must be cleared to 0 if it 

has been set to 1. The ADRS bit is cleared after reading the I2CSR register. The detailed master 

receiver mode timing diagram is shown in the following figure.

Data Frame

In the master receiver mode, data is transmitted from the slave device. Once a data is received by 

the master device, the RXDNE flag in the I2CSR register is set but it will not hold the SCL line. 

However, if the device receives a complete new data byte and the RXDNE flag has already been set 

Summary of Contents for HT32F54231

Page 1: ...Holtek 32 Bit Microcontroller with Arm Cortex M0 Core HT32F54231 HT32F54241 HT32F54243 HT32F54253 User Manual Revision V1 00 Date January 28 2022 ...

Page 2: ...ction 43 Features 43 Functional Descriptions 44 Flash Memory Map 44 Flash Memory Architecture 45 Wait State Setting 45 Booting Configuration 46 Page Erase 46 Mass Erase 48 Word Programming 49 Option Byte Description 50 Page Erase Program Protection 51 Security Protection 52 Register Map 53 Register Descriptions 54 Flash Target Address Register TADR 54 Flash Write Data Register WRDR 55 Flash Operat...

Page 3: ...ol Register PWRCR 76 Low Voltage Brown Out Detect Control and Status Register LVDCSR 78 Power Control LDO Status Register PWRLDOSR 79 6 Clock Control Unit CKCU 80 Introduction 80 Features 82 Functional Descriptions 82 High Speed External Crystal Oscillator HSE 82 High Speed Internal RC Oscillator HSI 83 Auto Trimming of High Speed Internal RC Oscillator HSI 83 Phase Locked Loop PLL 85 Low Speed Ex...

Page 4: ...15 Power On Reset 115 System Reset 116 AHB and APB Unit Reset 116 Register Map 116 Register Descriptions 117 Global Reset Status Register GRSR 117 AHB Peripheral Reset Register AHBPRSTR 118 APB Peripheral Reset Register 0 APBPRSTR0 119 APB Peripheral Reset Register 1 APBPRSTR1 121 8 General Purpose I O GPIO 123 Introduction 123 Features 124 Functional Descriptions 124 Default GPIO Pin Configuratio...

Page 5: ...ull Down Selection Register PCPDR 150 Port C Open Drain Selection Register PCODR 151 Port C Drive Current Selection Register PCDRVR 152 Port C Lock Register PCLOCKR 153 Port C Data Input Register PCDINR 154 Port C Output Data Register PCDOUTR 155 Port C Output Set Reset Control Register PCSRR 156 Port C Output Reset Register PCRR 157 Port D Data Direction Control Register PDDIRCR 158 Port D Input ...

Page 6: ...179 Interrupt and Debounce 180 Register Map 181 Register Descriptions 182 EXTI Interrupt n Configuration Register EXTICFGRn n 0 15 182 EXTI Interrupt Control Register EXTICR 183 EXTI Interrupt Edge Flag Register EXTIEDGEFLGR 184 EXTI Interrupt Edge Status Register EXTIEDGESR 185 EXTI Interrupt Software Set Command Register EXTISSCR 185 EXTI Interrupt Wakeup Control Register EXTIWAKUPCR 186 EXTI In...

Page 7: ...209 ADC Interrupt Clear Register ADCICLR 210 ADC DMA Request Register ADCDMAR 211 Voltage Reference Control Register VREFCR 212 Voltage Reference Value Register VREFVALR 213 13 Comparator CMP HT32F54243 HT32F54253 only 214 Introduction 214 Features 214 Functional Descriptions 215 Comparator Inputs and Output 215 Comparator Voltage Reference 215 Interrupts and Wakeup 216 Power Mode and Hysteresis 2...

Page 8: ...egister CH3ICFR 259 Channel 0 Output Configuration Register CH0OCFR 261 Channel 1 Output Configuration Register CH1OCFR 263 Channel 2 Output Configuration Register CH2OCFR 265 Channel 3 Output Configuration Register CH3OCFR 267 Channel Control Register CHCTR 269 Channel Polarity Configuration Register CHPOLR 270 Timer PDMA Interrupt Control Register DICTR 271 Timer Event Generator Register EVGR 27...

Page 9: ... Configuration Register CH1ICFR 332 Channel 2 Input Configuration Register CH2ICFR 334 Channel 3 Input Configuration Register CH3ICFR 336 Channel 0 Output Configuration Register CH0OCFR 338 Channel 1 Output Configuration Register CH1OCFR 340 Channel 2 Output Configuration Register CH2OCFR 342 Channel 3 Output Configuration Register CH3OCFR 344 Channel Control Register CHCTR 346 Channel Polarity Co...

Page 10: ...mer Counter Configuration Register CNTCFR 379 Timer Mode Configuration Register MDCFR 380 Timer Trigger Configuration Register TRCFR 381 Timer Control Register CTR 382 Channel Input Configuration Register CHICFR 383 Channel Output Configuration Register CHOCFR 385 Channel Control Register CHCTR 386 Channel Polarity Configuration Register CHPOLR 387 Timer Interrupt Control Register DICTR 388 Timer ...

Page 11: ...ptions 404 RTC Counter Register RTCCNT 404 RTC Compare Register RTCCMP 405 RTC Control Register RTCCR 406 RTC Status Register RTCSR 408 RTC Interrupt and Wakeup Enable Register RTCIWEN 409 19 Watchdog Timer WDT 410 Introduction 410 Features 411 Functional Description 411 Register Map 413 Register Descriptions 413 Watchdog Timer Control Register WDTCR 413 Watchdog Timer Mode Register 0 WDTMR0 414 W...

Page 12: ...L High Period Generation Register I2CSHPGR 438 I2 C SCL Low Period Generation Register I2CSLPGR 439 I2 C Data Register I2CDR 440 I2 C Target Register I2CTAR 441 I2 C Address Mask Register I2CADDMR 442 I2 C Address Snoop Register I2CADDSR 443 I2 C Timeout Register I2CTOUT 444 21 Serial Peripheral Interface SPI 445 Introduction 445 Features 446 Functional Descriptions 446 Master Mode 446 Slave Mode ...

Page 13: ...81 USART FIFO Control Register USRFCR 483 USART Interrupt Enable Register USRIER 484 USART Status Interrupt Flag Register USRSIFR 486 USART Timing Parameter Register USRTPR 488 USART IrDA Control Register IrDACR 489 USART RS485 Control Register RS485CR 490 USART Synchronous Control Register SYNCR 491 USART Divider Latch Register USRDLR 492 USART Test Register USRTSTR 493 23 Universal Asynchronous ...

Page 14: ...R n 0 5 514 PDMA Channel n Destination Address Register PDMACHnDADR n 0 5 515 PDMA Channel n Transfer Size Register PDMACHnTSR n 0 5 516 PDMA Channel n Current Transfer Size Register PDMACHnCTSR n 0 5 517 PDMA Interrupt Status Register PDMAISR 518 PDMA Interrupt Status Clear Register PDMAISCR 519 PDMA Interrupt Enable Register PDMAIER 520 25 Divider DIV 522 Introduction 522 Features 522 Functional...

Page 15: ...te Calculation 538 Register Map 539 Register Descriptions 540 LED Control Register LEDCR 540 LED COM Enable Register LEDCER 541 LED Polarity Control Register LEDPCR 542 LED Interrupt Enable Register LEDIER 543 LED Status Register LEDSR 544 LED Dead Time Control Register LEDDTCR 545 LED Data Register n LEDDRn n 0 11 546 28 Touch Key 547 Introduction 547 Features 547 Function Description 547 Manual ...

Page 16: ...pacitor Register TKMnK2CPR 569 Touch Key Module n Key 1 Capacitor Register TKMnK1CPR 570 Touch Key Module n Key 0 Capacitor Register TKMnK0CPR 570 Touch Key Module n C F Counter Register TKMnCFCNTR 571 Touch Key Module n Key 3 Counter Register TKMnK3CNTR 572 Touch Key Module n Key 2 Counter Register TKMnK2CNTR 572 Touch Key Module n Key 1 Counter Register TKMnK1CNTR 573 Touch Key Module n Key 0 Co...

Page 17: ... Table 16 Output Divider 2 Value Mapping 85 Table 17 Feedback Divider 2 Value Mapping 86 Table 18 CKOUT Clock Source 88 Table 19 CKCU Register Map 89 Table 20 RSTCU Register Map 116 Table 21 AFIO GPIO and I O Pad Control Signal True Table 125 Table 22 GPIO Register Map 126 Table 23 AFIO Selection for Peripheral Map Example 170 Table 24 AFIO Register Map 170 Table 25 Exception Types 175 Table 26 NV...

Page 18: ...52 SPI Master Mode SPI_SEL Pin Status 455 Table 53 SPI Register Map 456 Table 54 Baud Rate Deviation Error Calculation CK_USART 40 MHz 471 Table 55 Baud Rate Deviation Error Calculation CK_USART 48 MHz 471 Table 56 Baud Rate Deviation Error Calculation CK_USART 60 MHz 471 Table 57 USART Register Map 479 Table 58 Baud Rate Deviation Error Calculation CK_UART 40 MHz 496 Table 59 Baud Rate Deviation ...

Page 19: ...onators for HSE 82 Figure 17 HSI Auto Trimming Block Diagram 84 Figure 18 PLL Block Diagram 85 Figure 19 External Crystal Ceramic and Resonators for LSE 86 Figure 20 RSTCU Block Diagram 115 Figure 21 Power On Reset Sequence 116 Figure 22 GPIO Block Diagram 123 Figure 23 AFIO GPIO Control Signal 125 Figure 24 AFIO Block Diagram 168 Figure 25 EXTI Channel Input Selection 169 Figure 26 EXTI Block Dia...

Page 20: ...Stage Block Diagram 237 Figure 60 Toggle Mode Channel Output Reference Signal CHxPRE 0 238 Figure 61 Toggle Mode Channel Output Reference Signal CHxPRE 1 239 Figure 62 PWM Mode Channel Output Reference Signal and Counter in Up counting Mode 239 Figure 63 PWM Mode Channel Output Reference Signal and Counter in Down counting Mode 240 Figure 64 PWM Mode Channel Output Reference Signal and Counter in ...

Page 21: ...igure 98 Dead Time Insertion Performed for Complementary Outputs 305 Figure 99 MCTM Break Signal Bolck Diagram 306 Figure 100 MT_BRK Pin Digital Filter Diagram with N 2 306 Figure 101 Channel 3 Output with a Break Event Occurrence 307 Figure 102 Channel 0 2 Complementary Outputs with a Break Event Occurrence 308 Figure 103 Channel 0 2 Only One Output Enabled when Break Event Occurs 309 Figure 104 ...

Page 22: ...412 Figure 140 I2 C Module Block Diagram 419 Figure 141 START and STOP Condition 421 Figure 142 Data Validity 421 Figure 143 7 bit Addressing Mode 422 Figure 144 10 bit Addressing Write Transmit Mode 422 Figure 145 10 bits Addressing Read Receive Mode 422 Figure 146 I2 C Bus Acknowledge 423 Figure 147 Clock Synchronization during Arbitration 423 Figure 148 Two Masters Arbitration Procedure 424 Fig...

Page 23: ... RS485 Interface and Waveform 476 Figure 178 USART Synchronous Transmission Example 477 Figure 179 8 Bit Format USART Synchronous Waveform 478 Figure 180 UART Block Diagram 494 Figure 181 UART Serial Data Format 495 Figure 182 UART Clock CK_UART and Data Frame Timing 496 Figure 183 PDMA Block Diagram 506 Figure 184 PDMA Request Mapping Architecture 507 Figure 185 PDMA Channel Arbitration and Sched...

Page 24: ...241 HT32F54243 HT32F54253 List of Figures Figure 200 Touch Key Interrupts 551 Figure 201 Touch Key Manual Scan Mode Flowchart TKMOD 1 0 01 551 Figure 202 Touch Key Auto Scan Mode Flowchart TKMOD 1 0 00 552 Figure 203 Touch Key Periodic Auto Scan Mode Flowchart TKMOD 1 0 10 11 553 ...

Page 25: ...and up to 16 KB of embedded SRAM memory for system operation and application program usage A variety of peripherals such as Hardware Divider DIV PDMA ADC I2 C USART UART SPI GPTM SCTM BFTM MCTM CRC 16 32 RTC WDT Touch key LED controller and SW DP Serial Wire Debug Port etc are also implemented in the device series Several power saving modes provide the flexibility for maximum optimization between ...

Page 26: ...ontroller EXTI Up to 16 EXTI lines with configurable trigger source and type All GPIO pins can be selected as EXTI trigger source Source trigger type can be high level low level negative edge positive edge or both edges Individual interrupt enable wakeup enable and status bits for each EXTI line Software interrupt trigger mode for each EXTI line Integrated deglitch filter for short pulse blocking ...

Page 27: ...prescaler that allows division of the prescaler clock source by any factor between 1 and 65536 to generate the counter clock frequency Input Capture function Compare Match Output PWM waveform generation with Edge aligned and Center aligned Counting Modes Single Pulse Mode Output Encoder interface controller with two inputs using quadrature decoder Single Channel Timer SCTM 16 bit auto reload up co...

Page 28: ... including word length parity bit stop bit and bit order Error detection Parity overrun and frame error Supports Auto hardware flow control mode RTS CTS IrDA SIR encoder and decoder RS485 mode with output enable control FIFO Depth 8 level for both receiver and transmitter Universal Asynchronous Receiver Transmitter UART Asynchronous serial communication operating baud rate clock frequency of up to...

Page 29: ...rupt Three frequency sources LSI LSE and PCLK The LED light on off times can be controlled using the dead time setting Touch Key Four key oscillator frequencies 1 MHz 3 MHz 7 MHz 11 MHz 1024 level reference oscillator internal capacitor Single 16 bit C F Counter Three scan modes Manual mode Auto scan mode and Periodic auto scan mode Support detection in the Sleep Deep Sleep1 and Deep Sleep2 modes ...

Page 30: ...M KB 4 8 8 16 Timers MCTM 1 1 GPTM 1 1 SCTM 2 4 BFTM 2 2 WDT 1 1 RTC 1 1 Communication SPI 2 2 USART 1 2 UART 2 4 I2 C 2 3 Hardware Divider 1 CRC 16 32 1 PDMA 6 channels EXTI 16 12 bit ADC Number of channels 1 Max 10 channels Comparator 2 GPIO Up to 40 Up to 54 LED controller Up to 8 8 segment Up to 12 8 segment Touch key 24 28 CPU frequency Up to 60 MHz Operating voltage 2 5 V 5 5 V Operating tem...

Page 31: ...ORE AF Flash Memory Interface X32KIN X32KOUT LSI 32 kHz LSE 32 768 Hz VDD VSS RTC PWRCU nRST RTCOUT WAKEUP AF AF Powered by VDDA VDDA VSSA ADC_IN0 ADC_IN9 12 bit SAR ADC AHB to APB Bridge SRAM PA PB 15 0 PC 7 0 AF TX RX IO Port Powered by VDD VSS VDD POR PDR BOD LVD XTALIN XTALOUT ULDO VCORE HSE 4 16 MHz AF LDO VCORE CLDO CAP SCTM AF PLL fMax 60 MHz AF AF TX RX RTS TXE CTS SCK HSI 8 MHz VCORE POR ...

Page 32: ...er supply Bus Control signal Alternate function AF Powered by VCORE AF Flash Memory Interface X32KIN X32KOUT LSI 32 kHz LSE 32 768 Hz VDD VSS RTC PWRCU nRST RTCOUT WAKEUP AF AF Powered by VDDA VDDA VSSA ADC_IN0 ADC_IN9 12 bit SAR ADC AHB to APB Bridge SRAM AF TX RX AF IO Port Powered by VDD VSS VDD POR PDR BOD LVD XTALIN XTALOUT ULDO VCORE HSE 4 16 MHz AF LDO VCORE CLDO CAP SCTM AF PLL fMax 60 MHz...

Page 33: ...tion which means any value is allowed RW RW 0 RW 0 19 18 PLLEN HSEEN Software can read and write to this bit RO HSIRDY RO 1 RO 0 3 2 HSERDY Software can only read this bit A write operation will have no effect RC PDF RC 0 RC 1 1 0 PORF Software can only read this bit A read operation will clear it to 0 automatically WC WC 0 WC 0 3 2 CKSF Software can read this bit or clear it by writing 1 Writing ...

Page 34: ...re pre defined memory map and up to 4 GB of memory space making the system flexible and extendable Arm Cortex M0 Processor The Cortex M0 processor is a very low gate count highly energy efficient processor that is intended for microcontroller and deeply embedded applications that require an area optimized low power processor The processor is based on the ARMv6 M architecture and supports Thumb ins...

Page 35: ...st of one master and four slaves in the bus architecture The HT32F54243 HT32F54253 series consist of two masters and four slaves in the bus architecture The system bus and Peripheral Direct Memory Access PDMA are the masters while the internal SRAM access bus the internal Flash memory access bus the AHB peripherals access bus and the AHB to APB bridge are the slaves The PDMA is only available for ...

Page 36: ...Arm Cortex M0 processor access and debug access share the single external interface to external AHB peripherals The processor access takes priority over debug access The maximum address range of the Cortex M0 is 4 GB since it has 32 bit bus address width Additionally a pre defined memory map is provided by the Cortex M0 processor to reduce the software complexity of repeated implementation of diff...

Page 37: ... AHB peripherals 0x4008_0000 0x4010_0000 Private peripheral bus 0xE000_0000 Reserved 0xE010_0000 0xFFFF_FFFF 512 KB 512 KB 0x4000_0000 UART0 0x4000_1000 SPI0 0x4000_4000 0x4000_5000 I2 C0 ADC Reserved 0x4001_0000 EXTI 0x4002_3000 0x4002_4000 WDT 0x4004_5000 0x4004_8000 0x4006_9000 0x4006_B000 0x4006_A000 0x4004_9000 0x4006_E000 0x4002_C000 APB FMC 0x4008_0000 Reserved 0x4008_2000 CKCU RSTCU 0x4008...

Page 38: ...0x4008_0000 0x4010_0000 Private peripheral bus 0xE000_0000 Reserved 0xE010_0000 0xFFFF_FFFF 512 KB 512 KB 0x4000_0000 UART0 0x4000_1000 SPI0 0x4000_4000 0x4000_8000 I2 C0 ADC Reserved 0x4001_0000 EXTI 0x4002_3000 0x4002_4000 WDT 0x4004_5000 0x4004_8000 0x4006_9000 0x4006_B000 0x4006_A000 0x4004_9000 0x4006_E000 0x4002_C000 APB FMC 0x4008_0000 Reserved 0x4008_2000 CKCU RSTCU 0x4008_8000 0x400C_C000...

Page 39: ... 0x4002_5000 0x4002_BFFF Reserved 0x4002_C000 0x4002_CFFF MCTM 0x4002_D000 0x4003_3FFF Reserved 0x4003_4000 0x4003_4FFF SCTM0 0x4003_5000 0x4004_0FFF Reserved 0x4004_1000 0x4004_1FFF UART1 0x4004_2000 0x4004_3FFF Reserved 0x4004_4000 0x4004_4FFF SPI1 0x4004_5000 0x4004_7FFF Reserved 0x4004_8000 0x4004_8FFF I2 C0 0x4004_9000 0x4004_9FFF I2 C1 0x4004_A000 0x4005_9FFF Reserved 0x4005_A000 0x4005_AFFF...

Page 40: ..._2FFF UART2 0x4000_3000 0x4000_3FFF Reserved 0x4000_4000 0x4000_4FFF SPI0 0x4000_5000 0x4000_7FFF Reserved 0x4000_8000 0x4000_8FFF I2 C2 0x4000_9000 0x4000_FFFF Reserved 0x4001_0000 0x4001_0FFF ADC 0x4001_1000 0x4001_9FFF Reserved 0x4001_A000 0x4001_AFFF TKEY 0x4001_B000 0x4002_1FFF Reserved 0x4002_2000 0x4002_2FFF AFIO 0x4002_3000 0x4002_3FFF Reserved 0x4002_4000 0x4002_4FFF EXTI 0x4002_5000 0x40...

Page 41: ...006_F000 0x4007_3FFF Reserved 0x4007_4000 0x4007_4FFF SCTM1 0x4007_5000 0x4007_5FFF SCTM3 0x4007_6000 0x4007_6FFF BFTM0 0x4007_7000 0x4007_7FFF BFTM1 0x4007_8000 0x4007_FFFF Reserved 0x4008_0000 0x4008_1FFF FMC AHB 0x4008_2000 0x4008_7FFF Reserved 0x4008_8000 0x4008_9FFF CKCU RSTCU 0x4008_A000 0x4008_BFFF CRC 0x4008_C000 0x400A_FFFF Reserved 0x4009_0000 0x4009_1FFF PDMA_REG 0x4009_2000 0x400A_FFFF...

Page 42: ...ress 0x2000_0000 It supports byte half word and word access operations AHB Peripherals The address of the AHB peripherals ranges from 0x4008_0000 to 0x400F_FFFF Some peripherals such as Clock Control Unit Reset Control Unit and Flash Memory Controller are connected to the AHB bus directly The AHB peripherals clocks are always enabled after a system reset Access to registers for these peripherals c...

Page 43: ...o provided for instruction data storage Flash Memory Controller Main Flash Memory Information Block Wait State Control Addressing Data Programming Control AHB Peripheral Bus Flash Control Register Pre fetch Buffer Figure 7 Flash Memory Controller Block Diagram Features Up to 128 KB of on chip Flash memory for storing instruction data and option bytes 128 KB instruction data Option Byte for the HT3...

Page 44: ...07FF is mapped to the Boot Loader Block with a capacity of 2 KB Additionally the region addressed from 0x1FF0_0000 to 0x1FF0_03FF is the alias of the Option Byte block with a capacity of 1 KB which physically locates at the last page of the main Flash The memory mapping on system view is shown below Main Flash Block User Application Reserved 0x0000_0000 Boot Loader Block Reserved Option Byte Reser...

Page 45: ... Loader 0x1F00_0000 0x1F00_07FF NA 2 KB Notes 1 The Information Block stores the boot loader and this block cannot be programmed or erased by users 2 The Option Byte is always located at the last page of the Main Flash Block Wait State Setting When the CPU clock HCLK is faster than the Flash memory access speed the wait state cycles must be inserted during CPU fetching instructions or loading data...

Page 46: ...ined by the BOOT pin status which will be sampled during the reset duration Hard Fault Handler NMI Handler Program Counter Initial Stack Point 0x0 0x4 0x8 0xC 0x0000_0000 0x4 0x8 0xC 0x1F00_0000 0x4 0x8 0xC 1 Main Flash 0 Boot Loader Boot Setting Figure 9 Vector Remapping Page Erase The FMC provides a page erase function which is used to reset partial content of the Flash memory Any page can be er...

Page 47: ...appens Additionally the page erase operation will be ignored on the protected pages When this occurs the OREF bit will be set by the FMC and then a Flash Operation Error interrupt will be generated if the OREIEN bit in the OIER register is set The software can check the PPEF bit in the OISR register to detect this condition in the interrupt handler The following figure shows the page erase operati...

Page 48: ... 3 0 0xA 3 Commit the mass erase command to the FMC by setting the OPCR register Set OPM 3 0 0xA 4 Wait until all the operations have been finished by checking the value of the OPCR register OPM 3 0 is equal to 0xE 5 Read and verify the Flash memory if required Since all Flash data will be reset as 0xFFFF_FFFF the mass erase operation can be implemented by the program that runs on the SRAM or by t...

Page 49: ... 0 0xA 5 Wait until all the operations have been finished by checking the value of the OPCR register OPM 3 0 is equal to 0xE 6 Read and verify the Flash memory if required Note that the word programming operation cannot be successively applied to the same address twice Successive word programming operation to the same address must be separated by a page erase operation Additionally the word progra...

Page 50: ... variable X is equal to 126 0xFFFF_FFFF 0xFFFF_FFFF 0xFFFF_FFFF 0xFFFF_FFFF OB_CP 0x010 Flash Security Protection OB_CP 0 0 Flash Security protection is enabled 1 Flash Security protection is disabled Option Byte Protection OB_CP 1 0 Option Byte protection is enabled 1 Option Byte protection is disabled OB_CP 31 2 Reserved 0xFFFF_FFFF OB_CK 0x020 Flash Option Byte Checksum OB_CK 31 0 OB_CK should ...

Page 51: ...n function has been enabled Other pages are not affected 2 The main Flash page protection is configured by OB_PP 127 0 Option Byte is physically located at the last page of the main Flash The Option Byte page protection is configured by the OB_CP 1 bit 3 The page erase operation on the Option Byte area can disable the page protection of the main Flash 4 The page protection of the Option Byte can o...

Page 52: ...on means the software that is executed or booted from the main Flash memory with the SW debugger being disconnected However the Option Byte area and page 0 are still under protection where the Programming Page Erase operations are not accepted 2 The Mass Erase operation can erase the Option Byte area and disable the security protection The following steps show the register access sequence for the ...

Page 53: ...PSR 0x020 0x024 0x028 0x02C Flash Page Erase Program Protection Status Register 0xXXXX_XXXX 0xXXXX_XXXX 0xXXXX_XXXX 0xXXXX_XXXX CPSR 0x030 Flash Security Protection Status Register 0x0000_000X VMCR 0x100 Flash Vector Mapping Control Register 0x0000_000X MDID 0x180 Flash Manufacturer and Device ID Register 0x0376_XXXX PNSR 0x184 Flash Page Number Status Register 0x0000_00XX PSSR 0x188 Flash Page Si...

Page 54: ...ess Bits For programming operations the TADR register specifies the address where the data is written to Since the programming length is 32 bit the TADR register should be set as word aligned 4 bytes The TADB 1 0 bits will be ignored during programming operations For page erase operations the TADR register contains the page address which is to be erased Since the page size is 1 KB the TADB 9 0 bit...

Page 55: ...fset 0x004 Reset value 0x0000_0000 31 30 29 28 27 26 25 24 WRDB Type Reset RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 23 22 21 20 19 18 17 16 WRDB Type Reset RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 15 14 13 12 11 10 9 8 WRDB Type Reset RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 7 6 5 4 3 2 1 0 WRDB Type Reset RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 Bits Field Descriptions 31 0 WRDB Flash Write Data Bits...

Page 56: ...d Type Reset 23 22 21 20 19 18 17 16 Reserved Type Reset 15 14 13 12 11 10 9 8 Reserved Type Reset 7 6 5 4 3 2 1 0 Reserved CMD Type Reset RW 0 RW 0 RW 0 RW 0 Bits Field Descriptions 3 0 CMD Flash Operation Command The following table shows the definitions of the operation command field CMD 3 0 which specifies the Flash memory operation If an invalid command is set and the IOCMIEN bit is set to 1 ...

Page 57: ...le shows the FMC operation modes Users can commit command which is set by the OCMR register to the FMC according to the address alias setting in the TADR register The contents of the TADR WRDR and OCMR registers should be prepared before setting this register After all the operations have been finished the OPM field will be set to 0xE by the FMC hardware The Idle mode can be set when all the opera...

Page 58: ...BEIEN ITADIEN ORFIEN Type Reset RW 0 RW 0 RW 0 RW 0 RW 0 Bits Field Descriptions 4 OREIEN Operation Error Interrupt Enable 0 Operation Error Interrupt is disabled 1 Operation Error Interrupt is enabled 3 IOCMIEN Invalid Operation Command Interrupt Enable 0 Invalid Operation Command Interrupt is disabled 1 Invalid Operation Command Interrupt is enabled 2 OBEIEN Option Byte Check Sum Error Interrupt...

Page 59: ...rogram operation being applied to a protected page This bit is reset by hardware once a new flash operation command is committed 16 RORFF Raw Operation Finished Flag 0 The last Flash operation command is not finished 1 The last Flash operation command is finished The RORFF bit is directly connected to the Flash memory for debugging purpose 4 OREF Operation Error Flag 0 No Flash operation error occ...

Page 60: ...eans that the Option Byte checksum value has be correctly modified or the corresponding interrupt control is disabled Otherwise the interrupt will be continually generated 1 ITADF Invalid Target Address Flag 0 The target address is valid 1 The target address is invalid The data in the TADR field must be within the range from 0x0000_0000 to 0x1FFF_ FFFF Otherwise this bit will be set high and an In...

Page 61: ... RO X RO X RO X RO X Bits Field Descriptions 127 0 PPSBn Page Erase Program Protection Status Bits n 0 127 PPSB n OB_PP n 0 The corresponding page is protected 1 The corresponding page is not protected The content of this register is not dynamically updated and will only be reloaded from the Option Byte when any kind of reset occurs The erase or program function of the specific pages is not allowe...

Page 62: ...00_000X 31 30 29 28 27 26 25 24 Reserved Type Reset 23 22 21 20 19 18 17 16 Reserved Type Reset 15 14 13 12 11 10 9 8 Reserved Type Reset 7 6 5 4 3 2 1 0 Reserved OBPSB CPSB Type Reset RO X RO X Bits Field Descriptions 1 OBPSB Option Byte Page Erase Program Protection Status Bit 0 The Option Byte page is protected 1 The Option Byte page is not protected The reset value of the OBPSB bit is determin...

Page 63: ...Type Reset 7 6 5 4 3 2 1 0 Reserved VMCB Reserved Type Reset RW X Bits Field Descriptions 1 VMCB Vector Mapping Control Bit The VMCB bit is used to control the mapping source of the first 4 words of vector addressed from 0x0 to 0xC The following table shows the vector mapping setting BOOT VMCB Descriptions Low 0 Boot Loader mode The vector mapping source is the boot loader area High 1 Main Flash m...

Page 64: ...ntity Offset 0x180 Reset value 0x0376_XXXX 31 30 29 28 27 26 25 24 MFID Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 1 RO 1 23 22 21 20 19 18 17 16 MFID Type Reset RO 0 RO 1 RO 1 RO 1 RO 0 RO 1 RO 1 RO 0 15 14 13 12 11 10 9 8 ChipID Type Reset RO X RO X RO X RO X RO X RO X RO X RO X 7 6 5 4 3 2 1 0 ChipID Type Reset RO X RO X RO X RO X RO X RO X RO X RO X Bits Field Descriptions 31 16 MFID Manufact...

Page 65: ...t RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 PNSB Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 7 6 5 4 3 2 1 0 PNSB Type Reset RO X RO X RO X RO X RO X RO X RO X RO X Bits Field Descriptions 31 0 PNSB Flash Page Number Status Bits 0x0000_0010 Totally 16 pages for the on chip Flash memory device 0x0000_0020 Totally 32 pages for the on chip Flash memory device 0x0000_0040 To...

Page 66: ... 0 RO 0 RO 0 RO 0 RO 0 Bits Field Descriptions 31 0 PSSB Flash Page Size Status Bits 0x200 The page size is 512 Bytes per page 0x400 The page size is 1 K Bytes per page 0x800 The page size is 2 K Bytes per page Device ID Register DIDR This register specifies the device part number information which can be used as the product identity Offset 0x18C Reset value 0x000X_XXXX 31 30 29 28 27 26 25 24 Res...

Page 67: ...tions 4 PFBE Pre fetch Buffer Enable Bit 0 Pre fetch buffer is disabled 1 Pre fetch buffer is enabled The pre fetch buffer is enabled by default setting When the pre fetch buffer is disabled the instruction and data are directly provided by the Flash memory 2 0 WAIT Flash Wait State Setting The WAIT 2 0 field is used to set the HCLK wait clock during a non sequential Flash access The actual wait c...

Page 68: ...ous depending on Flash Manufacture Privilege Information Block 31 30 29 28 27 26 25 24 CID Type Reset RO X RO X RO X RO X RO X RO X RO X RO X 23 22 21 20 19 18 17 16 CID Type Reset RO X RO X RO X RO X RO X RO X RO X RO X 15 14 13 12 11 10 9 8 CID Type Reset RO X RO X RO X RO X RO X RO X RO X RO X 7 6 5 4 3 2 1 0 CID Type Reset RO X RO X RO X RO X RO X RO X RO X RO X Bits Field Descriptions 31 0 CI...

Page 69: ... application to achieve the best trade off between the conflicting demands of CPU operating time speed and power consumption The dash line in the following figure indicates the power supply source of two digital power domains PWR_CTRL LSI LSE LDOOFF ULDOON SLEEPDEEP RTC nRST VCORE VDD VCORE Domain VDD Domain LVD BOD Low Voltage Detector Brown Out Detector POR PDR Power On Reset Power Down Reset ML...

Page 70: ...llowing conditions occurs Resume operation from the power saving mode RTC wakeup LVD wakeup EXTI wakeup and WAKEUPn pin wakeup Detect a falling edge on the external reset pin nRST The control bit BODEN 1 and the supply power VDD VBOD To enter the Deep Sleep1 or Deep Sleep2 mode the PWRCU will turn off the main LDO and request the ULDO to operate in the low standby current mode to supply an alterna...

Page 71: ... then immediately disable the internal LDO regulator when the BODRIS bit is cleared to 0 or issue an interrupt to notify the CPU to execute a power down procedure when the BODRIS bit is set to 1 For more details concerning the Brown Out Detector voltage VBOD refer to the electrical characteristics of the corresponding datasheet High Speed External Oscillator The High Speed External Oscillator HSE ...

Page 72: ...lock by setting the AHBPRE field in the CKCU AHBCFGR register and the second is to turn off the unused peripherals clock by setting the APBCCR0 and APBCCR1 registers or slow down the peripherals clock by setting the APBPCSR0 and APBPCSR1 registers to meet the application requirement Reducing the system clock speed before entering the sleep mode will also help to minimize power consumption Addition...

Page 73: ...ep mode configure the registers as shown in the preceding table and execute the WFI or WFE instruction In the Deep Sleep mode all clocks including the PLL and high speed oscillators known as HSI and HSE will be stopped In addition the Deep Sleep1 and Deep Sleep2 mode will turns off the main LDO and uses an ultra low power LDO ULDO to keep the VCORE power Once the PWRCU receives a wakeup event or a...

Page 74: ...main it also can be reset by the nRST reset pin After the reset there will be a delay before the WUPnEN bit is active This bit will not be active until the system reset is finished and the VDD domain ISO signal is disabled This means that the bit cannot be immediately set by software after a system reset is finished and the VDD domain ISO signal is disabled The delay time requires at least three 3...

Page 75: ...is cleared by software read Software should read this bit to clear it after a system wake up from the power saving mode 8 WUPF0 External WAKEUP0 Pin Flag 0 The WAKEUP0 pin is not asserted 1 The WAKEUP0 pin is asserted This bit is set by hardware when the WAKEUP0 pin asserts and is cleared by software read Software should read this bit to clear it after a system wake up from the power saving mode 4...

Page 76: ...dge Triggered 0 1 Negative edge Triggered 1 0 High level Sensitive 1 1 Low level Sensitive 17 16 WUP0TYPE WAKEUP0 Signal Trigger Type WUP0TYPE 1 0 WAKEUP0 Signal Trigger Type 0 0 Positive edge Triggered 0 1 Negative edge Triggered 1 0 High level Sensitive 1 1 Low level Sensitive 15 ULDOSTS Ultra low Power Regulator Status This bit is set to 1 if the ULDOON bit in this register has been cleared to ...

Page 77: ...LDOOFF Main regulator Operating Mode Control 0 The LDO operates in a low current mode when MCU enters the Deep Sleep mode SLEEPDEEP 1 That means MCU VCORE power is available and supplied by ultra low power regulator ULDO 1 The LDO is turned off when the MCU enters the Deep Sleep mode SLEEPDEEP 1 That means MCU VCORE power is not available and enters power down mode Note This bit is only available ...

Page 78: ...d If the system requires to be woken up from the Deep Sleep mode by an LVD condition this bit must be set to 1 20 LVDIWEN LVD Interrupt Wakeup Enable 0 LVD interrupt wakeup is disabled 1 LVD interrupt wakeup is enabled Setting this bit to 1 will enable the LVD interrupt function When an LVD condition occurs and the LVDIWEN bit is set to 1 an LVD interrupt will be generated and sent to the MCU NVIC...

Page 79: ...n activity 3 BODF Brown Out Detect Flag 0 VDD VBOD 1 VDD VBOD 1 BODRIS BOD Reset or Interrupt Selection 0 Reset the whole chip 1 Generate Interrupt 0 BODEN Brown Out Detector Enable 0 Disable Brown Out Detector 1 Enable Brown Out Detector Power Control LDO Status Register PWRLDOSR Power Control LDO Status Register PWRLDOSR Offset 0x11C Reset value 0x30XX_XXXX 31 30 29 28 27 26 25 24 Reserved LDOPS...

Page 80: ...ler clock multiplexer and clock gating The clocks of AHB APB and CPU are derived from system clock CK_SYS which can come from HSI HSE LSI LSE or PLL Watchdog Timer and Real Time Clock RTC use either LSI or LSE as their clock source The maximum operating frequency of system clock fCK_AHB can be up to 60 MHz A variety of internal clocks can also be wired out through CKOUT for debugging purpose The c...

Page 81: ...M MCTM SCTMx BFTMx EXTI RTC PWRCU WDT PLL Clock Monitor PLLEN CK_LSE CK_PLL DMAEN ADCEN CK_LSI HCLKS to SRAM HCLKF to Flash CM0PEN FMCEN CM0PEN SRAMEN 1 0 RTCSRC 1 CK_RTC RTCEN 1 1 0 1 0 Note 1 These control bits are located in RTC Control Register RTCCR 2 The CK_IN signal is sourced from the external CKIN pin CK_AHB 000 001 010 011 100 101 110 CK_SYS SW 2 0 8 HCLKC to Cortex M0 CM0PEN control by ...

Page 82: ...urate clock source to the system clock The related hardware configuration is shown in the following figure The crystal with specific frequency must be placed across the two HSE pins XTALIN XTALOUT and the external components such as resistors and capacitors are necessary to make it oscillate properly The following guidelines are provided to improve the stability of the crystal circuit PCB layout T...

Page 83: ...d the cost will determine the use of the oscillators Software could configure the Power Saving Wakeup RC Clock Enable bit PSRCEN to 1 to force the HSI clock to be the system clock when waking up from the Deep Sleep1 or Deep Sleep2 mode Subsequently the system clock is back to the original clock source HSE or PLL if the original clock source ready flag is asserted This function can reduce the wakeu...

Page 84: ...ARSE 4 0 HSIFINE 7 0 8 MHz Auto Trimming Controller Fine Trimming Write Register 1 kHz 1 024 kHz 32 LSE 32 768 kHz AT Counter Register Fine Trimming Read Register TMSEL Coarse Trimming Read Register Factory Trimming Bits 0 1 TRIMEN REFCLKSEL 1x 00 0 1 AHB Bus ATCEN Auto Trimming HSI Block Diagram External pin CKIN Figure 17 HSI Auto Trimming Block Diagram ...

Page 85: ...k Divider 1 4 NF2 Feedback Divider 2 1 16 NO1 Output Divider 1 2 NO2 Output Divider 2 1 2 4 or 8 Considering the duty cycle with 50 both input frequency and output frequency is divided by 2 Assume that a given CLKIN frequency as PLL input generates a specific PLL output frequency a larger number of NF2 is suggested because it will cause the PLL more stable and less jittered but enlarges the settli...

Page 86: ... frequency produces a low power but highly accurate clock source for the circuits of Real Time Clock peripheral Watchdog Timer or system clock The associated hardware configuration is shown in the following figure The crystal or ceramic resonator must be placed across the two LSE pins X32KIN X32KOUT and the external components such as resistors and capacitors are necessary to make it oscillate pro...

Page 87: ...ts ready The corresponding clock ready status bit in the Global Clock Status Register GCSR will indicate whether the selected clock is ready to use or not The CKCU also contains the clock source status bits in the Clock Source Status Register CKST to indicate which clock is currently used as the system clock If a clock source or the PLL output clock is used as the system clock it is not possible t...

Page 88: ... the HSE is directly used as the system clock source when the HSE oscillator failure occurs the HSE will be turned off and the system clock will be switched to the HSI automatically by the hardware If the HSE is used as the clock input of the PLL circuit and the system clock comes from the PLL circuit output the PLL circuit will also be turned off as well as the HSE when the failure happens Clock ...

Page 89: ...CR 0x01C PLL Control Register 0x0000_0000 AHBCFGR 0x020 AHB Configuration Register 0x0000_0000 AHBCCR 0x024 AHB Clock Control Register 0x0000_0065 APBCFGR 0x028 APB Configuration Register 0x0001_0000 APBCCR0 0x02C APB Clock Control Register 0 0x0000_0000 APBCCR1 0x030 APB Clock Control Register 1 0x0000_0000 CKST 0x034 Clock Source Status Register 0x0100_0003 APBPCSR0 0x038 APB Peripheral Clock Se...

Page 90: ...hen chip once entered Deep Sleep1 mode 011 When chip once entered Deep Sleep2 mode Others Reserved Set by hardware Reset by software writing b11x 15 11 CKREFPRE CK_REF Clock Prescaler Selection CK_REF CK_PLL CKREFPRE 1 2 00000 CK_REF CK_PLL 2 00001 CK_REF CK_PLL 4 11111 CK_REF CK_PLL 64 Set and reset by software to control the CK_REF clock prescaler setting 8 PLLSRC PLL Clock Source Selection 0 Ex...

Page 91: ...is provided to CPU After the original clock source which is selected as CK_SYS before entering the Deep Sleep1 2 mode is ready hardware will switch back the clock source as originally 16 CKMEN HSE Clock Monitor Enable 0 Disable external 4 16 MHz crystal oscillator clock monitor 1 Enable external 4 16 MHz crystal oscillator clock monitor When hardware detects the HSE clock stuck at low high state i...

Page 92: ...t be immediately switched and a certain delay is necessary Software can monitor the CKSWST field in the clock source status register CKST to make sure which clock is currently used as the system clock Global Clock Status Register GCSR This register indicates the clock ready status Offset 0x008 Reset value 0x0000_0028 31 30 29 28 27 26 25 24 Reserved Type Reset 23 22 21 20 19 18 17 16 Reserved Type...

Page 93: ...lock Ready Flag 0 PLL is not ready 1 PLL is ready Set by hardware to indicate that the PLL is stable to be used Global Clock Interrupt Register GCIR This register specifies interrupt enable and flag bits Offset 0x00C Reset value 0x0000_0000 31 30 29 28 27 26 25 24 Reserved Type Reset 23 22 21 20 19 18 17 16 Reserved CKSIE Type Reset RW 0 15 14 13 12 11 10 9 8 Reserved Type Reset 7 6 5 4 3 2 1 0 Re...

Page 94: ...d PFBD Type Reset RW 0 RW 0 RW 0 RW 0 23 22 21 20 19 18 17 16 PFBD POTD Reserved Type Reset RW 0 RW 0 RW 0 15 14 13 12 11 10 9 8 Reserved Type Reset 7 6 5 4 3 2 1 0 Reserved Type Reset Bits Field Descriptions 28 REFDIV PLL Input Reference Clock Divider 0 Reference divider 1 1 Reference divider 2 26 23 PFBD PLL VCO Output Clock Feedback Divider B3 B0 in PLL Block Diagram Feedback Divider divides th...

Page 95: ...pecifies Bypass mode control of PLL Offset 0x01C Reset value 0x0000_0000 31 30 29 28 27 26 25 24 PLLBPS Reserved Type Reset RW 0 23 22 21 20 19 18 17 16 Reserved Type Reset 15 14 13 12 11 10 9 8 Reserved Type Reset 7 6 5 4 3 2 1 0 Reserved Type Reset Bits Field Descriptions 31 PLLBPS PLL Bypass Mode Enable 0 Disable PLL Bypass mode 1 Enable PLL Bypass mode where fOUT fIN ...

Page 96: ...28 27 26 25 24 Reserved Type Reset 23 22 21 20 19 18 17 16 Reserved Type Reset 15 14 13 12 11 10 9 8 Reserved Type Reset 7 6 5 4 3 2 1 0 Reserved AHBPRE Type Reset RW 0 RW 0 RW 0 Bits Field Descriptions 2 0 AHBPRE AHB Pre scaler 000 CK_AHB CK_SYS 001 CK_AHB CK_SYS 2 010 CK_AHB CK_SYS 4 011 CK_AHB CK_SYS 8 100 CK_AHB CK_SYS 16 101 CK_AHB CK_SYS 32 110 CK_AHB CK_SYS 32 111 CK_AHB CK_SYS 32 Set and r...

Page 97: ...Divider Clock Enable 0 Divider clock is disabled 1 Divider clock is enabled Set and reset by software 19 PDEN GPIO Port D Clock Enable 0 Port D clock is disabled 1 Port D clock is enabled Set and reset by software This bit is only available for the HT32F54243 HT32F54253 devices 18 PCEN GPIO Port C Clock Enable 0 Port C clock is disabled 1 Port C clock is enabled Set and reset by software 17 PBEN G...

Page 98: ...sed during Sleep mode 4 PDMAEN Peripheral DMA Clock Enable 0 PDMA clock is disabled 1 PDMA clock is enabled Set and reset by software Note The PDMA can independently operate when the processor enters the sleep mode But the relative clock of AHB bus slave or peripherals has to be enabled This bit is only available for the HT32F54243 HT32F54253 devices 2 SRAMEN SRAM Clock Enable 0 SRAM clock is auto...

Page 99: ... 24 Reserved Type Reset 23 22 21 20 19 18 17 16 Reserved ADCDIV Type Reset RW 0 RW 0 RW 1 15 14 13 12 11 10 9 8 Reserved Type Reset 7 6 5 4 3 2 1 0 Reserved Type Reset Bits Field Descriptions 18 16 ADCDIV ADC Clock Frequency Division Selection 000 CK_ADC CK_AHB 001 CK_ADC CK_AHB 2 010 CK_ADC CK_AHB 4 011 CK_ADC CK_AHB 8 100 CK_ADC CK_AHB 16 101 CK_ADC CK_AHB 32 110 CK_ADC CK_AHB 64 111 CK_ADC CK_A...

Page 100: ...e 0 LEDC clock is disabled 1 LEDC clock is enabled Set and reset by software 15 EXTIEN External Interrupt Clock Enable 0 EXTI clock is disabled 1 EXTI clock is enabled Set and reset by software 14 AFIOEN Alternate Function I O Clock Enable 0 AFIO clock is disabled 1 AFIO clock is enabled Set and reset by software 13 UR3EN UART3 Clock Enable 0 UART3 clock is disabled 1 UART3 clock is enabled Set an...

Page 101: ...2F54241 devices the pins registers and control bits related to the USART do not have the serial number 0 5 SPI1EN SPI1 Clock Enable 0 SPI1 clock is disabled 1 SPI1 clock is enabled Set and reset by software 4 SPI0EN SPI0 Clock Enable 0 SPI0 clock is disabled 1 SPI0 clock is enabled Set and reset by software 2 I2C2EN I2 C2 Clock Enable 0 I2 C2 clock is disabled 1 I2 C2 clock is enabled Set and rese...

Page 102: ...ns 31 SCTM3EN SCTM3 Clock Enable 0 SCTM3 clock is disabled 1 SCTM3 clock is enabled Set and reset by software This bit is only available for the HT32F54243 HT32F54253 devices 30 SCTM2EN SCTM2 Clock Enable 0 SCTM2 clock is disabled 1 SCTM2 clock is enabled Set and reset by software This bit is only available for the HT32F54243 HT32F54253 devices 29 SCTM1EN SCTM1 Clock Enable 0 SCTM1 clock is disabl...

Page 103: ...M0 Clock Enable 0 BFTM0 clock is disabled 1 BFTM0 clock is enabled Set and reset by software 8 GPTMEN GPTM Clock Enable 0 GPTM clock is disabled 1 GPTM clock is enabled Set and reset by software 6 VDDREN VDD Domain Clock Enable for Register Access 0 Register access clock is disabled 1 Register access clock is enabled Set and reset by software 4 WDTREN Watchdog Timer Clock Enable for Register Acces...

Page 104: ...d Descriptions 27 24 HSIST Internal High Speed Clock Occupation Status CK_HSI xxx1 HSI is used by System Clock CK_SYS SW 0x3 xx1x HSI is used by System PLL x1xx HSI is used by Clock Monitor 18 16 HSEST External High Speed Clock Occupation Status CK_HSE xx1 HSE is used by System Clock CK_SYS SW 0x2 x1x HSE is used by System PLL 11 8 PLLST PLL Clock Occupation Status xxx1 PLL is used by System Clock...

Page 105: ... 0 Bits Field Descriptions 31 30 UR1PCLK UART1 Peripheral Clock Selection 00 PCLK CK_AHB 01 PCLK CK_AHB 2 10 PCLK CK_AHB 4 11 PCLK CK_AHB 8 PCLK Peripheral Clock CK_AHB AHB and CPU clock 29 28 UR0PCLK UART0 Peripheral Clock Selection 00 PCLK CK_AHB 01 PCLK CK_AHB 2 10 PCLK CK_AHB 4 11 PCLK CK_AHB 8 PCLK Peripheral Clock CK_AHB AHB and CPU clock 27 26 USR1PCLK USART1 Peripheral Clock Selection 00 P...

Page 106: ...on 00 PCLK CK_AHB 01 PCLK CK_AHB 2 10 PCLK CK_AHB 4 11 PCLK CK_AHB 8 PCLK Peripheral Clock CK_AHB AHB and CPU clock 11 10 UR3PCLK UART3 Peripheral Clock Selection 00 PCLK CK_AHB 01 PCLK CK_AHB 2 10 PCLK CK_AHB 4 11 PCLK CK_AHB 8 PCLK Peripheral Clock CK_AHB AHB and CPU clock These bits are only available for the HT32F54243 HT32F54253 devices 9 8 UR2PCLK UART2 Peripheral Clock Selection 00 PCLK CK_...

Page 107: ...27 26 25 24 SCTM3PCLK SCTM2PCLK SCTM1PCLK SCTM0PCLK Type Reset RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 23 22 21 20 19 18 17 16 I2C2PCLK Reserved Type Reset RW 0 RW 0 15 14 13 12 11 10 9 8 VDDRPCLK WDTRPCLK Reserved CMPPCLK Type Reset RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 7 6 5 4 3 2 1 0 Reserved ADCPCLK EXTIPCLK AFIOPCLK Type Reset RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 Bits Field Descriptions 31 30 SCTM3PCLK SCTM...

Page 108: ...32F54253 devices 15 14 VDDRPCLK VDD Domain Register Access Clock Selection 00 PCLK CK_AHB 4 01 PCLK CK_AHB 8 10 PCLK CK_AHB 16 11 PCLK CK_AHB 32 PCLK Peripheral Clock CK_AHB AHB and CPU clock 13 12 WDTRPCLK WDT Register Access Clock Selection 00 PCLK CK_AHB 01 PCLK CK_AHB 2 10 PCLK CK_AHB 4 11 PCLK CK_AHB 8 PCLK Peripheral Clock CK_AHB AHB and CPU clock 9 8 CMPPCLK CMP Peripheral Clock Selection 0...

Page 109: ...ns 28 24 HSICOARSE HSI Clock Coarse Trimming Value These bits are initialized automatically at startup They are adjusted by factory trimming and cannot be trimmed by program 23 16 HSIFINE HSI Clock Fine Trimming Value These bits are initialized automatically at startup They are also adjusted by factory trimming But these bits provide an additional user programmable trimming value that is added to ...

Page 110: ... 1 0 2 variation This bit is used to select the lock target range of the internal HSI RC oscillator trimming function for 0 1 or 0 2 variation 1 ATCEN ATC Enable 0 Disable Auto Trimming Controller 1 Enable Auto Trimming Controller 0 TRIMEN Trimming Enable 0 HSI Trimming is disabled 1 HSI Trimming is enabled Setting this bit high enables the HSI RC oscillator trimming function by ATC hardware or us...

Page 111: ...23 22 21 20 19 18 17 16 Reserved Type Reset 15 14 13 12 11 10 9 8 Reserved TOUCHKEYPCLK Reserved Type Reset RW 0 RW 0 7 6 5 4 3 2 1 0 LEDCPCLK Reserved Type Reset RW 0 RW 0 Bits Field Descriptions 11 10 TOUCHKEYPCLK Touch Key Peripheral Clock Selection 00 PCLK CK_AHB 01 PCLK CK_AHB 2 10 PCLK CK_AHB 4 11 PCLK CK_AHB 8 PCLK Peripheral Clock CK_AHB AHB and CPU clock 7 6 LEDCPCLK LEDC Controller Perip...

Page 112: ...ller FIFO timeout is frozen when the core is halted Set and reset by software 28 DBI2C2 I2 C2 Debug Mode Enable 0 Same behavior as in normal mode 1 I2 C2 timeout is frozen when the core is halted Set and reset by software This bit is only available for the HT32F54243 HT32F54253 devices 27 DBUR3 UART3 Debug Mode Enable 0 Same behavior as in normal mode 1 UART3 FIFO timeout is frozen when the core i...

Page 113: ...ftware 16 DBBFTM0 BFTM0 Debug Mode Enable 0 BFTM0 counter continues to count even if the core is halted 1 BFTM0 counter is stopped when the core is halted Set and reset by software 14 DBDSLP2 Debug Deep Sleep2 Mode 0 LDO ULDO On FCLK Off and CM0PEN 0 in Deep Sleep2 mode 1 LDO MLDO On FCLK On and CM0PEN 1 in Deep Sleep2 mode Set and reset by software 13 DBI2C1 I2 C1 Debug Mode Enable 0 Same behavio...

Page 114: ...GPTM counter is stopped when the core is halted Set and reset by software 4 DBMCTM MCTM Debug Mode Enable 0 MCTM counter continue to count even if the core is halted 1 MCTM counter is stopped when the core is halted Set and reset by software 3 DBWDT Watchdog Timer Debug Mode Enable 0 Watchdog Timer counter continues to count even if the core is halted 1 Watchdog Timer counter is stopped when the c...

Page 115: ...eset Generator URnRST WDT Reset UARTn Reset VDD Domain POR Filter PORB VDD PWCURST RTC PWRCU Reset Brown Out Detector RESET Filter VDD BODRST Cortex M0 RSTCU NVIC SYSRESETn SYSRESETREQ HRESETn CORERESTn CM0 Core System Components BusMatrix PMU System Debug Components SYSRESETREQ PORRESETn Figure 20 RSTCU Block Diagram Functional Descriptions Power On Reset The Power on reset POR is generated by ei...

Page 116: ...nit Reset The AHB and APB unit reset can be divided into hardware and software resets A hardware reset can be generated by either power on reset or system reset for all AHB and APB units Each functional IP connected to the AHB and APB buses can be reset individually through the associated software reset bits in the RSTCU For example the application software can generate a UART0 reset via the UR0RS...

Page 117: ...R occurred This bit is set by hardware when a power on reset occurs and reset by writing 1 into it 2 WDTRSTF Watchdog Timer Reset Flag 0 No Watchdog Timer reset occurred 1 Watchdog Timer occurred This bit is set by hardware when a watchdog timer reset occurs and reset by writing 1 into it or by hardware when a power on reset occurs 1 EXTRSTF External Pin Reset Flag 0 No pin reset occurred 1 Pin re...

Page 118: ...eset Control 0 No reset 1 Reset Port D This bit is set by software and cleared to 0 by hardware automatically This bit is only available for the HT32F54243 HT32F54253 devices 10 PCRST GPIO Port C Reset Control 0 No reset 1 Reset Port C This bit is set by software and cleared to 0 by hardware automatically 9 PBRST GPIO Port B Reset Control 0 No reset 1 Reset Port B This bit is set by software and c...

Page 119: ...d to 0 by hardware automatically 15 EXTIRST External Interrupt Controller Reset Control 0 No reset 1 Reset EXTI This bit is set by software and cleared to 0 by hardware automatically 14 AFIORST Alternate Function I O Reset Control 0 No reset 1 Reset Alternate Function I O This bit is set by software and cleared to 0 by hardware automatically 13 UR3RST UART3 Reset Control 0 No reset 1 Reset UART3 T...

Page 120: ...s and control bits related to the USART do not have the serial number 0 5 SPI1RST SPI1 Reset Control 0 No reset 1 Reset SPI1 This bit is set by software and cleared to 0 by hardware automatically 4 SPI0RST SPI0 Reset Control 0 No reset 1 Reset SPI0 This bit is set by software and cleared to 0 by hardware automatically 2 I2C2RST I2 C2 Reset Control 0 No reset 1 Reset I2 C2 This bit is set by softwa...

Page 121: ... and cleared to 0 by hardware automatically This bit is only available for the HT32F54243 HT32F54253 devices 30 SCTM2RST SCTM2 Reset Control 0 No reset 1 Reset SCTM2 This bit is set by software and cleared to 0 by hardware automatically This bit is only available for the HT32F54243 HT32F54253 devices 29 SCTM1RST SCTM1 Reset Control 0 No reset 1 Reset SCTM1 This bit is set by software and cleared t...

Page 122: ...0 Reset Control 0 No reset 1 Reset BFTM0 This bit is set by software and cleared to 0 by hardware automatically 8 GPTMRST GPTM Reset Control 0 No reset 1 Reset GPTM This bit is set by software and cleared to 0 by hardware automatically 4 WDTRST Watchdog Timer Reset Control 0 No reset 1 Reset Watchdog Timer This bit is set by software and cleared to 0 by hardware automatically 0 MCTMRST MCTM Reset ...

Page 123: ...tions The actual available General Purpose I O port numbers are dependent on the device specification and package type Refer to the device datasheet for detailed information The GPIO ports are pin shared with other alternative functions AFs to obtain maximum flexibility on the package pins The GPIO pins can be used as alternative functional pins by configuring the corresponding registers regardles...

Page 124: ...pull up General Purpose I O GPIO The GPIO pins can be configured as inputs or outputs via the data direction control registers PxDIRCR where x A D When the GPIO pins are configured as input pins the data on the external pads can be read if the enable bits in the input enable function register PxINER are set The GPIO pull up pull down registers PxPUR PxPDR can be configured to fit specific applicat...

Page 125: ...n x A D Input Enable PxDVn x A D Output Drive PxODn x A D Open Drain PxPDn PxPUn x A D Pull Down Up PxCFGn x A D AFIO Configuration Table 21 AFIO GPIO and I O Pad Control Signal True Table Type AFIO GPIO PAD ADENAFIO OENAFIO IENAFIO PxDIRn PxINENn ADEN OEN IEN GPIO Input Note 1 1 1 0 1 1 1 0 GPIO Output Note 1 1 1 1 0 1 if need 1 0 1 0 AFIO Input 1 1 0 0 X 1 1 0 AFIO Output 1 0 1 X 0 1 if need 1 0...

Page 126: ... Current Selection Register 0x0000_0000 PALOCKR 0x018 Port A Lock Register 0x0000_0000 PADINR 0x01C Port A Data Input Register 0x0000_3200 PADOUTR 0x020 Port A Data Output Register 0x0000_0000 PASRR 0x024 Port A Output Set Reset Control Register 0x0000_0000 PARR 0x028 Port A Output Reset Control Register 0x0000_0000 GPIO B Base Address 0x400B_2000 PBDIRCR 0x000 Port B Data Direction Control Regist...

Page 127: ...0 Port D Data Direction Control Register 0x0000_0000 PDINER 0x004 Port D Input Function Enable Control Register 0x0000_0000 PDPUR 0x008 Port D Pull Up Selection Register 0x0000_0000 PDPDR 0x00C Port D Pull Down Selection Register 0x0000_0000 PDODR 0x010 Port D Open Drain Selection Register 0x0000_0000 PDDRVR 0x014 Port D Drive Current Selection Register 0x0000_0000 PDLOCKR 0x018 Port D Lock Regist...

Page 128: ... the GPIO Port A pin as input or output Offset 0x000 Reset value 0x0000_0000 31 30 29 28 27 26 25 24 Reserved Type Reset 23 22 21 20 19 18 17 16 Reserved Type Reset 15 14 13 12 11 10 9 8 PADIR Type Reset RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 7 6 5 4 3 2 1 0 PADIR Type Reset RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 Bits Field Descriptions 15 0 PADIRn GPIO Port A pin n Direction Control Bits n 0 15...

Page 129: ... Reserved Type Reset 23 22 21 20 19 18 17 16 Reserved Type Reset 15 14 13 12 11 10 9 8 PAINEN Type Reset RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 1 RW 0 7 6 5 4 3 2 1 0 PAINEN Type Reset RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 Bits Field Descriptions 15 0 PAINENn GPIO Port A pin n Input Enable Control Bits n 0 15 0 Pin n input function is disabled 1 Pin n input function is enabled When the pin n input fun...

Page 130: ...22 21 20 19 18 17 16 Reserved Type Reset 15 14 13 12 11 10 9 8 PAPU Type Reset RW 0 RW 0 RW 1 RW 1 RW 0 RW 0 RW 1 RW 0 7 6 5 4 3 2 1 0 PAPU Type Reset RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 Bits Field Descriptions 15 0 PAPUn GPIO Port A pin n Pull Up Selection Control Bits n 0 15 0 Pin n pull up function is disabled 1 Pin n pull up function is enabled Note When the pull up and pull down functions...

Page 131: ...2 21 20 19 18 17 16 Reserved Type Reset 15 14 13 12 11 10 9 8 PAPD Type Reset RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 7 6 5 4 3 2 1 0 PAPD Type Reset RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 Bits Field Descriptions 15 0 PAPDn GPIO Port A pin n Pull Down Selection Control Bits n 0 15 0 Pin n pull down function is disabled 1 Pin n pull down function is enabled Note When the pull up and pull down func...

Page 132: ...2 21 20 19 18 17 16 Reserved Type Reset 15 14 13 12 11 10 9 8 PAOD Type Reset RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 7 6 5 4 3 2 1 0 PAOD Type Reset RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 Bits Field Descriptions 15 0 PAODn GPIO Port A pin n Open Drain Selection Control Bits n 0 15 0 Pin n Open Drain output is disabled The output type is CMOS output 1 Pin n Open Drain output is enabled The output...

Page 133: ...RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 23 22 21 20 19 18 17 16 PADV11 PADV10 PADV9 PADV8 Type Reset RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 15 14 13 12 11 10 9 8 PADV7 PADV6 PADV5 PADV4 Type Reset RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 7 6 5 4 3 2 1 0 PADV3 PADV2 PADV1 PADV0 Type Reset RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 Bits Field Descriptions 31 0 PADVn 1 0 GPIO Port A pin n Drive Current ...

Page 134: ...his field is not equal to 0x5FA0 any write operations on the PALOCKR register will be aborted The result of a read operation on the PALKEY field returns the GPIO Port A Lock Status which indicates whether the GPIO Port A is locked or not If the read value of the PALKEY field is 0 this indicates that the GPIO Port A Lock function is disabled Otherwise it indicates that the GPIO Port A Lock function...

Page 135: ... RO 0 Bits Field Descriptions 15 0 PADINn GPIO Port A pin n Data Input Bits n 0 15 0 The input data of the corresponding pin is 0 1 The input data of the corresponding pin is 1 Port A Output Data Register PADOUTR This register specifies the GPIO Port A output data Offset 0x020 Reset value 0x0000_0000 31 30 29 28 27 26 25 24 Reserved Type Reset 23 22 21 20 19 18 17 16 Reserved Type Reset 15 14 13 1...

Page 136: ... 11 10 9 8 PASET Type Reset WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 7 6 5 4 3 2 1 0 PASET Type Reset WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 Bits Field Descriptions 31 16 PARSTn GPIO Port A pin n Output Reset Control Bits n 0 15 0 No effect on the PADOUTn bit 1 Reset the PADOUTn bit Note that when the PARSTn bit in this register or the PARSTn bit in the PARR register is enabled the reset function ...

Page 137: ...0 WO 0 WO 0 WO 0 WO 0 Bits Field Descriptions 15 0 PARSTn GPIO Port A pin n Output Reset Control Bits n 0 15 0 No effect on the PADOUTn bit 1 Reset the PADOUTn bit Port B Data Direction Control Register PBDIRCR This register is used to control the direction of GPIO Port B pin as input or output Offset 0x000 Reset value 0x0000_0000 31 30 29 28 27 26 25 24 Reserved Type Reset 23 22 21 20 19 18 17 16...

Page 138: ... Reserved Type Reset 23 22 21 20 19 18 17 16 Reserved Type Reset 15 14 13 12 11 10 9 8 PBINEN Type Reset RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 7 6 5 4 3 2 1 0 PBINEN Type Reset RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 Bits Field Descriptions 15 0 PBINENn GPIO Port B pin n Input Enable Control Bits n 0 15 0 Pin n input function is disabled 1 Pin n input function is enabled When the pin n input fun...

Page 139: ...22 21 20 19 18 17 16 Reserved Type Reset 15 14 13 12 11 10 9 8 PBPU Type Reset RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 7 6 5 4 3 2 1 0 PBPU Type Reset RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 Bits Field Descriptions 15 0 PBPUn GPIO Port B pin n Pull Up Selection Control Bits n 0 15 0 Pin n pull up function is disabled 1 Pin n pull up function is enabled Note When the pull up and pull down functions...

Page 140: ...2 21 20 19 18 17 16 Reserved Type Reset 15 14 13 12 11 10 9 8 PBPD Type Reset RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 7 6 5 4 3 2 1 0 PBPD Type Reset RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 Bits Field Descriptions 15 0 PBPDn GPIO Port B pin n Pull Down Selection Control Bits n 0 15 0 Pin n pull down function is disabled 1 Pin n pull down function is enabled Note When the pull up and pull down func...

Page 141: ...2 21 20 19 18 17 16 Reserved Type Reset 15 14 13 12 11 10 9 8 PBOD Type Reset RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 7 6 5 4 3 2 1 0 PBOD Type Reset RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 Bits Field Descriptions 15 0 PBODn GPIO Port B pin n Open Drain Selection Control Bits n 0 15 0 Pin n Open Drain output is disabled The output type is CMOS output 1 Pin n Open Drain output is enabled The output...

Page 142: ...RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 23 22 21 20 19 18 17 16 PBDV11 PBDV10 PBDV9 PBDV8 Type Reset RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 15 14 13 12 11 10 9 8 PBDV7 PBDV6 PBDV5 PBDV4 Type Reset RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 7 6 5 4 3 2 1 0 PBDV3 PBDV2 PBDV1 PBDV0 Type Reset RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 Bits Field Descriptions 31 0 PBDVn 1 0 GPIO Port B pin n Drive Current ...

Page 143: ...his field is not equal to 0x5FA0 any write operations on the PBLOCKR register will be aborted The result of a read operation on the PBLKEY field returns the GPIO Port B Lock Status which indicates whether the GPIO Port B is locked or not If the read value of the PBLKEY field is 0 this indicates that the GPIO Port B Lock function is disabled Otherwise it indicates that the GPIO Port B Lock function...

Page 144: ...RO 0 RO 0 Bits Field Descriptions 15 0 PBDINn GPIO Port B pin n Data Input Bits n 0 15 0 The input data of corresponding pin is 0 1 The input data of corresponding pin is 1 Port B Output Data Register PBDOUTR This register specifies the GPIO Port B output data Offset 0x020 Reset value 0x0000_0000 31 30 29 28 27 26 25 24 Reserved Type Reset 23 22 21 20 19 18 17 16 Reserved Type Reset 15 14 13 12 11...

Page 145: ... 11 10 9 8 PBSET Type Reset WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 7 6 5 4 3 2 1 0 PBSET Type Reset WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 Bits Field Descriptions 31 16 PBRSTn GPIO Port B pin n Output Reset Control Bits n 0 15 0 No effect on the PBDOUTn bit 1 Reset the PBDOUTn bit Note that when the PBRSTn bit in this register or the PBRSTn bit in the PBRR register is enabled the reset function ...

Page 146: ...rt B output data Offset 0x028 Reset value 0x0000_0000 31 30 29 28 27 26 25 24 Reserved Type Reset 23 22 21 20 19 18 17 16 Reserved Type Reset 15 14 13 12 11 10 9 8 PBRST Type Reset WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 7 6 5 4 3 2 1 0 PBRST Type Reset WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 Bits Field Descriptions 15 0 PBRSTn GPIO Port B pin n Output Reset Control Bits n 0 15 0 No effect on the ...

Page 147: ... 29 28 27 26 25 24 Reserved Type Reset 23 22 21 20 19 18 17 16 Reserved Type Reset 15 14 13 12 11 10 9 8 PCDIR Type Reset RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 7 6 5 4 3 2 1 0 PCDIR Type Reset RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 Bits Field Descriptions x 0 PCDIRn GPIO Port C pin n Direction Control Bits n 0 x 0 Pin n is in input mode 1 Pin n is in output mode For the HT32F54231 HT32F54241 de...

Page 148: ... 13 12 11 10 9 8 PCINEN Type Reset RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 7 6 5 4 3 2 1 0 PCINEN Type Reset RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 Bits Field Descriptions x 0 PCINENn GPIO Port C pin n Input Enable Control Bits n 0 x 0 Pin n input function is disabled 1 Pin n input function is enabled When the pin n input function is disabled the input Schmitt trigger will be turned off and the S...

Page 149: ...pe Reset RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 7 6 5 4 3 2 1 0 PCPU Type Reset RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 Bits Field Descriptions x 0 PCPUn GPIO Port C pin n Pull Up Selection Control Bits n 0 x 0 Pin n pull up function is disabled 1 Pin n pull up function is enabled For the HT32F54231 HT32F54241 devices the variable x is equal to 7 while the variable x is equal to 15 for the HT32F5...

Page 150: ...e Reset RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 7 6 5 4 3 2 1 0 PCPD Type Reset RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 Bits Field Descriptions x 0 PCPDn GPIO Port C pin n Pull Down Selection Control Bits n 0 x 0 Pin n pull down function is disabled 1 Pin n pull down function is enabled For the HT32F54231 HT32F54241 devices the variable x is equal to 7 while the variable x is equal to 15 for the H...

Page 151: ...e Reset RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 7 6 5 4 3 2 1 0 PCOD Type Reset RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 Bits Field Descriptions x 0 PCODn GPIO Port C pin n Open Drain Selection Control Bits n 0 x 0 Pin n Open Drain output is disabled The output type is CMOS output 1 Pin n Open Drain output is enabled The output type is open drain output For the HT32F54231 HT32F54241 devices the var...

Page 152: ...PCDV10 PCDV9 PCDV8 Type Reset RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 15 14 13 12 11 10 9 8 PCDV7 PCDV6 PCDV5 PCDV4 Type Reset RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 7 6 5 4 3 2 1 0 PCDV3 PCDV2 PCDV1 PCDV0 Type Reset RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 Bits Field Descriptions 2x 1 0 PCDVn 1 0 GPIO Port C pin n Drive Current Selection Control Bits n 0 x 00 4 mA source sink current 01 8 mA sour...

Page 153: ...egister will be aborted The result of a read operation on the PCLKEY field returns the GPIO Port C Lock Status which indicates whether the GPIO Port C is locked or not If the read value of the PCLKEY field is 0 this indicates that the GPIO Port C Lock function is disabled Otherwise it indicates that the GPIO Port C Lock function is enabled as the read value is equal to 1 x 0 PCLOCKn GPIO Port C pi...

Page 154: ... 23 22 21 20 19 18 17 16 Reserved Type Reset 15 14 13 12 11 10 9 8 PCDIN Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 7 6 5 4 3 2 1 0 PCDIN Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 Bits Field Descriptions x 0 PCDINn GPIO Port C pin n Data Input Bits n 0 x 0 The input data of corresponding pin is 0 1 The input data of corresponding pin is 1 For the HT32F54231 HT32F54241 devices the ...

Page 155: ...ype Reset 23 22 21 20 19 18 17 16 Reserved Type Reset 15 14 13 12 11 10 9 8 PCDOUT Type Reset RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 7 6 5 4 3 2 1 0 PCDOUT Type Reset RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 Bits Field Descriptions x 0 PCDOUTn GPIO Port C pin n Data Output Bits n 0 x 0 Data to be output on pin n is 0 1 Data to be output on pin n is 1 For the HT32F54231 HT32F54241 devices the varia...

Page 156: ...Bits Field Descriptions x 16 16 PCRSTn GPIO Port C pin n Output Reset Control Bits n 0 x 0 No effect on the PCDOUTn bit 1 Reset the PCDOUTn bit Note that when the PCRSTn bit in this register or the PCRSTn bit in the PCRR register is enabled the reset function on the PCDOUTn bit will take effect For the HT32F54231 HT32F54241 devices the variable x is equal to 7 while the variable x is equal to 15 f...

Page 157: ...6 25 24 Reserved Type Reset 23 22 21 20 19 18 17 16 Reserved Type Reset 15 14 13 12 11 10 9 8 PCRST Type Reset WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 7 6 5 4 3 2 1 0 PCRST Type Reset WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 Bits Field Descriptions x 0 PCRSTn GPIO Port C pin n Output Reset Control Bits n 0 x 0 No effect on the PCDOUTn bit 1 Reset the PCDOUTn bit For the HT32F54231 HT32F54241 device...

Page 158: ...irection of GPIO Port D pin as input or output Offset 0x000 Reset value 0x0000_0000 31 30 29 28 27 26 25 24 Reserved Type Reset 23 22 21 20 19 18 17 16 Reserved Type Reset 15 14 13 12 11 10 9 8 Reserved Type Reset 7 6 5 4 3 2 1 0 Reserved PDDIR Type Reset RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 Bits Field Descriptions 5 0 PDDIRn GPIO Port D pin n Direction Control Bits n 0 5 0 Pin n is in input mode 1 Pin n...

Page 159: ...30 29 28 27 26 25 24 Reserved Type Reset 23 22 21 20 19 18 17 16 Reserved Type Reset 15 14 13 12 11 10 9 8 Reserved Type Reset 7 6 5 4 3 2 1 0 Reserved PDINEN Type Reset RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 Bits Field Descriptions 5 0 PDINENn GPIO Port D pin n Input Enable Control Bits n 0 5 0 Pin n input function is disabled 1 Pin n input function is enabled When the pin n input function is disabled the...

Page 160: ...rved Type Reset 23 22 21 20 19 18 17 16 Reserved Type Reset 15 14 13 12 11 10 9 8 Reserved Type Reset 7 6 5 4 3 2 1 0 Reserved PDPU Type Reset RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 Bits Field Descriptions 5 0 PDPUn GPIO Port D pin n Pull Up Selection Control Bits n 0 5 0 Pin n pull up function is disabled 1 Pin n pull up function is enabled Note When the pull up and pull down functions are both enabled th...

Page 161: ...ved Type Reset 23 22 21 20 19 18 17 16 Reserved Type Reset 15 14 13 12 11 10 9 8 Reserved Type Reset 7 6 5 4 3 2 1 0 Reserved PDPD Type Reset RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 Bits Field Descriptions 5 0 PDPDn GPIO Port D pin n Pull Down Selection Control Bits n 0 5 0 Pin n pull down function is disabled 1 Pin n pull down function is enabled Note When the pull up and pull down functions are both enabl...

Page 162: ...ved Type Reset 23 22 21 20 19 18 17 16 Reserved Type Reset 15 14 13 12 11 10 9 8 Reserved Type Reset 7 6 5 4 3 2 1 0 Reserved PDOD Type Reset RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 Bits Field Descriptions 5 0 PDODn GPIO Port D pin n Open Drain Selection Control Bits n 0 5 0 Pin n Open Drain output is disabled The output type is CMOS output 1 Pin n Open Drain output is enabled The output type is open drain ...

Page 163: ...0_0000 31 30 29 28 27 26 25 24 Reserved Type Reset 23 22 21 20 19 18 17 16 Reserved Type Reset 15 14 13 12 11 10 9 8 Reserved PDDV5 PDDV4 Type Reset RW 0 RW 0 RW 0 RW 0 7 6 5 4 3 2 1 0 PDDV3 PDDV2 PDDV1 PDDV0 Type Reset RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 Bits Field Descriptions 11 0 PDDVn 1 0 GPIO Port D pin n Drive Current Selection Control Bits n 0 5 00 4 mA source sink current 01 8 mA sour...

Page 164: ...t equal to 0x5FA0 any write operations on the PDLOCKR register will be aborted The result of a read operation on the PDLKEY field returns the GPIO Port D Lock Status which indicates whether the GPIO Port D is locked or not If the read value of the PDLKEY field is 0 this indicates that the GPIO Port D Lock function is disabled Otherwise it indicates that the GPIO Port D Lock function is enabled as ...

Page 165: ...0 RO 0 RO 0 Bits Field Descriptions 5 0 PDDINn GPIO Port D pin n Data Input Bits n 0 5 0 The input data of corresponding pin is 0 1 The input data of corresponding pin is 1 Port D Output Data Register PDDOUTR This register specifies the GPIO Port D output data Offset 0x020 Reset value 0x0000_0000 31 30 29 28 27 26 25 24 Reserved Type Reset 23 22 21 20 19 18 17 16 Reserved Type Reset 15 14 13 12 11...

Page 166: ...2 11 10 9 8 Reserved Type Reset 7 6 5 4 3 2 1 0 Reserved PDSET Type Reset WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 Bits Field Descriptions 21 16 PDRSTn GPIO Port D pin n Output Reset Control Bits n 0 5 0 No effect on the PDDOUTn bit 1 Reset the PDDOUTn bit Note that when the PDRSTn bit in this register or the PDRSTn bit in the PDRR register is enabled the reset function on the PDDOUTn bit will take effect 5 ...

Page 167: ...nding bit of the GPIO Port D output data Offset 0x028 Reset value 0x0000_0000 31 30 29 28 27 26 25 24 Reserved Type Reset 23 22 21 20 19 18 17 16 Reserved Type Reset 15 14 13 12 11 10 9 8 Reserved Type Reset 7 6 5 4 3 2 1 0 Reserved PDRST Type Reset WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 Bits Field Descriptions 5 0 PDRSTn GPIO Port D pin n Output Reset Bits n 0 5 0 No effect on the PDDOUTn bit 1 Reset the ...

Page 168: ...table pin out locations can be selected by using the peripheral I O remapping mechanism Additionally various GPIO pins can be selected to be the EXTI interrupt line by setting the EXTInPIN 3 0 field in the ESSRn register to trigger an interrupt or event Please refer to the EXTI section for more details AFIO Configuration Registers PxLOCKR GPIO Module GPIOx APB Interface Peripheral IP I O AFIO Conf...

Page 169: ...re connected to the 16 EXTI lines as shown in the accompanying figure For example the user can set the EXTI0PIN 3 0 field in the ESSR0 register to b0000 to select the GPIO PA0 pin as EXTI line 0 input Since not all the pins of the Port A D are available in all package types refer to the pin assignment section for detailed pin information The setting of the EXTInPIN 3 0 field is invalid when the co...

Page 170: ...ion 15 AF15 Table 23 AFIO Selection for Peripheral Map Example AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15 System Default GPIO ADC CMP MCTM GPTM SPI USART UART I2 C N A N A N A N A TKEY SCTM LEDC System Other Note CMP is only available for the HT32F54243 HT32F54253 devices Lock Mechanism The device also offers a lock function to lock the AFIO configuration using the GPIO ...

Page 171: ... 0 RW 0 15 14 13 12 11 10 9 8 EXTI3PIN EXTI2PIN Type Reset RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 7 6 5 4 3 2 1 0 EXTI1PIN EXTI0PIN Type Reset RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 Bits Field Descriptions 31 0 EXTInPIN 3 0 EXTIn Pin Selection n 0 7 0000 PA Bit n is selected as EXTIn source signal 0001 PB Bit n is selected as EXTIn source signal 0010 PC Bit n is selected as EXTIn source signal 0...

Page 172: ... 14 13 12 11 10 9 8 EXTI11PIN EXTI10PIN Type Reset RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 7 6 5 4 3 2 1 0 EXTI9PIN EXTI8PIN Type Reset RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 Bits Field Descriptions 31 0 EXTInPIN 3 0 EXTIn Pin Selection n 8 15 0000 PA Bit n is selected as EXTIn source signal 0001 PB Bit n is selected as EXTIn source signal 0010 PC Bit n is selected as EXTIn source signal 0011 PD ...

Page 173: ... 0 15 14 13 12 11 10 9 8 PxCFG3 PxCFG2 Type Reset RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 7 6 5 4 3 2 1 0 PxCFG1 PxCFG0 Type Reset RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 Bits Field Descriptions 31 0 PxCFGn 3 0 Alternate function selection for port x pin n n 0 7 0000 Port x pin n is selected as AF0 0001 Port x pin n is selected as AF1 1110 Port x pin n is selected as AF14 1111 Port x pin n is sele...

Page 174: ...RW 0 15 14 13 12 11 10 9 8 PxCFG11 PxCFG10 Type Reset RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 7 6 5 4 3 2 1 0 PxCFG9 PxCFG8 Type Reset RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 Bits Field Descriptions 31 0 PxCFGn 3 0 Alternate function selection for port x pin n n 8 15 0000 Port x pin n is selected as AF0 0001 Port x pin n is selected as AF1 1110 Port x pin n is selected as AF14 1111 Port x pin n is...

Page 175: ...ipheral interrupts Table 25 Exception Types Interrupt Number Exception Number Exception Type Priority Vector Address Description 0 0x000 Initial Stack Point value 1 Reset 3 Highest 0x004 Reset 14 2 NMI 2 0x008 Non Maskable Interrupt The clock stuck interrupt signal clock monitor function provided by Clock Control Unit is connected to the NMI input 13 3 Hard Fault 1 0x00C All fault classes 4 10 Res...

Page 176: ...3 4 Configurable 2 0x0B0 UART3 global interrupt 29 45 LEDC Configurable 2 0x0B4 LED Controller global interrupt 30 46 PDMA_CH0 1 4 Configurable 2 0x0B8 PDMA channel 0 1 global interrupt 31 47 PDMA_CH2 5 4 Configurable 2 0x0BC PDMA channel 2 5 global interrupt Notes 1 The exception priority can be changed using the NVIC System Handler Priority Registers For more information refer to the Arm Cortex ...

Page 177: ...0000_0000 NVIC_ICER 0x180 Interrupt Clear Enable Register 0x0000_0000 NVIC_ISPR 0x200 Interrupt Set Pending Register 0x0000_0000 NVIC_ICPR 0x280 Interrupt Clear Pending Register 0x0000_0000 NVIC_IPR0 0x400 Interrupt 0 3 Priority Register 0x0000_0000 NVIC_IPR1 0x404 Interrupt 4 7 Priority Register 0x0000_0000 NVIC_IPR2 0x408 Interrupt 8 11 Priority Register 0x0000_0000 NVIC_IPR3 0x40C Interrupt 12 ...

Page 178: ...event occurs and the corresponding EXTI wakeup enable bit is set Each EXTI line can also be masked independently Debounce Deglitch Edge Level Detection Polarity Detection Polarity Control EXTInWPOL Edge Level Control SRCnTYPE 2 0 EXTI Interrupt Control Status EXTI Event Control Status Software Activate EXTInSC EXTI 0 EXTI 15 DBnCNT 15 0 16 16 16 16 16 16 16 16 16 16 High or Low level High or Low l...

Page 179: ...event occurs Additionally the software can enable the event wakeup interrupt function by setting the EVWUPIEN bit in the EXTIWAKUPCR register and the EXTI controller will then assert an interrupt when the wakeup event occurs Set event signal to NVIC to wake up MCU SLEEPING NVIC EXTI Wakeup Event Management EXTInWFL RTC_WAKEUP LVD_WAKEUP WUPF PWRCU EXTInWEN High Low level detector EXTInWPOL 1 0 16 ...

Page 180: ...unce The application software can set the DBnEN bit in the EXTIn Interrupt Configuration Register EXTICFGRn n 0 15 to enable the corresponding pin debounce function and configure the DBnCNT field in the EXTICFGRn register so as to select an appropriate debounce time for specific applications The interrupt signal will however be delayed due to the debounce function When the device is woken up from ...

Page 181: ...0_0000 EXTICFGR8 0x020 EXTI Interrupt 8 Configuration Register 0x0000_0000 EXTICFGR9 0x024 EXTI Interrupt 9 Configuration Register 0x0000_0000 EXTICFGR10 0x028 EXTI Interrupt 10 Configuration Register 0x0000_0000 EXTICFGR11 0x02C EXTI Interrupt 11 Configuration Register 0x0000_0000 EXTICFGR12 0x030 EXTI Interrupt 12 Configuration Register 0x0000_0000 EXTICFGR13 0x034 EXTI Interrupt 13 Configuratio...

Page 182: ... 13 12 11 10 9 8 DBnCNT Type Reset RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 7 6 5 4 3 2 1 0 DBnCNT Type Reset RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 Bits Field Descriptions 31 DBnEN EXTIn Debounce Circuit Enable Bit n 0 15 0 Debounce circuit is disabled 1 Debounce circuit is enabled 30 28 SRCnTYPE EXTIn Interrupt Source Trigger Type n 0 15 SRCnTYPE 2 0 Interrupt Source Type 0 0 0 Low level Sensiti...

Page 183: ...27 26 25 24 Reserved Type Reset 23 22 21 20 19 18 17 16 Reserved Type Reset 15 14 13 12 11 10 9 8 EXTI15EN EXTI14EN EXTI13EN EXTI12EN EXTI11EN EXTI10EN EXTI9EN EXTI8EN Type Reset RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 7 6 5 4 3 2 1 0 EXTI7EN EXTI6EN EXTI5EN EXTI4EN EXTI3EN EXTI2EN EXTI1EN EXTI0EN Type Reset RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 Bits Field Descriptions 15 0 EXTInEN EXTIn Interru...

Page 184: ... Reset 15 14 13 12 11 10 9 8 EXTI15EDF EXTI14EDF EXTI13EDF EXTI12EDF EXTI11EDF EXTI10EDF EXTI9EDF EXTI8EDF Type Reset WC 0 WC 0 WC 0 WC 0 WC 0 WC 0 WC 0 WC 0 7 6 5 4 3 2 1 0 EXTI7EDF EXTI6EDF EXTI5EDF EXTI4EDF EXTI3EDF EXTI2EDF EXTI1EDF EXTI0EDF Type Reset WC 0 WC 0 WC 0 WC 0 WC 0 WC 0 WC 0 WC 0 Bits Field Descriptions 15 0 EXTInEDF EXTIn Edge Detection Flag n 0 15 0 No edge is detected 1 Positive...

Page 185: ...WC 0 WC 0 WC 0 WC 0 Bits Field Descriptions 15 0 EXTInEDS EXTIn Edge Detection Status n 0 15 0 Negative edge is detected 1 Positive edge is detected Software should write 1 to clear it EXTI Interrupt Software Set Command Register EXTISSCR This register is used to activate the EXTI interrupt Offset 0x04C Reset value 0x0000_0000 31 30 29 28 27 26 25 24 Reserved Type Reset 23 22 21 20 19 18 17 16 Res...

Page 186: ...21 20 19 18 17 16 Reserved Type Reset 15 14 13 12 11 10 9 8 EXTI15WEN EXTI14WEN EXTI13WEN EXTI12WEN EXTI11WEN EXTI10WEN EXTI9WEN EXTI8WEN Type Reset RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 7 6 5 4 3 2 1 0 EXTI7WEN EXTI6WEN EXTI5WEN EXTI4WEN EXTI3WEN EXTI2WEN EXTI1WEN EXTI0WEN Type Reset RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 Bits Field Descriptions 31 EVWUPIEN EXTI Event Wakeup Interrupt Enable B...

Page 187: ...ype Reset RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 Bits Field Descriptions 15 0 EXTInWPOL EXTIn Wakeup Polarity n 0 15 0 EXTIn wakeup is high level active 1 EXTIn wakeup is low level active EXTI Interrupt Wakeup Flag Register EXTIWAKUPFLG This register is the EXTI interrupt wakeup flag register Offset 0x058 Reset value 0x0000_0000 31 30 29 28 27 26 25 24 Reserved Type Reset 23 22 21 20 19 18 17 16 ...

Page 188: ... set thresholds There are three conversion modes to convert an analog signal to digital data The A D conversion can be operated in one shot continuous and discontinuous conversion mode A 16 bit data register is provided to store the data after conversion Analog Watchdog High Threshold Low Threshold DMA Request ADC_IN0 ADC_IN1 ADC_IN9 12 bit A D Converter ADC Control Logic Analog Watchdog Interrupt...

Page 189: ... conversion result Three conversion mode One shot conversion mode Continuous conversion mode Discontinuous conversion mode Analog watchdog for predefined voltage range monitor Lower upper threshold register Interrupt generation Various trigger start sources for conversion modes Software trigger EXTI external interrupt input pin MCTM trigger GPTM trigger BFTM0 BFTM1 BFTM2 BFTM3 trigger the BFTM2 an...

Page 190: ...n process will reset the current conversion after which a new start pulse is required to restart a new conversion Conversion Mode The A D has three operating conversion modes The conversion modes are One Shot Conversion Mode Continuous Conversion Mode and Discontinuous Conversion mode Details are provided later One Shot Conversion Mode In the One Shot Conversion mode the ADC will perform conversio...

Page 191: ...verter will operate in the Continuous Conversion Mode which can be started by a software trigger a comparator output transition event an external EXTI event or a TM event determined by the Trigger Control Register ADCTCR and the Trigger Source Register ADCTSR After conversion The converted data will be stored in the 16 bit ADCDRy y 0 7 registers The ADC group cycle end of conversion event raw stat...

Page 192: ...ecified in the ADCLSTn registers After n conversions have completed the subgroup EOC interrupt raw flag ADIRAWG in the ADCIRAW register will be asserted The A D converter will now not continue to perform the next n conversions until the next trigger event occurs The conversion cycle will end after all the group channels of which the total number is defined by the ADSEQL 2 0 bits in the ADCCR regis...

Page 193: ...g the software trigger bit ADSC in the ADCTSR register for the group channel when the software trigger enable bit ADSW in the ADCTCR register is set to 1 After the A D converter starts converting the analog data the corresponding enable bit ADSC will be cleared to 0 automatically The A D converter can also be triggered to start a group conversion by a TM event The TM events include a GPTM or MCTM ...

Page 194: ...28 Data Format in ADCDR 15 0 Description ADCDR register Data Format Right aligned 0_0_0_0_d11_d10_d9_d8_d7_d6_d5_d4_d3_d2_d1_d0 Analog Watchdog The A D converter includes a watchdog function to monitor the converted data There are two kinds of thresholds for the watchdog monitor function known as the watchdog lower threshold and watchdog upper threshold which are specified by the ADLT bit field an...

Page 195: ...sion is less than the lower threshold or higher than the upper threshold the watchdog lower or upper threshold interrupt raw flag ADIRAWL or ADIRAWU in the ADCIRAW register will be asserted When the ADIRAWL or ADIRAWU flag is asserted and the corresponding interrupt enable bit ADIEL or ADIEU in the ADCIER register is set a watchdog lower or upper threshold interrupt will be generated The A D Conve...

Page 196: ...DCCR 0x000 ADC Conversion Control Register 0x0000_0000 ADCLST0 0x004 ADC Conversion List Register 0 0x0000_0000 ADCLST1 0x008 ADC Conversion List Register 1 0x0000_0000 ADCSTR 0x020 ADC Input Sampling Time Register 0x0000_0000 ADCDR0 0x030 ADC Conversion Data Register 0 0x0000_0000 ADCDR1 0x034 ADC Conversion Data Register 1 0x0000_0000 ADCDR2 0x038 ADC Conversion Data Register 2 0x0000_0000 ADCDR...

Page 197: ... 4 3 2 1 0 ADCEN ADCRST Reserved ADMODE Type Reset RW 0 RW 0 RW 0 RW 0 Bits Field Descriptions 18 16 ADSUBL ADC Conversion Subgroup Length The ADSUBL field specifies the conversion channel length of each subgroup in the Discontinuous Conversion Mode Subgroup length ADSUBL 2 0 1 If the sequence length ADSEQL 2 0 1 is not a multiple of the subgroup length ADSUBL 2 0 1 the last subgroup will be the r...

Page 198: ... will be executed on the specific channels for the whole conversion sequence once 01 Reserved 10 Continuous mode After a start trigger the conversion will be executed on the specific channels for the whole sequence continuously until conversion mode is changed 11 Discontinuous mode After a start trigger the conversion will be executed on the current subgroup When the last subgroup is finished the ...

Page 199: ... 0 RW 0 RW 0 RW 0 RW 0 7 6 5 4 3 2 1 0 Reserved ADSEQ0 Type Reset RW 0 RW 0 RW 0 RW 0 RW 0 Bits Field Descriptions 28 24 ADSEQ3 ADC Conversion Sequence Select 3 Select the ADC input channel for the 3rd ADC conversion sequence 0x00 ADC_IN0 0x01 ADC_IN1 0x02 ADC_IN2 0x03 ADC_IN3 0x04 ADC_IN4 0x05 ADC_IN5 0x06 ADC_IN6 0x07 ADC_IN7 0x08 ADC_IN8 0x09 ADC_IN9 0x0A Analog ground VSSA 0x0B VDDA 0x0C Inter...

Page 200: ... 0 RW 0 RW 0 RW 0 RW 0 7 6 5 4 3 2 1 0 Reserved ADSEQ4 Type Reset RW 0 RW 0 RW 0 RW 0 RW 0 Bits Field Descriptions 28 24 ADSEQ7 ADC Conversion Sequence Select 7 Select the ADC input channel for the 7th ADC conversion sequence 0x00 ADC_IN0 0x01 ADC_IN1 0x02 ADC_IN2 0x03 ADC_IN3 0x04 ADC_IN4 0x05 ADC_IN5 0x06 ADC_IN6 0x07 ADC_IN7 0x08 ADC_IN8 0x09 ADC_IN9 0x0A Analog ground VSSA 0x0B VDDA 0x0C Inter...

Page 201: ...ecifies the A D converter input channel sampling time Offset 0x020 Reset value 0x0000_0000 31 30 29 28 27 26 25 24 Reserved Type Reset 23 22 21 20 19 18 17 16 Reserved Type Reset 15 14 13 12 11 10 9 8 Reserved Type Reset 7 6 5 4 3 2 1 0 ADST Type Reset RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 Bits Field Descriptions 7 0 ADST ADC Input Channel Sampling Time Sampling time ADST 7 0 1 5 CK_ADC clocks ...

Page 202: ...C Reset value 0x0000_0000 31 30 29 28 27 26 25 24 ADVLDy Reserved Type Reset RC 0 23 22 21 20 19 18 17 16 Reserved Type Reset 15 14 13 12 11 10 9 8 ADDy Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 7 6 5 4 3 2 1 0 ADDy Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 Bits Field Descriptions 31 ADVLDy ADC Conversion Data of Sequence Order No y Valid Bit y 0 7 0 Data are invalid or have been...

Page 203: ...isable conversion trigger by CMP output transition 1 Enable conversion trigger by CMP output transition This bit is only available for the HT32F54243 HT32F54253 devices 3 TM1 ADC Conversion BFTM Event Trigger enable control 0 Disable conversion trigger by BFTM events 1 Enable conversion trigger by BFTM events 2 TM0 ADC Conversion GPTM or MCTM Event Trigger enable control 0 Disable conversion trigg...

Page 204: ...M CH2O event 100 GPTM or MCTM CH3O event Others Reserved Should not be used to avoid unpredictable results 20 CMPS CMP Trigger Selection of ADC Conversion 0 CMP0 1 CMP1 This bit is only available for the HT32F54243 HT32F54253 devices 23 22 19 TM1S BFTM Trigger Timer Selection of ADC Conversion 000 BFTM0 001 BFTM1 Others Reserved Should not be used to avoid unpredictable results 18 16 TM0S GPTM or ...

Page 205: ...the watchdog monitor function the status field value should first be stored in the user defined memory location in the corresponding ISR Otherwise the ADUCH field will be changed if another input channel converted data is higher than the upper threshold 19 16 ADLCH Lower Threshold Channel Status 0000 ADC_IN0 converted data is lower then the lower threshold 0001 ADC_IN1 converted data is lower then...

Page 206: ...r ADCTR This register specifies the upper and lower threshold of the ADC watchdog function Offset 0x07C Reset value 0x0000_0000 31 30 29 28 27 26 25 24 Reserved ADUT Type Reset RW 0 RW 0 RW 0 RW 0 23 22 21 20 19 18 17 16 ADUT Type Reset RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 15 14 13 12 11 10 9 8 Reserved ADLT Type Reset RW 0 RW 0 RW 0 RW 0 7 6 5 4 3 2 1 0 ADLT Type Reset RW 0 RW 0 RW 0 RW 0 RW 0...

Page 207: ...s disabled 1 ADC data register overwrite interrupt is enabled 17 ADIEU ADC Watchdog Upper Threshold Interrupt enable 0 ADC watchdog upper threshold interrupt is disabled 1 ADC watchdog upper threshold interrupt is enabled 16 ADIEL ADC Watchdog Lower Threshold Interrupt enable 0 ADC watchdog lower threshold interrupt is disabled 1 ADC watchdog lower threshold interrupt is enabled 2 ADIEC ADC Cycle ...

Page 208: ...ter overwrite event does not occur 1 ADC data register overwrite event occurs 17 ADIRAWU ADC Watchdog Upper Threshold Interrupt Raw Status 0 ADC watchdog upper threshold event does not occur 1 ADC watchdog upper threshold event occurs 16 ADIRAWL ADC Watchdog Lower Threshold Interrupt Raw Status 0 ADC watchdog lower threshold event does not occurs 1 ADC watchdog lower threshold event occurs 2 ADIRA...

Page 209: ...shold interrupt does not occur or the watchdog upper threshold interrupt is disabled 1 ADC watchdog upper threshold interrupt occurs as the watchdog upper threshold interrupt is enabled 16 ADISRL ADC Watchdog Lower Threshold Interrupt Status 0 ADC watchdog lower threshold interrupt does not occur or the watchdog lower threshold interrupt is disabled 1 ADC watchdog lower threshold interrupt occurs ...

Page 210: ...WO 0 15 14 13 12 11 10 9 8 Reserved Type Reset 7 6 5 4 3 2 1 0 Reserved ADICLRC ADICLRG ADICLRS Type Reset WO 0 WO 0 WO 0 Bits Field Descriptions 24 ADICLRO ADC Data Register Overwrite Interrupt Status Clear Bit 0 No effect 1 Clear ADISRO and ADIRAWO bits 17 ADICLRU ADC Watchdog Upper Threshold Interrupt Status Clear Bit 0 No effect 1 Clear ADISRU and ADIRAWU bits 16 ADICLRL ADC Watchdog Lower Thr...

Page 211: ...ved Type Reset 7 6 5 4 3 2 1 0 Reserved ADDMAC ADDMAG ADDMAS Type Reset RW 0 RW 0 RW 0 Bits Field Descriptions 2 ADDMAC ADC Cycle EOC DMA Request Enable Bit 0 ADC cycle end of conversion DMA request is disabled 1 ADC cycle end of conversion DMA request is enabled 1 ADDMAG ADC Subgroup EOC DMA Request Enable Bit 0 ADC subgroup end of conversion DMA request is disabled 1 ADC subgroup end of conversi...

Page 212: ... Type Reset 23 22 21 20 19 18 17 16 Reserved Type Reset 15 14 13 12 11 10 9 8 Reserved MVDDAEN Type Reset RW 0 7 6 5 4 3 2 1 0 Reserved VREFSEL Reserved VREFEN Type Reset RW 0 RW 0 RW 0 Bits Field Descriptions 8 MVDDAEN Measurement VDDA 2 power Enable 0 Disable 1 Enable measurement VDDA 2 power 5 4 VREFSEL Voltage Reference Output Selection 00 2 5 V 01 3 0 V 10 4 0 V 11 4 5 V These bits select the...

Page 213: ...cture Privilege Information Block 31 30 29 28 27 26 25 24 Reserved Type Reset 23 22 21 20 19 18 17 16 Reserved Type Reset 15 14 13 12 11 10 9 8 Reserved Type Reset 7 6 5 4 3 2 1 0 Reserved VREFVAL Type Reset RO X RO X RO X RO X RO X RO X Bits Field Descriptions 5 0 VREFVAL Voltage Reference Calibration Value During the manufacturing process the calibration data of the internal voltage reference is...

Page 214: ...OL Sync Programmable Hysteresis Programmable Response Time CMPEN PCLK MUX 0 1 MUX CMPSTS GPIO AFIO COUT To EXTI Wakeup Event Management CMP Status Interrupt Request ADC GPTM MCTM Comparator Analog IP MUX 0 1 VREF CVRSS VDDA Domain VCORE Domain VCVR MUX 0 1 SYNCSEL Control Interrupt Generator CMPOUT Reserved Figure 35 Comparator Block Diagram Features Rail to rail comparator Configurable negative i...

Page 215: ...ock diagram of the comparator voltage reference is shown in the figure above It also has a power down function to conserve power when the reference is not used The comparator voltage reference provides 256 distinct levels The equation used to calculate the value of the reference voltage is as follows VCVR CVRVAL VRP VSSA 255 R R R R R R R 256 1 Mux CVREN CVRVAL 7 0 VDDA VREF CVRSS 0 CVRSS 1 VCVR V...

Page 216: ... into the comparator rising edge flag bit CMPRF in the Comparator Transition Flag Register CMPTFRn will clear the CMPRF bit The comparator output falling edge interrupt also has the same corresponding interrupt setting A block diagram of interrupt signals for comparators is shown in the following figure CMPRIEN CMPRF CMPFF CMPFIEN NVIC CMP Interrupt CMP0 CMPRIEN CMPRF CMPFF CMPFIEN CMP1 Figure 37 ...

Page 217: ...d in the Comparator Control Register CMPCRn The write protection function is enabled by default Before configuring the bits 15 0 in the Comparator Control Register CMPCRn the pattern 0x9C3A must first be written into the register protection bits 31 16 in the CMPCRn register Then the write protection will be disabled and the bits 15 0 can be configured by application program For the same reason the...

Page 218: ...C3A Disable the CMPCRn register write protection Others values Enable the CMPCRn register write protection For read operation 0x0000 CMPCRn register write protection is disabled 0x0001 CMPCRn register write protection is enabled These bits are used to enable or disable the write protection of the field 14 0 in the CMPCRn register Enabling the write protection will make the field 14 0 in the CMPCRn...

Page 219: ... 8 bit CVR output to CN pin 1 Enable 8 bit CVR output to CN pin 8 CVREN Comparator Voltage Reference Enable 0 Disable 8 bit CVR 1 Enable 8 bit CVR Setting this bit will enable the CVR to output a configured reference voltage 7 SYNSEL Synchronization Selection 0 Asynchronous signal of comparator output is selected 1 Synchronous signal of comparator output is selected The synchronous comparator outp...

Page 220: ...0 29 28 27 26 25 24 Reserved Type Reset 23 22 21 20 19 18 17 16 Reserved Type Reset 15 14 13 12 11 10 9 8 Reserved Type Reset 7 6 5 4 3 2 1 0 CVRVAL Type Reset RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 Bits Field Descriptions 7 0 CVRVAL Comparator Voltage Reference Value There are 256 levels of the comparator voltage reference which is set using the CVRVAL bits The relationship between the CVRVAL re...

Page 221: ... value 0x0000_0000 31 30 29 28 27 26 25 24 Reserved Type Reset 23 22 21 20 19 18 17 16 Reserved Type Reset 15 14 13 12 11 10 9 8 Reserved Type Reset 7 6 5 4 3 2 1 0 Reserved CMPRIEN CMPFIEN Type Reset RW 0 RW 0 Bits Field Descriptions 1 CMPRIEN Comparator Output Rising Edge Interrupt Enable 0 Disable comparator output rising edge interrupt 1 Enable comparator output rising edge interrupt 0 CMPFIEN...

Page 222: ...ected is a copy of the comparator output state after the polarity selection and synchronization by the PCLK clock 8 CMPFDEN Comparator Output Falling Edge Detection Enable 0 Disable comparator output falling edge detection 1 Enable comparator output falling edge detection Note that the signal to be detected is a copy of the comparator output state after the polarity selection and synchronization b...

Page 223: ...r CH1CCR CH2 Capture Compare Register CH2CCR CH3 Capture Compare Register CH3CCR TM_CNT CH0 Capture Compare Register CH0CCR Reload Register CRR Output Control Output Control Output Control Output Control GT_CH0O GT_CH1O GT_CH2O GT_CH3O TI1 TI2 TI3 PSC PRESCALER Input Filter Polarity Selection Edge Detection Edge Detector ITI0 ITI1 ITI2 TI0S0ED TI0S1ED TI1S0ED TI1S1ED Input Filter Polarity Selectio...

Page 224: ...r with external signals and to interconnect several timers together Interrupt PDMA generation with the following events PDMA is only available for the HT32F54243 HT32F54253 devices Update event Trigger event Input capture event Output compare match event GPTM Master Slave mode controller Functional Descriptions Counter Mode Up Counting In this mode the counter counts continuously from 0 to the cou...

Page 225: ...hich is defined in the CRR register to 0 in a count down direction then restarts from the counter reload value and generates a counter underflow event This action will continue repeatedly The counting direction bit DIR in the CNTCFR register should be set to 1 for the down counting mode When the update event is set by the UEVG bit in the EVGR register the counter value will also be initialized to ...

Page 226: ...ring Write a new value Counter Overflow 1 2 3 Software clearing Figure 42 Center aligned Counting Example Clock Controller The following describes the Timer Module clock controller which determines the clock source of the internal prescaler counter Internal APB clock fCLKIN The default internal clock source is the APB clock fCLKIN used to drive the counter prescaler when the slave mode is disabled...

Page 227: ...0x0 When the STI signal is selected as the clock source the internal edge detection circuitry will generate a clock pulse during each STI signal rising edge to drive the counter prescaler It is important to note that if the TRSEL field is set to 0x0 to select the software UEVG bit as the trigger source then when the SMSEL field is set to 0x7 the counter will be updated instead of counting PSCR CRR...

Page 228: ... stimulate some GPTM functions which are triggered by a trigger signal rising edge Trigger Controller Block Edge Trigger Mux Level Trigger Mux Edge Detection ITI0 ITI1 ITI2 ITI0ED ITI1ED ITI2ED STI TRSEL 2 0 TRSEL 3 0 1 0 S W Set UEVG Bit TI0S0 TI1S1 ITI0 ITI1 ITI2 Level Trigger Source Internal ITIx Channel input TIn Software UEVG bit fCLKIN STI_S0 STI_S1 000 001 010 011 others Reserved 000 001 01...

Page 229: ...e occurs the update event software generation bit named UEVG will automatically be asserted by hardware and the trigger event flag will also be set Then the counter and prescaler will be reinitialized Although the UEVG bit is set to 1 by hardware the update event does not really occur It depends upon whether the update event disable control bit UEVDIS is set to 1 or not If the UEVDIS is set to 1 t...

Page 230: ...signal polarity 0 STI source signal Sync polarity 1 Figure 47 GPTM in Pause Mode Trigger Mode After the counter is disabled to count the counter can resume counting when an STI rising edge signal occurs When an STI rising edge occurs the counter will start to count from the current value in the counter Note that if the STI signal is selected to be derived from the UEVG bit software trigger the cou...

Page 231: ...drive another GPTM or TM if exists which is configured in the Slave Mode GPTMn Master MTO ITI GPTMm TMm Slave MMSEL SMSEL TSE TRSEL Figure 49 Master GPTMn and Slave GPTMm TMm Connection The Master Mode Selection field MMSEL in the MDCFR register is used to select the MTO source for synchronizing another slave GPTM or TM if exists Channel 0 Capture Compare event MTO UEVG bit Counter enable signal U...

Page 232: ...en used in the input capture mode the counter value is captured into the CHxCCR shadow register first and then transferred into the CHxCCR preload register when the capture event occurs When used in the compare match output mode the contents of the CHxCCR preload register is copied into the associated shadow register the counter value is then compared with the register value CHxCCR Preload Registe...

Page 233: ...TIx The following example shows how to configure the GPTM operated in the input capture mode to measure the high pulse width and the input period on the GT_CH0 pin using channel 0 and channel 1 The basic steps are shown as follows Configure the capture channel 0 CH0CCS 0x1 to select the TI0 signal as the capture input Configure the CH0P bit to 0 to choose the rising edge of the TI0 input as the ac...

Page 234: ...H2 signals The channel input signal TIx is sampled by a digital filter to generate a filtered input signal TIxFP Then the channel polarity and the edge detection block can generate a TIxS0ED or TIxS1ED signal for the input capture function The effective input event number can be set by the channel capture input source prescaler setting field CHxPSC Filter TI0FP TI0FN TI0F GT_CH0 fsampling CH0P Fil...

Page 235: ...S3ED TI3S3ED fCLKIN fsampling fsampling TI2 TI3 Figure 55 Channel 2 and Channel 3 Input Stages Digital Filter The digital filters are embedded in the input stage for the GT_CH0 GT_CH3 pins respectively The digital filter in the GPTM is an N event counter where N refers to how many valid transitions are necessary to output a filtered signal The N value can be 0 2 4 5 6 or 8 according to the user se...

Page 236: ...ing table The Quadrature decoder can be regarded as an external clock with a directional selection This means that the counter counts continuously in the interval between 0 and the counter reload value Therefore users must configure the CRR register before the counter starts to count Filter TI0FP TI0FN TI0F GT_CH0 fsampling CH0P Filter TI1FP TI1FN TI1F CH1P GT_CH1 TI0S0 TI1S0 TI0S1 TI1S1 TRCED CH0...

Page 237: ...Down Up X X TI1S1 Low Up Down X X TI0S0 High X X Up Down TI0S0 Low X X Down Up Note means no counting X impossible TI0 TI1 Up Down Quadrature Decoder Counting on Both TI0 TI1 CH0P 0 CH1P 0 Figure 58 Both TI0 and TI1 Quadrature Decoder Counting Output Stage The GPTM has four channels for compare match single pulse or PWM output function The channel output GT_CHxO is controlled by the CHxOM CHxP and...

Page 238: ...e count direction and the relationship between the counter value and the CHxCCR content There are also two modes which will force the output into an inactive or active state irrespective of the CHxCCR content or counter values With regard to a more detailed description refer to the relative bit definition The accompanying table shows a summary of the output type setup Table 32 Compare Match Output...

Page 239: ... Time Output toggle preload enable CHxCCR New value 3 Update CHxCCR value 1 2 3 TME CHxOREF UEV Update Event Figure 61 Toggle Mode Channel Output Reference Signal CHxPRE 1 Counter Value CRR CHxCCR CHxOREF CHxOM 0x6 CHxCCIF CHxOREF Counter Value 100 0 CHxOM 0x7 CHxCCR CRR CHxOREF CHxCCIF CHxCCIF CHxOREF CHxCCR 0x0000 CRR Counter Value Figure 62 PWM Mode Channel Output Reference Signal and Counter i...

Page 240: ...HxOM 0x7 CHxOREF 100 CRR CHxCCR Counter Value CHxOREF CHxCCIF CHxCCIF Figure 63 PWM Mode Channel Output Reference Signal and Counter in Down counting Mode Up counting Down counting CRR 5 CHxCCR 3 CMSEL 0x1 CHxCCIF CHxCCR 4 CHxCCIF CHxCCR 5 CHxCCR 0 CHxCCIF CHxCCIF 100 0 0 1 2 3 4 5 4 3 2 1 0 1 Figure 64 PWM Mode Channel Output Reference Signal and Counter in Centre aligned Mode ...

Page 241: ...in the CNTCFR register can determine whether the update event occurs or not When the update event occurs the corresponding update event interrupt will be generated depending upon whether the update event interrupt generation function is enabled or not by configuring the UGDIS bit in the CNTCFR register For more detailed description refer to the UEVDIS and UGDIS bit definition in the CNTCFR registe...

Page 242: ...lse and then keep the TME bit at a high state until the update event occurs or the TME bit is written to 0 by software If the TME bit is cleared to 0 using software the counter will be stopped and its value held If the TME bit is automatically cleared to 0 by a hardware update event the counter will be reinitialized Trigger by S W Trigger by STI Cleared by Update Event Flag is set by compare match...

Page 243: ...bit in each CHxOCFR register After an STI rising edge trigger occurs in the single pulse mode the CHxOREF signal will immediately be forced to the state which the CHxOREF signal will change to as the compare match event occurs without taking the comparison result into account The CHxIMAE bit is available only when the output channel is configured to operate in the PWM mode 1 or PWM mode 2 and the ...

Page 244: ...xOREF CHxOREF PWM center aligned mode CRR 8 CCR 3 ACR X PWM center aligned mode CRR 8 CCR 5 ACR X Asymmetric PWM center aligned mode CRR 8 CCR 3 ACR 5 Asymmetric PWM center aligned mode CRR 8 CCR 5 ACR 3 CCR 3 CCR 5 CCR 3 ACR 5 CCR 5 ACR 3 Phase delay 2 CRR 8 Figure 68 Asymmetric PWM Mode versus Center Aligned Counting Mode Timer Interconnection The timers can be internally connected together for ...

Page 245: ...gger another Timer Start Counting Configure GPTM to operate in the master mode to send its Update Event UEV as the trigger output MMSEL 0x2 Configure the GPTM period by setting the CRR register Configure PWM0 to get the input trigger source from the GPTM trigger output TRSEL 0xA Configure PWM0 to be in the slave trigger mode SMSEL 0x6 Start GPTM by writing 1 to the TME bit 14 15 00 01 02 FB FC FA ...

Page 246: ...PTM to be in the slave trigger mode SMSEL 0x6 Enable the GPTM master timer synchronization function by setting the TSE bit in the MDCFR register to 1 to synchronize the slave timer Configure PWM0 to receive its input trigger source from the GPTM trigger output TRSEL 0xA Configure PWM0 to be in the slave trigger mode SMSEL 0x6 TI0 TI0FP fDTS fCLKIN TI0S0ED GPTM TME bit GPTM TEVIF TSE 1 Delay GPTM C...

Page 247: ...ts if the corresponding enable control bits are set to 1 to enable the PDMA access These events are the GPTM update events trigger events and channel capture compare events When the PDMA request is generated from the GPTM channel it can be derived from the channel capture compare event or the GPTM update event selected by the channel PDMA selection bit CHCCDS for all channels For more detailed PDM...

Page 248: ...OCFR 0x044 Channel 1 Output Configuration Register 0x0000_0000 CH2OCFR 0x048 Channel 2 Output Configuration Register 0x0000_0000 CH3OCFR 0x04C Channel 3 Output Configuration Register 0x0000_0000 CHCTR 0x050 Channel Control Register 0x0000_0000 CHPOLR 0x054 Channel Polarity Configuration Register 0x0000_0000 DICTR 0x074 Timer PDMA Interrupt Control Register 0x0000_0000 EVGR 0x078 Timer Event Genera...

Page 249: ...de or when used as a Quadrature decoder 17 16 CMSEL Counter Mode Selection 00 Edge aligned mode Normal up counting and down counting available for this mode Counting direction is defined by the DIR bit 01 Center aligned mode 1 The counter counts up and down alternatively The compare match interrupt flag is set during the count down period 10 Center aligned mode 2 The counter counts up and down alt...

Page 250: ...neration through the slave mode 1 Disable the update event However the counter and the prescaler are reinitialized if the UEVG bit is set or if a hardware restart is received from the slave mode Timer Mode Configuration Register MDCFR This register specifies the GPTM master and slave mode selection and single pulse mode Offset 0x004 Reset value 0x0000_0000 31 30 29 28 27 26 25 24 Reserved SPMSET T...

Page 251: ...l is used as the trigger output 010 Update Mode The update event is used as the trigger output according to one of the following cases when the UEVDIS bit is cleared to 0 1 Counter overflow underflow 2 Software setting UEVG 3 Slave trigger input when used in slave restart mode 011 Capture Compare Mode When a Channel 0 capture or compare match event occurs it will generate a positive pulse used as ...

Page 252: ...en the TI0 and TI1 signals to drive the counter prescaler A transition of one channel edge is used in the quadrature decoder mode 3 depending upon the other channel level 100 Restart Mode The counter value restarts from 0 or the CRR shadow register value depending upon the counter mode on the rising edge of the STI signal The registers will also be updated 101 Pause Mode The counter starts to coun...

Page 253: ...its Field Descriptions 3 0 TRSEL Trigger Source Selection These bits are used to select the trigger input STI for counter synchronization 0000 Software Trigger by setting the UEVG bit 0001 Filtered input of channel 0 TI0S0 0010 Filtered input of channel 1 TI1S1 0011 Reserved 1000 Channel 0 Edge Detector TI0BED 1001 Internal Timing Module Trigger 0 ITI0 1010 Internal Timing Module Trigger 1 ITI1 10...

Page 254: ...eld Descriptions 16 CHCCDS Channel PDMA Event Selection 0 Channel PDMA request derived from the channel capture compare event 1 Channel PDMA request derived from the Update event 1 CRBE Counter Reload Register Buffer Enable 0 Counter reload register can be updated immediately 1 Counter reload register cannot be updated until the update event occurs 0 TME Timer Enable Bit 0 GPTM off 1 GPTM on GPTM ...

Page 255: ...9 18 CH0PSC Channel 0 Capture Input Source Prescaler Setting These bits define the effective events of the channel 0 capture input Note that the prescaler is reset once the Channel 0 Capture Compare Enable bit CH0E in the Channel Control register named CHCTR is cleared to 0 00 No prescaler channel 0 capture input signal is chosen for each active event 01 Channel 0 Capture input signal is chosen fo...

Page 256: ... fDTS 32 N 5 1110 fsampling fDTS 32 N 6 1111 fsampling fDTS 32 N 8 Channel 1 Input Configuration Register CH1ICFR This register specifies the channel 1 input mode configuration Offset 0x024 Reset value 0x0000_0000 31 30 29 28 27 26 25 24 Reserved Type Reset 23 22 21 20 19 18 17 16 Reserved CH1PSC CH1CCS Type Reset RW 0 RW 0 RW 0 RW 0 15 14 13 12 11 10 9 8 Reserved Type Reset 7 6 5 4 3 2 1 0 Reserv...

Page 257: ...the CH1E bit is cleared to 0 3 0 TI1F Channel 1 Input Source TI1 Filter Setting These bits define the frequency divided ratio used to sample the TI1 signal The Digital filter in the GPTM is an N event counter where N is defined as how many valid transitions are necessary to output a filtered signal 0000 No filter the sampling clock is fSYSTEM 0001 fsampling fCLKIN N 2 0010 fsampling fCLKIN N 4 001...

Page 258: ...annel 2 capture input Note that the prescaler is reset once the Channel 2 Capture Compare Enable bit CH2E in the Channel Control register named CHCTR is cleared to 0 00 No prescaler channel 2 capture input signal is chosen for each active event 01 Channel 2 Capture input signal is chosen for every 2 events 10 Channel 2 Capture input signal is chosen for every 4 events 11 Channel 2 Capture input si...

Page 259: ... fDTS 32 N 5 1110 fsampling fDTS 32 N 6 1111 fsampling fDTS 32 N 8 Channel 3 Input Configuration Register CH3ICFR This register specifies the channel 3 input mode configuration Offset 0x02C Reset value 0x0000_0000 31 30 29 28 27 26 25 24 Reserved Type Reset 23 22 21 20 19 18 17 16 Reserved CH3PSC CH3CCS Type Reset RW 0 RW 0 RW 0 RW 0 15 14 13 12 11 10 9 8 Reserved Type Reset 7 6 5 4 3 2 1 0 Reserv...

Page 260: ...the CH3E bit is cleared to 0 3 0 TI3F Channel 3 Input Source TI3 Filter Setting These bits define the frequency divided ratio used to sample the TI3 signal The Digital filter in the GPTM is an N event counter where N is defined as how many valid transitions are necessary to output a filtered signal 0000 No filter the sampling clock is fSYSTEM 0001 fsampling fCLKIN N 2 0010 fsampling fCLKIN N 4 001...

Page 261: ...e Immediate Active Mode is enabled The CH0OREF signal will be forced to the compare matched level immediately after an available trigger event occurs irrespective of the result of the comparison between the CNTR and the CH0CCR values The effective duration ends automatically at the next overflow or underflow event Note The CH0IMAE bit is available only if the channel 0 is configured to be operated...

Page 262: ...active level 0111 PWM mode 2 During up counting channel 0 is has an inactive level when CNTR CH0CCR or otherwise has an active level During down counting channel 0 has an active level when CNTR CH0CCR or otherwise has an inactive level 1110 Asymmetric PWM mode 1 During up counting channel 0 has an active level when CNTR CH0CCR or otherwise has an inactive level During down counting channel 0 has a...

Page 263: ...e Immediate Active Mode is enabled The CH1OREF signal will be forced to the compare matched level immediately after an available trigger event occurs irrespective of the result of the comparison between the CNTR and the CH1CCR values The effective duration ends automatically at the next overflow or underflow event Note The CH1IMAE bit is available only if the channel 1 is configured to be operated...

Page 264: ...n active level 0111 PWM mode 2 During up counting channel 1 has an inactive level when CNTR CH1CCR or otherwise has an active level During down counting channel 1 has an active level when CNTR CH1CCR or otherwise has an inactive level 1110 Asymmetric PWM mode 1 During up counting channel 1 has an active level when CNTR CH1CCR or otherwise has an inactive level During down counting channel 1 has an...

Page 265: ...e Immediate Active Mode is enabled The CH2OREF signal will be forced to the compare matched level immediately after an available trigger event occurs irrespective of the result of the comparison between the CNTR and the CH2CCR values The effective duration ends automatically at the next overflow or underflow event Note The CH2IMAE bit is available only if the channel 2 is configured to be operated...

Page 266: ...n active level 0111 PWM mode 2 During up counting channel 2 has an inactive level when CNTR CH2CCR or otherwise has an active level During down counting channel 2 has an active level when CNTR CH2CCR or otherwise has an inactive level 1110 Asymmetric PWM mode 1 During up counting channel 2 has an active level when CNTR CH2CCR or otherwise has an inactive level During down counting channel 2 has an...

Page 267: ...e Immediate Active Mode is enabled The CH3OREF signal will be forced to the compare matched level immediately after an available trigger event occurs irrespective of the result of the comparison between the CNTR and the CH3CCR values The effective duration ends automatically at the next overflow or underflow event Note The CH3IMAE bit is available only if the channel 3 is configured to be operated...

Page 268: ...n active level 0111 PWM mode 2 During up counting channel 3 has an inactive level when CNTR CH3CCR or otherwise has an active level During down counting channel 3 has an active level when CNTR CH3CCR or otherwise has an inactive level 1110 Asymmetric PWM mode 1 During up counting channel 3 has an active level when CNTR CH3CCR or otherwise has an inactive level During down counting channel 3 has an...

Page 269: ... generated on the corresponding output pin 4 CH2E Channel 2 Capture Compare Enable Channel 2 is configured as an input CH2CCS 0x1 0x2 0x3 0 Input Capture Mode is disabled 1 Input Capture Mode is enabled Channel 2 is configured as an output CH2CCS 0x0 0 Off Channel 2 output signal CH2O is not active 1 On Channel 2 output signal CH2O is generated on the corresponding output pin 2 CH1E Channel 1 Capt...

Page 270: ...nel 3 Output is active high 1 Channel 3 Output is active low 4 CH2P Channel 2 Capture Compare Polarity When Channel 2 is configured as an input CH2CCS 0x1 0x2 0x3 0 capture event occurs on a Channel 2 rising edge 1 capture event occurs on a Channel 2 falling edge When Channel 2 is configured as an output CH2CCS 0x0 0 Channel 2 Output is active high 1 Channel 2 Output is active low 2 CH1P Channel 1...

Page 271: ...isabled 1 Update event PDMA request is enabled 19 CH3CCDE Channel 3 Capture Compare PDMA Request Enable 0 Channel 3 PDMA request is disabled 1 Channel 3 PDMA request is enabled 18 CH2CCDE Channel 2 Capture Compare PDMA Request Enable 0 Channel 2 PDMA request is disabled 1 Channel 2 PDMA request is enabled 17 CH1CCDE Channel 1 Capture Compare PDMA Request Enable 0 Channel 1 PDMA request is disabled...

Page 272: ... 16 Reserved Type Reset 15 14 13 12 11 10 9 8 Reserved TEVG Reserved UEVG Type Reset WO 0 WO 0 7 6 5 4 3 2 1 0 Reserved CH3CCG CH2CCG CH1CCG CH0CCG Type Reset WO 0 WO 0 WO 0 WO 0 Bits Field Descriptions 10 TEVG Trigger Event Generation The trigger event TEV can be generated by setting this bit It is cleared by hardware automatically 0 No action 1 TEVIF flag is set 8 UEVG Update Event Generation Th...

Page 273: ...el 2 is configured as an input the counter value is captured into the CH2CCR register and then the CH2CCIF bit is set If Channel 2 is configured as an output the CH2CCIF bit is set 1 CH1CCG Channel 1 Capture Compare Generation A Channel 1 capture compare event can be generated by setting this bit It is cleared by hardware automatically 0 No action 1 Capture compare event is generated on channel 1 ...

Page 274: ...it is set by hardware on an update event and is cleared by software 0 No update event occurs 1 Update event occurs Note The update event is derived from the following conditions The counter overflows or underflows The UEVG bit is asserted A restart trigger event occurs from the slave trigger input 7 CH3OCF Channel 3 Over Capture Flag This flag is set by hardware and cleared by software 0 No over c...

Page 275: ...or by reading the CH3CCR register 2 CH2CCIF Channel 2 Capture Compare Interrupt Flag Channel 2 is configured as an output 0 No match event occurs 1 The content of the counter CNTR has matched the content of the CH2CCR register This flag is set by hardware when the counter value matches the CH2CCR value except in the center aligned mode It is cleared by software Channel 2 is configured as an input ...

Page 276: ...n the center aligned mode It is cleared by software Channel 0 is configured as an input 0 No input capture occurs 1 Input capture occurs This bit is set by hardware on a capture event It is cleared by software or by reading the CH0CCR register Timer Counter Register CNTR This register stores the timer counter value Offset 0x080 Reset value 0x0000_0000 31 30 29 28 27 26 25 24 Reserved Type Reset 23...

Page 277: ...x0000_0000 31 30 29 28 27 26 25 24 Reserved Type Reset 23 22 21 20 19 18 17 16 Reserved Type Reset 15 14 13 12 11 10 9 8 PSCV Type Reset RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 7 6 5 4 3 2 1 0 PSCV Type Reset RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 Bits Field Descriptions 15 0 PSCV Prescaler Value These bits are used to specify the prescaler value to generate the counter clock frequency fCK_CNT fC...

Page 278: ...load value Offset 0x088 Reset value 0x0000_FFFF 31 30 29 28 27 26 25 24 Reserved Type Reset 23 22 21 20 19 18 17 16 Reserved Type Reset 15 14 13 12 11 10 9 8 CRV Type Reset RW 1 RW 1 RW 1 RW 1 RW 1 RW 1 RW 1 RW 1 7 6 5 4 3 2 1 0 CRV Type Reset RW 1 RW 1 RW 1 RW 1 RW 1 RW 1 RW 1 RW 1 Bits Field Descriptions 15 0 CRV Counter Reload Value The CRV is the reload value which is loaded into the actual co...

Page 279: ...17 16 Reserved Type Reset 15 14 13 12 11 10 9 8 CH0CCV Type Reset RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 7 6 5 4 3 2 1 0 CH0CCV Type Reset RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 Bits Field Descriptions 15 0 CH0CCV Channel 0 Capture Compare Value When Channel 0 is configured as an output The CH0CCR value is compared with the counter value and the comparison result is used to trigger the CH0OREF o...

Page 280: ...17 16 Reserved Type Reset 15 14 13 12 11 10 9 8 CH1CCV Type Reset RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 7 6 5 4 3 2 1 0 CH1CCV Type Reset RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 Bits Field Descriptions 15 0 CH1CCV Channel 1 Capture Compare Value When Channel 1 is configured as an output The CH1CCR value is compared with the counter value and the comparison result is used to trigger the CH1OREF o...

Page 281: ...17 16 Reserved Type Reset 15 14 13 12 11 10 9 8 CH2CCV Type Reset RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 7 6 5 4 3 2 1 0 CH2CCV Type Reset RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 Bits Field Descriptions 15 0 CH2CCV Channel 2 Capture Compare Value When Channel 2 is configured as an output The CH2CCR value is compared with the counter value and the comparison result is used to trigger the CH2OREF o...

Page 282: ...17 16 Reserved Type Reset 15 14 13 12 11 10 9 8 CH3CCV Type Reset RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 7 6 5 4 3 2 1 0 CH3CCV Type Reset RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 Bits Field Descriptions 15 0 CH3CCV Channel 3 Capture Compare Value When Channel 3 is configured as an output The CH3CCR value is compared with the counter value and the comparison result is used to trigger the CH3OREF o...

Page 283: ...ic Compare Value When channel 0 is configured as asymmetric PWM mode and the counter is counting down the value written in this register will be compared to the counter Channel 1 Asymmetric Compare Register CH1ACR This register specifies the timer channel 1 asymmetric compare value Offset 0x0A4 Reset value 0x0000_0000 31 30 29 28 27 26 25 24 Reserved Type Reset 23 22 21 20 19 18 17 16 Reserved Typ...

Page 284: ...ic Compare Value When channel 2 is configured as asymmetric PWM mode and the counter is counting down the value written in this register will be compared to the counter Channel 3 Asymmetric Compare Register CH3ACR This register specifies the timer channel 3 asymmetric compare value Offset 0x0AC Reset value 0x0000_0000 31 30 29 28 27 26 25 24 Reserved Type Reset 23 22 21 20 19 18 17 16 Reserved Typ...

Page 285: ...Reload Register CRR DTG Dead Time Register DTG DTG Output Control Output Conf Registers Output Control Output Control Output Control MT_CH0O MT_CH0NO MT_CH1O MT_CH1NO MT_CH2O MT_CH2NO MT_CH3O MT_BRK Input Polarity Filter Clock Failure Event CMPx Note Transition EVent TI1 TI2 TI3 MT_BRK PSC PRESCALER Repetition Down Counter REPR Register Input Filter Polarity Selection Edge Detection Edge Detector ...

Page 286: ...lse Mode Output Complementary Outputs with programmable dead time insertion Repetition counter updates timer registers only after a given number of counter cycles Synchronization circuit to control the timer with external signals and can interconnect several timers together Interrupt PDMA generation on the following events PDMA is only available for the HT32F54243 HT32F54253 devices Update event 1...

Page 287: ...counter overflow event This action will continue repeatedly The counting direction bit DIR in the CNTCFR register should be cleared to 0 for the up counting mode When an update event 1 is generated by setting the UEV1G bit in the EVGR register to 1 the counter value will also be initialised to 0 CK_PSC CNT_EN F3 F4 F5 CK_CNT F2 F5 CNTR CRR Shadow Register CRR 36 F5 36 0 1 0 1 PSCR PSCR Shadow Regi...

Page 288: ...event This action will continue repeatedly The counting direction bit DIR in the CNTCFR register should be set to 1 for the down counting mode When an update event 1 is generated by setting the UEV1G bit in the EVGR register to 1 the counter value will also be initialised to the counter reload value CK_PSC CNT_EN 2 1 0 CK_CNT 3 F5 CNTR CRR Shadow Register CRR 36 F5 36 0 1 0 1 PSCR PSCR Shadow Regi...

Page 289: ...rection bit DIR in the CNTCFR register is read only and indicates the count direction when in the center aligned counting mode The count direction is updated by hardware automatically Setting the UEV1G bit in the EVGR register will initialise the counter value to 0 irrespective of whether the counter is counting up or down in the center aligned counting mode The update event 1 interrupt flag bit i...

Page 290: ...nditions occur At each counter overflow in the up counting mode At each counter underflow in the down counting mode At each counter overflow and underflow in the center aligned counting mode 1 2 3 4 5 0 1 2 3 4 5 0 1 2 3 4 0 1 2 1 0 3 2 1 0 3 2 1 0 3 2 1 0 3 3 2 Up Counting Down Counting Center Aligned Counting CK_CNT CNTR REPR UEV1 CNTR REPR UEV1 3 4 3 2 1 0 1 2 3 4 3 2 1 0 1 2 3 4 3 2 1 0 2 CNTR...

Page 291: ...ing the SMSEL field to 0x7 in the MDCFR register Here the counter will act as an event counter The input event known as STI here can be selected by setting the TRSEL field to an available value except the value of 0x0 When the STI signal is selected as the clock source the internal edge detection circuitry will generate a clock pulse during each STI signal rising edge to drive the counter prescale...

Page 292: ...to activate some MCTM functions which are triggered by a trigger signal rising edge Trigger Controller Block Edge Trigger Mux Level Trigger Mux Edge Detection ITI0 ITI1 ITI2 ITI0ED ITI1ED ITI2ED TI0S0ED TI1S1ED TRSEL 2 0 0 Edge Trigger Mux TI0BED ITI0ED ITI1ED ITI2ED STI TRSEL 2 0 TRSEL 3 0 1 0 S W Set UEV1G Bit TI0S0 TI1S1 ITI0 ITI1 ITI2 Level Trigger Source Internal ITIx Channel input TIn Softwa...

Page 293: ... occurs the update event 1 software generation bit named UEV1G will automatically be asserted by hardware and the trigger event flag TEVIF will also be set Then the counter and prescaler will be reinitialized Although the UEV1G bit is set to 1 by hardware whether the update event really occurs or not depends upon the update event 1 disable control bit UEV1DIS is set to 1 or not If the UEV1DIS bit ...

Page 294: ...g STI source signal polarity 0 STI source signal Sync polarity 1 Figure 82 MCTM in Pause Mode Trigger Mode After the counter is disabled to count the counter can resume counting when an STI rising edge signal occurs When an STI rising edge occurs the counter will start to count from the current value in the counter Note that if the STI signal is selected to be sourced from the UEV1G bit software t...

Page 295: ...trigger or drive another MCTM or GPTM if exists which should be configured in the Slave Mode MCTMn Master MTO ITI GPTMm Slave MMSEL SMSEL TSE TRSEL Figure 84 Master MCTMn and Slave GPTMm Connection The Master Mode Selection bits MMSEL in the MDCFR register are used to select the MTO source for synchronising another slave MCTM or GPTM if exists Channel 0 Capture Compare event MTO UEV1G bit Counter ...

Page 296: ... used in the input capture mode the counter value is captured into the CHxCCR shadow register first and then transferred into the CHxCCR preload register when the capture event occurs When used in the compare match output mode the contents of the CHxCCR preload register is copied into the associated shadow register the counter value is then compared with the register value CHxCCR Preload Register ...

Page 297: ...ure Compare Register CHxCCR when an effective input signal transition occurs Once the capture event occurs the CHxCCIF flag in the INTSR register is set accordingly If the CHxCCIF bit is already set i e the flag has not yet been cleared by software and another capture event on this channel occurs the corresponding channel Over Capture flag named CHxOCF will be set 25 26 27 28 29 30 31 32 33 34 35 ...

Page 298: ...olarity Configure the capture channel 1 CH1CCS 0x2 to select the TI0 signal as the capture input Set the CH1P bit to 1 to choose the falling edge of the TI0 input as the active polarity Setup the TRSEL bits to 0x1 to select TI0S0 as the trigger input Configure the Slave controller to operate in the Restart mode by setting the SMSEL field in the MDCFR register to 0x4 Enable the input capture mode b...

Page 299: ...hannel capture input source prescaler setting field CHxPSC Filter TI0FP TI0FN TI0F MT_CH0 fsampling CH0P Filter TI1FP TI1FN TI1F CH1P MT_CH1 TI0S0 TI1S0 TI0S1 TI1S1 TRCED CH0PRESCALER CH1PRESCALER TI0S0ED CH0PSC CH1PSC CH0CCS CH1CCS CH0PSC CH1PSC CH0CAP Event CH1CAP Event Edge Detection Edge Detection Edge Detection Edge Detection TI1S0ED TI0S1ED TI1S1ED MT_CH1 MT_CH2 TI0SRC TI0XOR Edge Detection ...

Page 300: ... clock controller block for the MT_CH0 MT_CH3 pins The digital filter in the MCTM is an N event counter where N refers to how many valid transitions are necessary to output a filtered signal The N value can be 0 2 4 5 6 or 8 according to the selection for each filter Digital Filter N 2 No Filtered J Q CK K Filtered TI0 fSYSTEM D Q CK D Q CK D Q CK fsampling Figure 91 TI0 Digital Filter Diagram wit...

Page 301: ...eforms according to the configuration values of corresponding control bits as shown by the dashed box in the diagram Output Mode Controller CNTR CHxCCR CHxOM CHxOREF DTG CHDTG 0 CHxO_DT CHxNO_DT CHxNE CHxE CHxP CHxNP Output Enable Controller Output Enable Controller CHxE CHxNE CHMOE CHMOE CHOSSI CHOSSR CHOSSI CHOSSR CHxOIS CHxOISN CHxO CHxNO x 0 2 Output Mode Controller CH3OM CH3P Output Enable Co...

Page 302: ...he count direction and the relationship between the counter value and the CHxCCR content There are also two modes which will force the output into an inactive or active state irrespective of the CHxCCR content or counter values With regard to a more detailed description refer to the relative bit definition The accompanying table shows a summary of the output type setup Table 35 Compare Match Outpu...

Page 303: ...oggle preload enable CHxCCR New value 3 Update CHxCCR value 1 2 3 TME CHxOREF UEV1 Update Event 1 Figure 94 Toggle Mode Channel Output Reference Signal CHxPRE 1 Counter Value CRR CHxCCR CHxOREF CHxOM 0x6 CHxCCIF CHxOREF Counter Value 100 0 CHxOM 0x7 CHxCCR CRR CHxOREF CHxCCIF CHxCCIF CHxOREF CHxCCR 0x0000 CRR Counter Value CHxOREF 0 CHxOREF 100 Figure 95 PWM Mode Channel Output Reference Signal an...

Page 304: ...xOREF 100 CRR CHxCCR Counter Value CHxOREF CHxCCIF CHxCCIF CHxOREF 0 Figure 96 PWM Mode Channel Output Reference Signal and Counter in Down counting Mode Up counting Down counting CRR 5 CHxCCR 3 CMSEL 0x1 CHxCCIF CHxCCR 4 CHxCCIF CHxCCR 5 CHxCCR 0 CHxCCIF CHxCCIF 100 0 0 1 2 3 4 5 4 3 2 1 0 1 Figure 97 PWM Mode 1 Channel Output Reference Signal and Counter in Centre Aligned Counting Mode ...

Page 305: ... a dead time relative to the reference signal rising edge The CHxNO is the opposite of the CHxOREF signal except for the rising edge which is delayed with a dead time relative to the reference signal falling edge CHxP 0 CHxNP 0 CHMOE 1 CHxE 1 CHxNE 1 CHxOREF Dead time CHxO CHxNO When dead time greater than negative pulse CHxO CHxNO Dead time Dead time CHxP 0 CHxNP 0 CHMOE 1 CHxE 1 CHxNE 1 CHxOREF ...

Page 306: ...l output will be forced to a reset state an inactive or idle state Moreover a break event can also be generated by the software asserting the BRKG bit in the EVGR register even if the break function is disabled The MT_BRK input signal can be enabled by setting the BKE bit in the CHBRKCTR register The break input polarity can be selected by setting the BKP bit in CHBRKCTR register The BKE and BKP b...

Page 307: ...it to 1 The channel output behavior is as described below If complementary outputs are used the channel outputs a level signal first which can be selected to be either a disable or inactive level selected by configuring the CHOSSI bit in the CHBRKCTR register After the dead time duration the outputs will be changed to the idle state The idle state is determined by the CHxOIS CHxOISN bits in the CH...

Page 308: ...tary output states when a break event occurs where the complementary outputs are enabled by setting both the CHxE and CHxNE bits to 1 CHMOE CHxOREF CHxO CHxNO Break event CHxO CHxNO CHxP 0 CHxOIS 0 CHxNP 0 CHxOISN 1 Dead time Dead time Dead time CHxP 0 CHxOIS 1 Dead time Dead time CHxNP 1 CHxOISN 1 Dead time Figure 102 Channel 0 2 Complementary Outputs with a Break Event Occurrence ...

Page 309: ...in the case of the output being enabled by setting the CHxE bit to 1 and the complementary output being disabled by clearing the CHxNE to 0 when a break event occurs CHMOE CHxOREF CHxO CHxNO Break event CHxO CHxNO CHxP 0 CHxOIS 0 CHxNP 0 CHxOISN 1 Dead time CHxP 0 CHxOIS 1 CHxNP 0 CHxOISN 0 Dead time Dead time 0 Figure 103 Channel 0 2 Only One Output Enabled when Break Event Occurs ...

Page 310: ... after a break event only the CHxO waveform is generated CHMOE CHxOREF CHxO CHxNO Break event CHxO CHxNO CHxP 0 CHxOIS 0 CHxNP 0 CHxOISN 0 CHxP 0 CHxOIS 1 CHxNP 0 CHxOISN 1 0 0 Figure 104 Hardware Protection When Both CHxO and CHxNO Are in Active Condition CHMOE can be set automatically by update event 1 if the automatic output enable function is enabled by setting the CHAOE bit in the CHBRKCTR re...

Page 311: ...d MT_CHxN not CHx_OREF xor CHxNP dead time MT_CHxN_OEN 0 1 0 0 Output disabled floating not driven by the timer MT_CHx floating MT_CHx_OEN 1 Output disabled floating not driven by the timer MT_CHxN floating MT_CHxN_OEN 1 1 0 1 Off State MT_CHx CHxP MT_CHx_OEN 0 Output enabled MT_CHxN CHx_OREF xor CHxNP MT_CHxN_OEN 0 1 1 0 Output enabled MT_CHx CHx_OCREF xor CHxP MT_CHx_OEN 0 Off State MT_CHxN CHxN...

Page 312: ...ted when a rising edge on the STI occurs or the corresponding software update event 2 generation bit UEV2G is set Update Event 1 The UEV1DIS bit in the CNTCFR register can determine whether an update event 1 occurs or not When the update event 1 occurs the corresponding update event interrupt will be generated depending upon whether the update event 1 interrupt generation function is enabled or no...

Page 313: ...pdate event 2 occurs COMPRE 1 CHOSSR 1 CHxP CHxNP 0 CHDTG 0 Update Event 2 CHxE CHxNE Shadow CHxE Shadow CHxNE CHxOM Shadow CHxOM CHxO CHxNO PWM1 PWM1 Forced Inactive Forced Inactive Forced Active Forced Active Figure 106 CHxE CHxNE and CHxOM Updated by Update Event 2 An update event 2 can be generated by setting the software update bit UEV2G in the EVGR register or by the rising edge of the STI s...

Page 314: ... then keep the TME bit at a high state until the update event 1 occurs or the TME bit is cleared to 0 by software If the TME bit is cleared to 0 using software the counter will be stopped and its value held If the TME bit is automatically cleared to 0 by a hardware update event 1 the counter will be reinitialised Triggered by S W Triggered by STI Cleared by Update Event Flag is set by compare matc...

Page 315: ...ach CHxOCFR register After an STI rising edge trigger occurs in the single pulse mode the CHxOREF signal will immediately be forced to the state to which the CHxOREF signal will change to as the compare match event occurs without taking the comparison result into account The CHxIMAE bit is available only when the output channel is configured to operate in the PWM mode 1 or PWM mode 2 and the trigg...

Page 316: ... in counting down stage then the value in the CHxACR register is used as the down count compare value The following figure is shown as an example for asymmetric PWM mode in Center aligned Counting mode Note Asymmetric PWM mode can only be operated in Center aligned Counting mode 2 3 4 5 6 7 0 1 8 5 4 3 2 1 0 7 6 2 3 4 5 6 7 1 8 5 4 3 2 1 0 7 6 2 3 4 5 6 7 1 8 5 4 3 2 1 7 6 CNTR CHxOREF CHxOREF CHx...

Page 317: ...ter and slave modes Using one timer to trigger another timer to start or stop counting Configure MCTM to be in the master mode and to send its channel 0 Output Reference signal CH0OREF as a trigger output MMSEL 0x4 Configure the MCTM CH0OREF waveform Configure the GPTM to receive its input trigger source from the MCTM trigger output TRSEL 0xA Configure GPTM to operate in the pause mode SMSEL 0x5 E...

Page 318: ... Update Event 1 UEV1 as the trigger output MMSEL 0x2 Configure the MCTM period by setting the CRR register Configure GPTM to get the input trigger source from the MCTM trigger output TRSEL 0xA Configure GPTM to be in the slave trigger mode SMSEL 0x6 Start MCTM by writing 1 to the TME bit 14 15 00 01 02 FB FC FA 03 13 fCLKIN MCTM CNTR GPTM CNTR Software clearing GPTM TME bit GPTM TEVIF FD MCTM UEV1...

Page 319: ...M to be in the slave trigger mode SMSEL 0x6 Enable the MCTM master timer synchronisation function by setting the TSE bit in the MDCFR register to 1 to synchronise the slave timer Configure GPTM to receive its input trigger source from the MCTM trigger output TRSEL 0xA Configure GPTM to be in the slave trigger mode SMSEL 0x6 TI0 TI0FP fDTS fCLKIN TI0S0ED MCTM TME bit MCTM TEVIF TSE 1 Delay MCTM CK_...

Page 320: ...SEL 0x0 Configure TI0BED to be connected to STI TRSEL 0x8 Configure the counter to be in the slave restart mode SMSEL 0x4 Enable GPTM TME 1 MCTM Select GPTM MTO to be the STI source of MCTM TRSEL 0xA Enable the CHxE CHxNE and CHxOM preload function COMPRE 1 Select the rising edge on STI to generate an update event 2 COMUS 1 Enable the update event 2 interrupt UEV2IE 1 In the update event 2 ISR wri...

Page 321: ...ged until an MCTM reset or system reset occurs Table 37 Lock Level Table Lock Configuration Protected Bits Lock Level 1 LOCKLV 01 CHDTG CHxOIS CHxOISN BKE BKP CHAOE Lock Level 2 LOCKLV 10 CHDTG CHxOIS CHxOISN BKE BKP CHAOE CHxP CHxNP CHOSSI CHOSSR MCTMEN 1 CKMEN 2 Lock Level 3 LOCKLV 11 CHDTG CHxOIS CHxOISN BKE BKP CHAOE CHxP CHxNP CHOSSI CHOSSR MCTMEN 1 CKMEN 2 CHxPRE CHxOM Notes 1 The MCTMEN bit...

Page 322: ... events When the PDMA request is generated from the MCTM channel it can be derived from the channel capture compare event or the MCTM update event 1 selected by the channel PDMA selection bit CHCCDS for all channels For more detailed PDMA configuring information refer to the corresponding section in the PDMA chapter UEV1_EV 0 1 CH0 PDMA Request UEV1_EV 0 1 CH1_EV UEV1_EV 0 1 CH2_EV UEV1_EV 0 1 CH3...

Page 323: ...Output Configuration Register 0x0000_0000 CH3OCFR 0x04C Channel 3 Output Configuration Register 0x0000_0000 CHCTR 0x050 Channel Control Register 0x0000_0000 CHPOLR 0x054 Channel Polarity Configuration Register 0x0000_0000 CHBRKCFR 0x06C Channel Break Configuration Register 0x0000_0000 CHBRKCTR 0x070 Channel Break Control Register 0x0000_0000 DICTR 0x074 Timer PDMA Interrupt Control Register 0x0000...

Page 324: ... mode 17 16 CMSEL Counter Mode Selection 00 Edge aligned counting mode Normal up counting and down counting available for this mode Counting direction is defined by the DIR bit 01 Center aligned counting mode 1 The counter counts up and down alternatively The compare match interrupt flag is set during the count down period 10 Center aligned counting mode 2 The counter counts up and down alternativ...

Page 325: ...generation through the slave mode 1 Disable the update event 1 however the counter and the prescaler are reinitialised if the UEV1G bit is set or if a hardware restart is received from the slave mode Timer Mode Configuration Register MDCFR This register specifies the MCTM master and slave mode selection and single pulse mode Offset 0x004 Reset value 0x0000_0000 31 30 29 28 27 26 25 24 Reserved SPM...

Page 326: ...e update event 1 is used as the trigger output according to one of the following cases when the UEV1DIS bit is cleared to 0 1 Counter overflow underflow 2 Software setting UEV1G 3 Slave has trigger input when used in slave restart mode 011 Capture Compare Mode When a Channel 0 capture or compare match event occurs it will generate a positive pulse which is used as the master trigger output 100 Com...

Page 327: ...also be updated 101 Pause Mode The counter starts to count when the selected trigger input STI is high The counter stops counting on the instant not being reset when the STI signal changes its state to a low level Both the counter start and stop control are determined by the STI signal 110 Trigger Mode The counter starts to count from the original value in the counter on the rising edge of the sel...

Page 328: ... 0 RW 0 RW 0 Bits Field Descriptions 3 0 TRSEL Trigger Source Selection These bits are used to select the trigger input STI for counter synchronization 0000 Software Trigger by setting the UEV1G bit 0001 Channel 0 filtered input TI0S0 0010 Channel 1 filtered input TI1S1 0011 Reserved 1000 Channel 0 Edge Detector TI0BED 1001 Internal Timer Trigger 0 ITI0 1010 Internal Timer Trigger 1 ITI1 1011 Inte...

Page 329: ...2G bit only 1 Updated by setting the UEV2G bit or when an STI signal rising edge occurs This bit is only available when the capture compare preload function is enabled by setting the COMPRE bit to 1 8 COMPRE Capture Compare Preloaded Enable Control 0 CHxE CHxNE and CHxOM bits are not preloaded 1 CHxE CHxNE and CHxOM bits are preloaded If this bit is set to 1 the corresponding capture compare contr...

Page 330: ...19 18 CH0PSC Channel 0 Capture Input Source Prescaler Setting These bits define the effective events of the channel 0 capture input Note that the prescaler is reset once the Channel 0 Capture Compare Enable bit CH0E in the Channel Control register named CHCTR is cleared to 0 00 No prescaler channel 0 capture input signal is chosen for each active event 01 Channel 0 Capture input signal is chosen f...

Page 331: ...ter where N is defined as how many valid transitions are necessary to output a filtered signal 0000 No filter the sampling clock is fSYSTEM 0001 fsampling fCLKIN N 2 0010 fsampling fCLKIN N 4 0011 fsampling fCLKIN N 8 0100 fsampling fDTS 2 N 6 0101 fsampling fDTS 2 N 8 0110 fsampling fDTS 4 N 6 0111 fsampling fDTS 4 N 8 1000 fsampling fDTS 8 N 6 1001 fsampling fDTS 8 N 8 1010 fsampling fDTS 16 N 5...

Page 332: ...nnel 1 capture input Note that the prescaler is reset once the Channel 1 Capture Compare Enable bit CH1E in the Channel Control register named CHCTR is cleared to 0 00 No prescaler channel 1 capture input signal is chosen for each active event 01 Channel 1 Capture input signal is chosen for every 2 events 10 Channel 1 Capture input signal is chosen for every 4 events 11 Channel 1 Capture input sig...

Page 333: ...er where N is defined as how many valid transitions are necessary to output a filtered signal 0000 No filter the sampling clock is fSYSTEM 0001 fsampling fCLKIN N 2 0010 fsampling fCLKIN N 4 0011 fsampling fCLKIN N 8 0100 fsampling fDTS 2 N 6 0101 fsampling fDTS 2 N 8 0110 fsampling fDTS 4 N 6 0111 fsampling fDTS 4 N 8 1000 fsampling fDTS 8 N 6 1001 fsampling fDTS 8 N 8 1010 fsampling fDTS 16 N 5 ...

Page 334: ...nnel 2 capture input Note that the prescaler is reset once the Channel 2 Capture Compare Enable bit CH2E in the Channel Control register named CHCTR is cleared to 0 00 No prescaler channel 2 capture input signal is chosen for each active event 01 Channel 2 Capture input signal is chosen for every 2 events 10 Channel 2 Capture input signal is chosen for every 4 events 11 Channel 2 Capture input sig...

Page 335: ...er where N is defined as how many valid transitions are necessary to output a filtered signal 0000 No filter the sampling clock is fSYSTEM 0001 fsampling fCLKIN N 2 0010 fsampling fCLKIN N 4 0011 fsampling fCLKIN N 8 0100 fsampling fDTS 2 N 6 0101 fsampling fDTS 2 N 8 0110 fsampling fDTS 4 N 6 0111 fsampling fDTS 4 N 8 1000 fsampling fDTS 8 N 6 1001 fsampling fDTS 8 N 8 1010 fsampling fDTS 16 N 5 ...

Page 336: ...nnel 3 capture input Note that the prescaler is reset once the Channel 3 Capture Compare Enable bit CH3E in the Channel Control register named CHCTR is cleared to 0 00 No prescaler channel 3 capture input signal is chosen for each active event 01 Channel 3 Capture input signal is chosen for every 2 events 10 Channel 3 Capture input signal is chosen for every 4 events 11 Channel 3 Capture input sig...

Page 337: ...er where N is defined as how many valid transitions are necessary to output a filtered signal 0000 No filter the sampling clock is fSYSTEM 0001 fsampling fCLKIN N 2 0010 fsampling fCLKIN N 4 0011 fsampling fCLKIN N 8 0100 fsampling fDTS 2 N 6 0101 fsampling fDTS 2 N 8 0110 fsampling fDTS 4 N 6 0111 fsampling fDTS 4 N 8 1000 fsampling fDTS 8 N 6 1001 fsampling fDTS 8 N 8 1010 fsampling fDTS 16 N 5 ...

Page 338: ...ingle pulse Immediate Active Mode is enabled The CH0OREF will be forced to the compare matched level immediately after an available trigger event occurs irrespective of the result of the comparison between the CNTR and the CH0CCR values The effective duration ends automatically at the next overflow or underflow event Note The CH0IMAE bit is available only if channel 0 is configured operate in PWM ...

Page 339: ... active level 0111 PWM mode 2 During up counting channel 0 has an inactive level when CNTR CH0CCR or otherwise has an active level During down counting channel 0 has an active level when CNTR CH0CCR or otherwise has an inactive level 1110 Asymmetric PWM mode 1 During up counting channel 0 has an active level when CNTR CH0CCR or otherwise has an inactive level During down counting channel 0 has an ...

Page 340: ...e pulse Immediate Active Mode is enabled The CH1OREF will be forced to the compare matched level immediately after an available trigger event occurs irrespective of the result of the comparison between the CNTR and the CH1CCR values The effective duration ends automatically at the next overflow or underflow event Note The CH1IMAE bit is available only if channel 1 is configured to be operated in P...

Page 341: ... active level 0111 PWM mode 2 During up counting channel 1 has an inactive level when CNTR CH1CCR or otherwise has an active level During down counting channel 1 has an active level when CNTR CH1CCR or otherwise has an inactive level 1110 Asymmetric PWM mode 1 During up counting channel 1 has an active level when CNTR CH1CCR or otherwise has an inactive level During down counting channel 1 has an ...

Page 342: ...pulse Immediate Active Mode is enabled The CH2OREF will be forced to the compare matched level immediately after an available trigger event occurs irrespective of the result of the comparison between the CNTR and the CH2CCR values The effective duration ends automatically at the next overflow or underflow event Note The CH2IMAE bit is available only if the channel 2 is configured to be operated in...

Page 343: ... active level 0111 PWM mode 2 During up counting channel 2 has an inactive level when CNTR CH2CCR or otherwise has an active level During down counting channel 2 has an active level when CNTR CH2CCR or otherwise has an inactive level 1110 Asymmetric PWM mode 1 During up counting channel 2 has an active level when CNTR CH2CCR or otherwise has an inactive level During down counting channel 2 has an ...

Page 344: ...e pulse Immediate Active Mode is enabled The CH3OREF will be forced to the compare matched level immediately after an available trigger event occurs irrespective of the result of the comparison between the CNTR and the CH3CCR values The effective duration ends automatically at the next overflow or underflow event Note The CH3IMAE bit is available only if channel 3 is configured to be operated in P...

Page 345: ... active level 0111 PWM mode 2 During up counting channel 3 has an inactive level when CNTR CH3CCR or otherwise has an active level During down counting channel 3 has an active level when CNTR CH3CCR or otherwise has an inactive level 1110 Asymmetric PWM mode 1 During up counting channel 3 has an active level when CNTR CH3CCR or otherwise has an inactive level During down counting channel 3 has an ...

Page 346: ...utput signal CH3O is generated on the corresponding output pin depending on the condition of the CHMOE CHOSSI CHOSSR and CH3OIS bits 5 CH2NE Channel 2 Capture Compare Complementary Enable 0 Off Channel 2 complementary output CH2NO is not active The CH2NO level is then determined by the CHMOE CHOSSI CHOSSR CH2OIS CH2OISN and CH2E bits 1 On Channel 2 complementary output CH2NO is generated on the co...

Page 347: ...N and CH1NE bits 1 On Channel 1 output signal CH1O is generated on the corresponding output pin depending on the condition of the CHMOE CHOSSI CHOSSR CH1OIS CH1OISN and CH1NE bits 1 CH0NE Channel 0 Capture Compare Complementary Enable 0 Off Channel 0 complementary output CH0NO is not active The CH0NO level is then determined by the condition of the CHMOE CHOSSI CHOSSR CH0OIS CH0OISN and CH0E bits ...

Page 348: ...high 1 Channel 3 Output is active low 5 CH2NP Channel 2 Capture Compare Complementary Polarity 0 Channel 2 Output is active high 1 Channel 2 Output is active low 4 CH2P Channel 2 Capture Compare Polarity When Channel 2 is configured as an input CH2CCS 0x1 0x2 0x3 0 Capture event occurs on a Channel 2 rising edge 1 Capture event occurs on a Channel 2 falling edge When Channel 2 is configured as an ...

Page 349: ...escriptions 6 CH3OIS MT_CH3O Output Idle State 0 Channel 3 output CH3O 0 when CHMOE 0 1 Channel 3 output CH3O 1 when CHMOE 0 5 CH2OISN MT_CH2NO Output Idle State 0 Channel 2 complementary output CH2NO 0 after a dead time when CHMOE 0 1 Channel 2 complementary output CH2NO 1 after a dead time when CHMOE 0 4 CH2OIS MT_CH2O Output Idle State 0 Channel 2 output CH2O 0 after a dead time when CHMOE 0 1 ...

Page 350: ... with tdtg 2 tDTS CHDTG 7 5 110 Channel Dead Time 32 CHDTG 4 0 tdtg with tdtg 8 tDTS CHDTG 7 5 111 Channel Dead Time 32 CHDTG 4 0 tdtg with tdtg 16 tDTS 21 CHOSSR Channel Off State CHxE CHxNE 0 Selection for Normal Run State CHMOE 1 0 When inactive MT_CHxO MT_CHxNO output is disable not driven by timer 1 When inactive MT_CHxO MT_CHxNO output is enabled with their inactive level 20 CHOSSI Channel O...

Page 351: ...pling fDTS 4 N 6 0111 fsampling fDTS 4 N 8 1000 fsampling fDTS 8 N 6 1001 fsampling fDTS 8 N 8 1010 fsampling fDTS 16 N 5 1011 fsampling fDTS 16 N 6 1100 fsampling fDTS 16 N 8 1101 fsampling fDTS 32 N 5 1110 fsampling fDTS 32 N 6 1111 fsampling fDTS 32 N 8 5 CHAOE Channel Automatic Output Enable 0 CHMOE can be set only by software 1 CHMOE can be set by software or automatically by an update event ...

Page 352: ...est is disabled 1 Update event 2 PDMA request is enabled 24 UEV1DE Update event 1 PDMA Request Enable 0 Update event 1 PDMA request is disabled 1 Update event 1 PDMA request is enabled 19 CH3CCDE Channel 3 Capture Compare PDMA Request Enable 0 Channel 3 PDMA request is disabled 1 Channel 3 PDMA request is enabled 18 CH2CCDE Channel 2 Capture Compare PDMA Request Enable 0 Channel 2 PDMA request is ...

Page 353: ... CH3CCIE Channel 3 Capture Compare Interrupt Enable 0 Channel 3 interrupt is disabled 1 Channel 3 interrupt is enabled 2 CH2CCIE Channel 2 Capture Compare Interrupt Enable 0 Channel 2 interrupt is disabled 1 Channel 2 interrupt is enabled 1 CH1CCIE Channel 1 Capture Compare Interrupt Enable 0 Channel 1 interrupt is disabled 1 Channel 1 interrupt is enabled 0 CH0CCIE Channel 0 Capture Compare Inter...

Page 354: ...The BRKIF flag is set and then the CHMOE bit will be cleared 10 TEVG Trigger Event Generation The trigger event TEV can be generated by setting this bit It is cleared by hardware automatically 0 No action 1 The TEVIF flag is set 9 UEV2G Update Event 2 Generation The update event 2 UEV2 can be generated by setting this bit It is cleared by hardware automatically 0 No action 1 Update the CHxE CHxNE ...

Page 355: ...l 2 is configured as an input the counter value is captured into the CH2CCR register and then the CH2CCIF bit is set If Channel 2 is configured as an output the CH2CCIF bit is set 1 CH1CCG Channel 1 Capture Compare Generation A Channel 1 capture compare event can be generated by setting this bit It is cleared by hardware automatically 0 No action 1 Capture compare event is generated on channel 1 I...

Page 356: ...curs 10 TEVIF Trigger Event Interrupt Flag This flag is set by hardware when a trigger event occurs and is cleared by software 0 No trigger event occurs 1 Trigger event occurs 9 UEV2IF Update Event 2 Interrupt Flag This bit is set by hardware when an update event 2 occurs and is cleared by software 0 No update event 2 occurs 1 Update event 2 occurs 8 UEV1IF Update Event 1 Interrupt Flag This bit i...

Page 357: ... center aligned counting mode It is cleared by software Channel 3 is configured as an input 0 No input capture occurs 1 Input capture occurs This bit is set by hardware when a capture event occurs It is cleared by software or by reading the CH3CCR register 2 CH2CCIF Channel 2 Capture Compare Interrupt Flag Channel 2 is configured as an output 0 No match event occurs 1 The contents of the counter C...

Page 358: ... the center aligned counting mode It is cleared by software Channel 0 is configured as an input 0 No input capture occurs 1 Input capture occurs This bit is set by hardware on a capture event It is cleared by software or by reading the CH0CCR register Timer Counter Register CNTR This register stores the timer counter value Offset 0x080 Reset value 0x0000_0000 31 30 29 28 27 26 25 24 Reserved Type ...

Page 359: ...0_0000 31 30 29 28 27 26 25 24 Reserved Type Reset 23 22 21 20 19 18 17 16 Reserved Type Reset 15 14 13 12 11 10 9 8 PSCV Type Reset RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 7 6 5 4 3 2 1 0 PSCV Type Reset RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 Bits Field Descriptions 15 0 PSCV Prescaler Value These bits are used to specify the prescaler value to generate the counter clock frequency fCK_CNT fCK_CN...

Page 360: ...Type Reset RW 1 RW 1 RW 1 RW 1 RW 1 RW 1 RW 1 RW 1 Bits Field Descriptions 15 0 CRV Counter Reload Value The CRV is the reload value which is loaded into the actual counter register Timer Repetition Register REPR This register specifies the timer repetition counter value Offset 0x08C Reset value 0x0000_0000 31 30 29 28 27 26 25 24 Reserved Type Reset 23 22 21 20 19 18 17 16 Reserved Type Reset 15 ...

Page 361: ...criptions 15 0 CH0CCV Channel 0 Capture Compare Value When Channel 0 is configured as an output The CH0CCR value is compared with the counter value and the comparison result is used to trigger the CH0OREF output signal When Channel 0 is configured as an input The CH0CCR register stores the counter value captured by the last channel 0 capture event Channel 1 Capture Compare Register CH1CCR This reg...

Page 362: ...Register CH2CCR This register specifies the timer channel 2 capture compare value Offset 0x098 Reset value 0x0000_0000 31 30 29 28 27 26 25 24 Reserved Type Reset 23 22 21 20 19 18 17 16 Reserved Type Reset 15 14 13 12 11 10 9 8 CH2CCV Type Reset RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 7 6 5 4 3 2 1 0 CH2CCV Type Reset RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 Bits Field Descriptions 15 0 CH2CCV Cha...

Page 363: ...7 16 Reserved Type Reset 15 14 13 12 11 10 9 8 CH3CCV Type Reset RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 7 6 5 4 3 2 1 0 CH3CCV Type Reset RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 Bits Field Descriptions 15 0 CH3CCV Channel 3 Capture Compare Value When Channel 3 is configured as an output The CH3CCR value is compared with the counter value and the comparison result is used to trigger the CH3OREF ou...

Page 364: ...Compare Value When channel 0 is configured as asymmetric PWM mode and the counter is counting down the value written into this register will be compared to the counter Channel 1 Asymmetric Compare Register CH1ACR This register specifies the timer channel 1 asymmetric compare value Offset 0x0A4 Reset value 0x0000_0000 31 30 29 28 27 26 25 24 Reserved Type Reset 23 22 21 20 19 18 17 16 Reserved Type...

Page 365: ...Compare Value When channel 2 is configured as asymmetric PWM mode and the counter is counting down the value written into this register will be compared to the counter Channel 3 Asymmetric Compare Register CH3ACR This register specifies the timer channel 3 asymmetric compare value Offset 0x0AC Reset value 0x0000_0000 31 30 29 28 27 26 25 24 Reserved Type Reset 23 22 21 20 19 18 17 16 Reserved Type...

Page 366: ...y of purposes including general timer input signal pulse width measurement or output waveform generation such as PWM output Trigger Controller TI SCTM_CH Input Filter Polarity Selection Edge Detection CH PRESCALER TM_CNT Channel Capture Compare Register CHCCR Reload Register CRR Output Control SCTM_CHO PSC PRESCALER TISED TIBED STIED TIBED TIS Clock Controller fCLKIN CK_CNT CK_PSC Slave Controller...

Page 367: ...t capture event Output compare match event Functional Descriptions Counter Mode Up Counting The counter counts continuously from 0 to the counter reload value which is defined in the CRR register then restarts from 0 and generates a counter overflow event This action will continue repeatedly When the update event is generated by setting the UEVG bit in the EVGR register to 1 the counter value will...

Page 368: ...ribed as follows STIED The counter prescaler can count during each rising edge of the STI signal This mode can be selected by setting the SMSEL field to 0x7 in the MDCFR register Here the counter will act as an event counter The input event known as STI here can be selected by setting the TRSEL field to an available value except the value of 0x0 When the STI signal is selected as the clock source ...

Page 369: ...ection circuitry will generate a clock pulse at each trigger signal rising edge to stimulate some SCTM functions which are triggered by a trigger signal rising edge STIED TISED TRSEL 2 0 TRSEL 3 0 1 0 Edge Trigger Mux TIBED STI TRSEL 2 0 TRSEL 3 0 1 0 S W Set UEVG Bit TIS Level Trigger Source Channel input Software UEVG bit STIED_S0 STIED_S1 STI_S0 STI_S1 Reserved 000 001 010 011 others 000 001 01...

Page 370: ...n an STI rising edge occurs the update event software generation bit named UEVG will automatically be asserted by hardware and the trigger event flag will also be set Then the counter and prescaler will be reinitialized Although the UEVG bit is set to 1 by hardware the update event does not really occur It depends upon whether the update event disable control bit UEVDIS is set to 1 or not If the U...

Page 371: ...gnal polarity 0 STI source signal Sync polarity 1 Figure 122 SCTM in Pause Mode Trigger Mode After the counter is disabled to count the counter can resume counting when an STI rising edge signal occurs When an STI rising edge occurs the counter will start to count from the current value in the counter Note that if the STI signal is selected to be derived from the UEVG bit software trigger the coun...

Page 372: ...in the input capture mode the counter value is captured into the CHCCR shadow register first and then transferred into the CHCCR preload register when the capture event occurs When used in the compare match output mode the contents of the CHCCR preload register is copied into the associated shadow register the counter value is then compared with the register value CHCCR Preload Register CHCCR Shad...

Page 373: ...ture Compare Register CHCCR when an effective input signal transition occurs Once the capture event occurs the CHCCIF flag in the INTSR register is set accordingly If the CHCCIF bit is already set i e the flag has not yet been cleared by software and another capture event on this channel occurs the corresponding channel Over Capture flag named CHOCF will be set 25 26 27 28 29 30 31 32 33 34 35 0 2...

Page 374: ...n be set by the channel capture input source prescaler setting field CHPSC Filter TIFP TIFN TIF SCTM_CH fsampling CHP TIS CH PRESCALER TISED CHPSC CHCCS CHPSC CHCAP Event Edge Detection fCLKIN Edge Detection Edge Detection TIBED fCLKIN TI Figure 126 Channel Input Stages Digital Filter The digital filter is embedded in the channel input stage The digital filter in the SCTM is an N event counter whe...

Page 375: ...has several types of output function which defines what happens to the output when the counter value matches the contents of the CHCCR register In addition to the low high and toggle CHOREF output types there are also PWM mode 1 and PWM mode 2 outputs In these modes the CHOREF signal level is changed according to the relationship between the counter value and the CHCCR content There are also two m...

Page 376: ...TME CHOREF UEV Update Event Time Output toggle preload disable CHCCR New value 3 Update CHCCR value 1 2 3 Figure 129 Toggle Mode Channel Output Reference Signal CHPRE 0 Counter Value CRR CHOM 0x3 CHPRE 1 CHCCR CHCCR New value 1 CHCCR New value 2 Time Output toggle preload enable CHCCR New value 3 Update CHCCR value 1 2 3 TME CHOREF UEV Update Event Figure 130 Toggle Mode Channel Output Reference S...

Page 377: ...m the actual registers to the corresponding shadow registers An update event will occur when the counter overflows the software update control bit is triggered or an update event from the slave controller is generated The UEVDIS bit in the CNTCFR register can determine whether the update event occurs or not When the update event occurs the corresponding update event interrupt will be generated dep...

Page 378: ...0x0000_0000 MDCFR 0x004 Timer Mode Configuration Register 0x0000_0000 TRCFR 0x008 Timer Trigger Configuration Register 0x0000_0000 CTR 0x010 Timer Control Register 0x0000_0000 CHICFR 0x020 Channel Input Configuration Register 0x0000_0000 CHOCFR 0x040 Channel Output Configuration Register 0x0000_0000 CHCTR 0x050 Channel Control Register 0x0000_0000 CHPOLR 0x054 Channel Polarity Configuration Regist...

Page 379: ...io between the timer clock fCLKIN and the dead time clock fDTS The dead time clock is also used for digital filter sampling clock 00 fDTS fCLKIN 01 fDTS fCLKIN 2 10 fDTS fCLKIN 4 11 Reserved 1 UGDIS Update event interrupt generation disable control 0 Any of the following events will generate an update interrupt Counter overflow Setting the UEVG bit Update generation through the slave mode 1 Only c...

Page 380: ...de The prescaler is clocked directly by the internal clock 100 Restart Mode The counter value restarts from 0 on the rising edge of the STI signal The registers will also be updated 101 Pause Mode The counter starts to count when the selected trigger input STI is high The counter stops counting on the instant not being reset when the STI signal changes its state to a low level Both the counter sta...

Page 381: ...8 17 16 Reserved Type Reset 15 14 13 12 11 10 9 8 Reserved Type Reset 7 6 5 4 3 2 1 0 Reserved TRSEL Type Reset RW 0 RW 0 RW 0 RW 0 Bits Field Descriptions 3 0 TRSEL Trigger Source Selection These bits are used to select the trigger input STI for counter synchronization 0000 Software Trigger by setting the UEVG bit 0001 Filtered input of the channel TIS 1000 Channel both edge detector TIBED Others...

Page 382: ...ype Reset 7 6 5 4 3 2 1 0 Reserved CRBE TME Type Reset RW 0 RW 0 Bits Field Descriptions 1 CRBE Counter Reload register Buffer Enable 0 Counter Reload register can be updated immediately 1 Counter Reload register cannot be updated until the update event occurs 0 TME Timer Enable bit 0 SCTM off 1 SCTM on SCTM functions normally When the TME bit is cleared to 0 the counter is stopped and the SCTM co...

Page 383: ...ing These bits define the effective events of the channel capture input Note that the prescaler is reset once the Channel Capture Compare Enable bit CHE in the Channel Control register named CHCTR is cleared to 0 00 No prescaler channel capture input signal is chosen for each active event 01 Channel Capture input signal is chosen for every 2 events 10 Channel Capture input signal is chosen for eve...

Page 384: ...r where N is defined as how many valid transitions are necessary to output a filtered signal 0000 No filter the sampling clock is fSYSTEM 0001 fsampling fCLKIN N 2 0010 fsampling fCLKIN N 4 0011 fsampling fCLKIN N 8 0100 fsampling fDTS 2 N 6 0101 fsampling fDTS 2 N 8 0110 fsampling fDTS 4 N 6 0111 fsampling fDTS 4 N 8 1000 fsampling fDTS 8 N 6 1001 fsampling fDTS 8 N 8 1010 fsampling fDTS 16 N 5 1...

Page 385: ...d The CHCCR register can be immediately assigned a new value when the CHPRE bit is cleared to 0 and the updated CHCCR value is used immediately 1 CHCCR preload function is enabled The new CHCCR value will not be transferred to its shadow register until the update event occurs 2 0 CHOM Channel Output Mode Setting These bits define the functional types of the output reference signal CHOREF 000 No Ch...

Page 386: ...9 28 27 26 25 24 Reserved Type Reset 23 22 21 20 19 18 17 16 Reserved Type Reset 15 14 13 12 11 10 9 8 Reserved Type Reset 7 6 5 4 3 2 1 0 Reserved CHE Type Reset RW 0 Bits Field Descriptions 0 CHE Channel Capture Compare Enable Channel is configured as an input CHCCS 0x1 0x3 0 Input Capture Mode is disabled 1 Input Capture Mode is enabled Channel is configured as an output CHCCS 0x0 0 Off Channel...

Page 387: ...0 31 30 29 28 27 26 25 24 Reserved Type Reset 23 22 21 20 19 18 17 16 Reserved Type Reset 15 14 13 12 11 10 9 8 Reserved Type Reset 7 6 5 4 3 2 1 0 Reserved CHP Type Reset RW 0 Bits Field Descriptions 0 CHP Channel Capture Compare Polarity When Channel is configured as an input CHCCS 0x1 0x3 0 Capture event occurs on a Channel rising edge 1 Capture event occurs on a Channel falling edge When Chann...

Page 388: ...2 21 20 19 18 17 16 Reserved Type Reset 15 14 13 12 11 10 9 8 Reserved TEVIE Reserved UEVIE Type Reset RW 0 RW 0 7 6 5 4 3 2 1 0 Reserved CHCCIE Type Reset RW 0 Bits Field Descriptions 10 TEVIE Trigger event Interrupt Enable 0 Trigger event interrupt is disabled 1 Trigger event interrupt is enabled 8 UEVIE Update event Interrupt Enable 0 Update event interrupt is disabled 1 Update event interrupt ...

Page 389: ...hardware automatically 0 No action 1 TEVIF flag is set 8 UEVG Update Event Generation The update event UEV can be generated by setting this bit It is cleared by hardware automatically 0 No action 1 Reinitialize the counter If this bit is set the counter value returns to 0 An update operation of any related registers will also be performed For more detail descriptions refer to the corresponding sec...

Page 390: ...event and is cleared by software 0 No update event occurs 1 Update event occurs Note The update event is derived from the following conditions The counter overflows The UEVG bit is asserted A restart trigger event occurs from the slave trigger input 4 CHOCF Channel Over Capture Flag This flag is set by hardware and cleared by software 0 No over capture event is detected 1 Capture event occurs agai...

Page 391: ... 0 RW 0 RW 0 Bits Field Descriptions 15 0 CNTV Counter Value Timer Prescaler Register PSCR This register specifies the timer prescaler value to generate the counter clock Offset 0x084 Reset value 0x0000_0000 31 30 29 28 27 26 25 24 Reserved Type Reset 23 22 21 20 19 18 17 16 Reserved Type Reset 15 14 13 12 11 10 9 8 PSCV Type Reset RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 7 6 5 4 3 2 1 0 PSCV Type ...

Page 392: ...load value Offset 0x088 Reset value 0x0000_FFFF 31 30 29 28 27 26 25 24 Reserved Type Reset 23 22 21 20 19 18 17 16 Reserved Type Reset 15 14 13 12 11 10 9 8 CRV Type Reset RW 1 RW 1 RW 1 RW 1 RW 1 RW 1 RW 1 RW 1 7 6 5 4 3 2 1 0 CRV Type Reset RW 1 RW 1 RW 1 RW 1 RW 1 RW 1 RW 1 RW 1 Bits Field Descriptions 15 0 CRV Counter Reload Value The CRV is the reload value which is loaded into the actual co...

Page 393: ... 18 17 16 Reserved Type Reset 15 14 13 12 11 10 9 8 CHCCV Type Reset RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 7 6 5 4 3 2 1 0 CHCCV Type Reset RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 Bits Field Descriptions 15 0 CHCCV Channel Capture Compare Value When Channel is configured as an output The CHCCR value is compared with the counter value and the comparison result is used to trigger the CHOREF output...

Page 394: ...pare match event which is generated by the internal comparator The BFTM also supports a one shot mode which will force the counter to stop counting when a compare match event occurs BFTMCMPR Comparator BFTMCNTR 32 bit Up Counter Counter Controller BFTM APB clock EN CLR MIEN MIF To NVIC OSM To A D Converter Figure 133 BFTM Block Diagram Features 32 bit up counting counter Compare Match function Inc...

Page 395: ... pre defined by the BFTMCMPR register When the BFTM operates in the repetitive mode and the counter reaches a value equal to the specific compare value in the BFTMCMPR register the timer will generate a compare match event signal MIF When this occurs the counter will be reset to 0 and resume its counting operation When the MIF signal is generated a BFTM compare match interrupt will also be generat...

Page 396: ... counter value will be reset to 0 and stop counting when the CEN bit is cleared automatically to 0 by the internal hardware when a counter compare match event occurs CMP CNT MIF CEN Time CNT value unchanged when CEN is reset By S W Cleared by hardware Cleared by software Updated by software Figure 135 BFTM One Shot Mode CMP CNT MIF CEN Time 0xFFFF_FFFF Cleared by hardware Cleared by software Updat...

Page 397: ...ved Type Reset 15 14 13 12 11 10 9 8 Reserved Type Reset 7 6 5 4 3 2 1 0 Reserved CEN OSM MIEN Type Reset RW 0 RW 0 RW 0 Bits Field Descriptions 2 CEN BFTM Counter Enable Control 0 BFTM is disabled 1 BFTM is enabled When this bit is set to 1 the BFTM counter will start to count The counter will stop counting and the counter value will remain unchanged when the CEN bit is cleared to 0 by the applic...

Page 398: ... Type Reset 23 22 21 20 19 18 17 16 Reserved Type Reset 15 14 13 12 11 10 9 8 Reserved Type Reset 7 6 5 4 3 2 1 0 Reserved MIF Type Reset W0C 0 Bits Field Descriptions 0 MIF BFTM Compare Match Interrupt Flag 0 No compare match event occurs 1 Compare match event occurs When the counter value CNT is equal to the compare register value CMP a compare match event will occur and the corresponding interr...

Page 399: ... RW 0 RW 0 RW 0 Bits Field Descriptions 31 0 CNT BFTM Counter Value A 32 bit BFTM counter value is stored in this field which can be read or written on the fly BFTM Compare Value Register BFTMCMPR The register specifies the BFTM compare value Offset 0x00C Reset value 0xFFFF_FFFF 31 30 29 28 27 26 25 24 CMP Type Reset RW 1 RW 1 RW 1 RW 1 RW 1 RW 1 RW 1 RW 1 23 22 21 20 19 18 17 16 CMP Type Reset RW...

Page 400: ...escribed in the following sections Prescaler 24 bit Counter Compare Register CSECFLAG OVFLAG CMFLAG CSECIEN OVIEN CMIEN CSECWEN OVWEN CMWEN RTCSRC CK_RTC CK_SECOND RTCINT RTCWAKEUP CK_LSE CK_LSI APB Bus Match 24 24 set set set CMPCLR LSE OSC 1 0 LSI RC OSC VDD Power Domain To NVIC To EXTI and PWRCU VCORE Power Domain APB Interface and Level Shift Figure 137 RTC Block Diagram Features 24 bit up cou...

Page 401: ...LSI oscillator by setting the RTCSRC bit in the RTCCR register A prescaler is provided to divide the CK_RTC by a ratio ranged from 20 to 215 determined by the RPRE 3 0 field For instance setting the prescaler value RPRE 3 0 to 0xF will generate an exact 1 Hz CK_SECOND clock if the CK_RTC clock frequency is equal to 32 768 Hz The LSE oscillator can be enabled by the LSEEN control bit in the RTCCR r...

Page 402: ...content is set to a decimal value of 60 and the CMPCLR bit is set to 1 then the CMFLAG bit will be set every minute In addition the OVFLAG bit in the RTCSR register will be set when the RTC counter overflows A read operation on the RTCSR register clears the status flags including the CSECFLAG CMFLAG and OVFLAG bits Interrupt and Wakeup Control The falling edge of the CK_SECOND clock causes the CSE...

Page 403: ...t Waveform 0 Pulse mode 0 Compare match RTCCMP 4 RTCCNT 3 4 5 TR RTCOUT ROAP 0 RTCOUT ROAP 1 ROLF 1 Second clock RTCCMP X RTCCNT 3 4 5 TR TR TR RTCOUT ROAP 0 RTCOUT ROAP 1 ROLF 1 Level mode 0 Compare match RTCCMP 4 RTCCNT 3 4 5 RTCOUT ROAP 0 RTCOUT ROAP 1 ROLF 1 Second clock RTCCMP X RTCCNT 3 4 5 RTCOUT ROAP 0 RTCOUT ROAP 1 ROLF TR RTCOUT output pulse time 1 fCK_RTC Cleared by software reading ROL...

Page 404: ...efines a 24 bit up counter which is increased by the CK_SECOND clock Address 0x000 Reset value 0x0000_0000 31 30 29 28 27 26 25 24 Reserved Type Reset 23 22 21 20 19 18 17 16 RTCCNTV Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 RTCCNTV Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 7 6 5 4 3 2 1 0 RTCCNTV Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 Bits Field...

Page 405: ...CMPV Type Reset RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 Bits Field Descriptions 23 0 RTCCMPV RTC Compare Match Value A match condition happens when the value in the RTCCNT register is equal to the RTCCMP value An interrupt can be generated if the CMIEN bit in the RTCIWEN register is set When the CMPCLR bit in the RTCCR register is set to 0 and a match condition happens the CMFLAG bit in the RTCSR ...

Page 406: ... level after software has read this bit 19 ROAP RTCOUT Output Active Polarity 0 Active level is high 1 Active level is low 18 ROWM RTCOUT Output Waveform Mode 0 Pulse mode The output pulse duration is one RTC clock CK_RTC period 1 Level mode The RTCOUT signal will remain at an active level until the ROLF bit is cleared by software reading the ROLF bit 17 ROES RTCOUT Output Event Selection 0 RTC co...

Page 407: ...up and requires less operating power 1 Fast startup but requires higher operating current 4 CMPCLR Compare Match Counter Clear 0 24 bit RTC counter is not affected when compare match condition occurs 1 24 bit RTC counter is cleared when compare match condition occurs 3 LSEEN LSE oscillator Enable Control 0 LSE oscillator is disabled 1 LSE oscillator is enabled 1 RTCSRC RTC Clock Source Selection 0...

Page 408: ...d in the RTC IRQ handler and should be taken care when software polling is used 1 CMFLAG Compare Match Condition Flag 0 Compare match condition has not occurred since the last RTCSR register read operation 1 Compare match condition has occurred since the last RTCSR register read operation This bit is set by hardware on the CK_SECOND clock falling edge when the RTCCNT register value is equal to the...

Page 409: ...0 OVWEN Counter Overflow Wakeup Enable 0 Counter overflow wakeup is disabled 1 Counter overflow wakeup is enabled 9 CMWEN Compare Match Wakeup Enable 0 Compare match wakeup is disabled 1 Compare match wakeup is enabled 8 CSECWEN Counter Clock CK_SECOND Wakeup Enable 0 Counter Clock CK_SECOND wakeup is disabled 1 Counter Clock CK_SECOND wakeup is enabled 2 OVIEN Counter Overflow Interrupt Enable 0 ...

Page 410: ... if the software reloads the counter before it reaches a delta value That means that the Watchdog Timer prevents a software deadlock that continuously triggers the Watchdog the reload must occur when the Watchdog Timer value has a value within a limited window of 0 and WDTD The Watchdog Timer counter can be stopped when the processor is in the debug or the three sleep modes The register write prot...

Page 411: ...otection function before accessing any configuration register A read operation on PROTECT 0 can obtain the enable disable status of the register write protection function During normal operation the Watchdog Timer counter should be reloaded before it underflows to prevent the generation of a Watchdog reset The 12 bit count down counter can be reloaded with the required Watchdog Timer Counter Value...

Page 412: ...er counter will either continue to count or stop depending on the DBWDT bit of the MCUDBGCR register in the Clock Control Unit The Watchdog timer should be used in the following manners Set the Watchdog Timer reload value WDTV and reset in the WDTMR0 register Set the Watchdog Timer delta value WDTD and prescaler in the WDTMR1 register Start the Watchdog Timer by writing to the WDTCR register with ...

Page 413: ...g Timer Control Register WDTCR This register is used to reload the Watchdog timer Offset 0x000 Reset value 0x0000_0000 31 30 29 28 27 26 25 24 RSKEY Type Reset WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 23 22 21 20 19 18 17 16 RSKEY Type Reset WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 15 14 13 12 11 10 9 8 Reserved Type Reset 7 6 5 4 3 2 1 0 Reserved WDTRS Type Reset WO 0 Bits Field Descriptions 31 16 ...

Page 414: ...the WDTV value and count down 15 14 WDTSHLT Watchdog Timer Sleep Halt 00 The Watchdog runs when the system is in the Sleep mode or Deep Sleep1 mode 01 The Watchdog runs when the system is in the Sleep mode and halts in Deep Sleep1 mode 10 or 11 The Watchdog halts when the system is in the Sleep mode and Deep Sleep1 mode Note that the Watchdog timer always halts when the system is in the Deep Sleep...

Page 415: ...1 0 WDTD Type Reset RW 1 RW 1 RW 1 RW 1 RW 1 RW 1 RW 1 RW 1 Bits Field Descriptions 14 12 WPSC Watchdog Timer Prescaler Selection 000 1 1 001 1 2 010 1 4 011 1 8 100 1 16 101 1 32 110 1 64 111 1 128 11 0 WDTD Watchdog Timer Delta Value Define the permitted range to reload the Watchdog Timer If the Watchdog Timer counter value is less than or equal to WDTD writing to the WDTCR register with WDTRS 1...

Page 416: ... Type Reset WC 0 WC 0 Bits Field Descriptions 1 WDTERR Watchdog Timer Error 0 No Watchdog Timer error has occurred since the last read of this register 1 A Watchdog Timer error has occurred since the last read of this register Note A reload operation when the Watchdog Timer counter value is larger than WDTD causes a Watchdog Timer error Note that this bit is a write one clear flag 0 WDTUF Watchdog...

Page 417: ... RW 0 RW 0 Bits Field Descriptions 15 0 PROTECT Watchdog Timer Register Protection For write operation 0x35CA Disable the Watchdog Timer register write protection Others Enable the Watchdog Timer register write protection For read operation 0x0000 Watchdog Timer register write protection is disabled 0x0001 Watchdog Timer register write protection is enabled This register is used to enable disable ...

Page 418: ... Bits Field Descriptions 4 WDTLOCK Watchdog Timer Lock Mode 0 This bit is only cleared to 0 on any reset it cannot be cleared by software 1 This bit is set once only by software and locks the Watchdog Timer function Software can set this bit to 1 at any time Once the WDTLOCK bit is set the function and registers of the Watchdog Timer cannot be modified or disabled including the Watchdog Timer cloc...

Page 419: ...CL period generation registers are used to set different kinds of duty cycle implementation for the SCL pulse The SDA line which is connected to the whole I2 C bus is a bidirectional data line between the master and slave devices used for the transmission and reception of data The I2 C module also has an arbitration detection function to prevent the situation where more than one master attempts to...

Page 420: ...face The I2 C module has two external lines the serial data SDA and serial clock SCL lines to carry information between the interconnected devices connected to the bus The SCL and SDA lines are both bidirectional and must be connected to a pull high resistor When the I2 C bus is in the free or idle state both pins are at a high level to perform the required wired AND function for multiple connecte...

Page 421: ...he address frame is sent just after the START signal by the master device The addressing mode selection bit named ADRM in the I2CCR register should be defined to choose either the 7 bit or 10 bit addressing mode 7 bit Address Format The 7 bit address format is composed of the 7 bit length slave address which the master device wants to communicate with a R W bit and an ACK bit The R W bit defines t...

Page 422: ...bout ten times For the 10 bit addressing mode the first two bytes after a START signal include a header byte and an address byte that usually determines which slave will be selected by the master The header byte is composed of a leading 11110 the 10th and 9th bits of the slave address The second byte is the remaining 8 bits of the slave device address S 1 W S START condition W Write command Ack Ac...

Page 423: ...aster device sends a Not Acknowledge NACK signal to the slave device the slave device should release the SDA line for the master device to generate a STOP signal to terminate the transfer 1 2 8 9 SCL from Master Data output by Transmitter Data output by Receiver Acknowledge bit Data Frame Not acknowledge acknowledge Figure 146 I2 C Bus Acknowledge Clock Synchronization Only one master device can g...

Page 424: ...DA line Device 1 loses arbitration 1 1 1 0 0 0 1 0 0 1 1 1 1 Figure 148 Two Masters Arbitration Procedure General Call Addressing The general call addressing function can be used to address all the devices connected to the I2 C bus The master device can activate the general call function by writing a value 0x00 into the TAR field and clearing the RWD bit to 0 in the I2CTAR register on the addressi...

Page 425: ...2 C device is not addressed Operation Mode The I2 C module can operate in the following modes Master Transmitter Master Receiver Slave Transmitter Slave Receiver The I2 C module operates in the slave mode by default The interface will switch to the master mode automatically after generating a START signal Master Transmitter Mode Start Condition Users write the target slave device address and commu...

Page 426: ...TA flag is cleared by reading the I2CSR register Address Frame In the 7 bit addressing mode The ADRS flag is set after the address frame is sent by the master device and the acknowledge signal from the address matched slave device is received In order to receive the following data frame the ADRS bit must be cleared to 0 if it has been set to 1 The ADRS bit is cleared after reading the I2CSR regist...

Page 427: ...H4 BEH2 BEH2 BEH2 BEH2 BEH1 Cleared by reading I2CSR register BEH2 Cleared by reading I2CDR register BEH3 Cleared by reading I2CDR register set AA 0 to send NACK signal Header A BEH1 STA BEH1 BEH3 BEH3 BEH4 Cleared by reading I2CDR register set STOP 1 to send STOP signal NA NA Sr RXDNE RXDNE RXDNE RXDNE RXDNE RXDNE RXDNE RXDNE ADRS 1 ADRS 2 Figure 150 Master Receiver Timing Diagram Slave Transmitt...

Page 428: ...E TXDE TXDE TXDE Header A BEH1 BEH4 Cleared by reading I2CSR register 7 bit Slave Transmitter BEH2 TXDE RXNACK NA ADRS ADRS 2 ADRS 1 NA RXNACK Sr Figure 151 Slave Transmitter Timing Diagram Slave Receiver Mode Address Frame The ADRS bit in the I2CSR register is set after the slave device receives the calling address which matches with the slave device address After the ADRS bit has been set to 1 i...

Page 429: ...nditions will cause the SCL line to be held at a logic low state by hardware resulting in all the I2 C transfers being stopped Data transfer will be continued after the creating conditions are eliminated Table 47 Conditions of Holding SCL line Type Condition Description Eliminating Condition Flag TXDE I2 C is used in transmitter mode and I2CDR register needs to have data to transmit Note TXDE won ...

Page 430: ...DE RXDNE RXNACK GCS or ADRS flag is asserted The timeout counter will stop counting when the ENTOUT bit is cleared However the counter will also stop counting when one of the conditions listed as follows occurs The I2 C slave module is not addressed The I2 C slave module detects a STOP signal The I2 C master module sends a STOP signal The ARBLOS or BUSERR flag in the I2CSR register is asserted If ...

Page 431: ...00 I2CTAR 0x01C I2 C Target Register 0x0000_0000 I2CADDMR 0x020 I2 C Address Mask Register 0x0000_0000 I2CADDSR 0x024 I2 C Address Snoop Register 0x0000_0000 I2CTOUT 0x028 I2 C Timeout Register 0x0000_0000 Register Descriptions I2 C Control Register I2CCR This register specifies the corresponding I2 C function enable control Offset 0x000 Reset value 0x0000_2000 31 30 29 28 27 26 25 24 Reserved Typ...

Page 432: ...fined in the corresponding PDMA register 8 TXDMAE DMA Mode TX Request Enable Control 0 TX DMA request is disabled 1 TX DMA request is enabled If the data register is empty in the transmitter mode and the TXDMAE bit is set to 1 the relevant PDMA channel will be activated to move the data from a specific location defined in the related PDMA register to the data register 7 ADRM Addressing Mode 0 7 bi...

Page 433: ... disabled 1 Interrupt is enabled 17 TXDEIE Data Register Empty Interrupt Enable Bit in Transmitter Mode 0 Interrupt is disabled 1 Interrupt is enabled 16 RXDNEIE Data Register Not Empty Interrupt Enable Bit in Received Mode 0 Interrupt is disabled 1 Interrupt is enabled 11 TOUTIE Timeout Interrupt Enable Bit 0 Interrupt is disabled 1 Interrupt is enabled 10 BUSERRIE Bus Error Interrupt Enable Bit ...

Page 434: ... used for the I2 C master mode only I2 C Address Register I2CADDR This register specifies the I2 C device address Offset 0x008 Reset value 0x0000_0000 31 30 29 28 27 26 25 24 Reserved Type Reset 23 22 21 20 19 18 17 16 Reserved Type Reset 15 14 13 12 11 10 9 8 Reserved ADDR Type Reset RW 0 RW 0 7 6 5 4 3 2 1 0 ADDR Type Reset RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 Bits Field Descriptions 9 0 ADDR...

Page 435: ...erface is switched as a master device on the I2 C bus when the I2CTAR register is assigned and the I2 C bus is idle The MASTER bit is cleared by hardware when software disables the I2 C bus by clearing the I2CEN bit to 0 or sends a STOP condition to the I2 C bus or the bus error is detected This bit is set and cleared by hardware and is a read only bit 19 BUSBUSY Bus Busy 0 I2 C bus is idle 1 I2 C...

Page 436: ...e I2 C interface detects a misplaced START or STOP condition in a transfer process Writing a 1 to this bit will clear the BUSERR flag In Master Mode Once the Bus Error event occurs both the SDA and SCL lines are released by hardware and the BUSERR flag is asserted The application software has to clear the BUSERR flag before the next address byte is transmitted In Slave Mode Once a misplaced START ...

Page 437: ...nowledged this bit will also be set Address Matched in Slave Mode 0 I2 C interface is not addressed 1 I2 C interface is addressed as slave When the I2 C interface has received the calling address that matches the address defined in the I2CADDR register together with the AA bit being set to 1 in the I2CCR register it will be switched to a slave mode This flag is cleared automatically after the I2CS...

Page 438: ...pe Reset 23 22 21 20 19 18 17 16 Reserved Type Reset 15 14 13 12 11 10 9 8 SHPG Type Reset RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 7 6 5 4 3 2 1 0 SHPG Type Reset RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 Bits Field Descriptions 15 0 SHPG SCL Clock High Period Generation High period duration setting SCLHIGH TPCLK SHPG d where TPCLK is the APB bus peripheral clock PCLK period and d value depends on t...

Page 439: ...its Field Descriptions 15 0 SLPG SCL Clock Low Period Generation Low period duration setting SCLLOW TPCLK SLPG d where TPCLK is the APB bus peripheral clock PCLK period and d value depends on the setting of SEQFILTER in the I2 C Control Register I2CCR If SEQFILTER 00 d 6 If SEQFILTER 01 d 8 If SEQFILTER 10 or 11 d 9 SCL High period duration TPCLK SHPG d Low period duration TPCLK SLPG d High period...

Page 440: ...ype Reset 7 6 5 4 3 2 1 0 DATA Type Reset RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 Bits Field Descriptions 7 0 DATA I2 C Data Register For the transmitter mode a data byte which is transmitted to a slave device can be assigned to these bits The TXDE flag is cleared if the application software assigns new data to the I2CDR register For the receiver mode a data byte is received bit by bit from MSB to...

Page 441: ...rection to target slave address 1 Read direction from target slave address If this bit is set to 1 in the 10 bit master receiver mode the I2 C interface will initiate a byte with a value of 11110XX0b in the first header frame and then continue to deliver a byte with a value of 11110XX1b in the second header frame by hardware automatically 9 0 TAR Target Slave Address The I2 C interface will assign...

Page 442: ... 17 16 Reserved Type Reset 15 14 13 12 11 10 9 8 Reserved ADDMR Type Reset RW 0 RW 0 7 6 5 4 3 2 1 0 ADDMR Type Reset RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 Bits Field Descriptions 9 0 ADDMR Address Mask Control Bit The ADDMR i is used to specify whether the ith bit of the ADDR field in the I2CADDR register is masked and is compared with the received address frame or not on the I2 C bus The regis...

Page 443: ...on the I2 C bus Offset 0x024 Reset value 0x0000_0000 31 30 29 28 27 26 25 24 Reserved Type Reset 23 22 21 20 19 18 17 16 Reserved Type Reset 15 14 13 12 11 10 9 8 Reserved ADDSR Type Reset RO 0 RO 0 7 6 5 4 3 2 1 0 ADDSR Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 Bits Field Descriptions 9 0 ADDSR Address Snoop Once the I2CEN bit is enabled the calling address value on the I2 C bus will aut...

Page 444: ...C timeout counter clock frequency fI2CTO The timeout clock frequency is obtained using the following formula fI2CTO fPCLK 2PSC PSC 0 fI2CTO fPCLK 20 fPCLK PSC 1 fI2CTO fPCLK 21 fPCLK 2 PSC 2 fI2CTO fPCLK 22 fPCLK 4 PSC 7 fI2CTO fPCLK 27 fPCLK 128 15 0 TOUT I2 C Timeout Counter Preload Value The TOUT field is used to define the counter preloaded value The counter value is reloaded as any one of the...

Page 445: ...who controls the data flow using the SEL and SCK signals to indicate the start of the data communication and the data sampling rate To receive the data bits the streamlined data bits which range from 1 bit to 16 bits specified by the DFL field in the SPICR1 register are latched on a specific clock edge and stored in the data register or in the RX FIFO Data transmission is carried out in a similar ...

Page 446: ...etting the MODE bit in the SPICR1 register When the MODE bit is set the SPI module is configured as a master and will generate the serial clock on the SPI_SCK pin The data stream will transmit data in the shift register to the SPI_MOSI pin on the serial clock edge The SPI_SEL pin is active during the full data transmission When the SELAP bit in the SPICR1 register is set the SPI_SEL pin is active ...

Page 447: ...ormats contained in the SPI interface The accompanying table shows how to configure these formats by setting the FORMAT field in the SPICR1 register Table 50 SPI Interface Format Setup FORMAT 2 0 CPOL CPHA 001 0 0 010 0 1 110 1 0 101 1 1 Others Reserved CPOL 0 CPHA 0 In this format the received data is sampled on the SCK line rising edge while the transmitted data is changed on the SCK line fallin...

Page 448: ...is changed on the SCK line rising edge In the master mode the first bit is driven when data is written into the SPIDR register In the slave mode the first bit is driven at the first SCK clock rising edge The accompanying figure shows the single data byte transfer timing SCK MISO MOSI TX 7 TX 6 TX 5 TX 4 TX 3 TX 2 TX 1 TX 0 RX 7 RX 6 RX 5 RX 4 RX 3 RX 2 RX 1 SCK SEL SELAP 1 RX 0 Data sampled SEL SE...

Page 449: ... driven when the SEL signal changes to an active level The accompanying figure shows the single byte transfer timing of this format SCK MISO MOSI TX 7 TX 6 TX 5 TX 4 TX 3 TX 2 TX 1 TX 0 RX 7 RX 6 RX 5 RX 4 RX 3 RX 2 RX 1 SCK SEL SELAP 0 SEL SELAP 1 RX 0 Data sampled Figure 159 SPI Single Byte Transfer Timing Diagram CPOL 1 CPHA 0 The accompanying figure shows the continuous data transfer timing of...

Page 450: ...rst bit is driven at the first SCK falling edge The accompanying figure shows the single byte transfer timing of this format SCK MISO MOSI TX 7 TX 6 TX 5 TX 4 TX 3 TX 2 TX 1 TX 0 RX 7 RX 6 RX 5 RX 4 RX 3 RX 2 RX 1 SCK SEL SELAP 0 SEL SELAP 1 RX 0 Data sampled Figure 161 SPI Single Byte Transfer Timing Diagram CPOL 1 CPHA 1 The accompanying figure shows the continuous data transfer timing of this f...

Page 451: ...ed to read data from an external device synchronously In addition the Dual mode only supports a data length of 16 bit DFL 0x8 The Dual mode is commonly used to read data from an external serial SPI Flash The following figures show the transfer format bit sequences in the SPI Dual mode SCK SEL SELAP 1 MOSI MISO SCK Data sampled SEL SELAP 0 RX 14 RX 12 RX 10 RX 8 RX 7 RX 15 RX 13 RX 11 RX 9 DUALEN R...

Page 452: ...RX 7 RX 5 RX 3 RX 1 RX 14 RX 13 RX 12 RX 11 RX 10 RX 9 RX 8 RX 0 Data sampled SCK Figure 165 SPI Dual Mode Bit Sequence CPOL 1 CPHA 0 DFL 0x8 16 bit MSB Transmitted First SCK MISO MOSI SEL SELAP 0 SEL SELAP 1 DUALEN RX 6 RX 4 RX 2 RX 15 RX 7 RX 5 RX 3 RX 1 RX 14 RX 13 RX 12 RX 11 RX 10 RX 9 RX 8 RX 0 SCK Data sampled Figure 166 SPI Dual Mode Bit Sequence CPOL 1 CPHA 1 DFL 0x8 16 bit MSB Transmitte...

Page 453: ...on Register Empty TXE This TXE flag is set when both the TX buffer and the TX shift registers are empty It will be reset when the TX buffer or the TX shift register contains new transmitted data RX Buffer Not Empty RXBNE This RXBNE flag is set when there is valid received data in the RX buffer in the non FIFO mode or the RX FIFO data length is equal to or greater than the RX FIFO threshold level a...

Page 454: ...at another SPI master is requesting to use the SPI bus Therefore when an SPI mode fault occurs it will force the SPI module to operate in the slave mode and also disable all of the SPI interface signals to avoid SPI bus signal collisions For the same reason if the SPI master wants to transfer data it also needs to inform other SPI masters by driving their SEL signals to an active state The detaile...

Page 455: ...egister Write Collision WC The following conditions will assert the Write Collision Flag The FIFOEN bit in the SPIFCR register is cleared The write collision flag is asserted when new data is written into the SPIDR register while both the TX buffer and the shift register are already full Any new data written into the TX buffer will be lost The FIFOEN bit in the SPIFCR register is set The write col...

Page 456: ...n will be activated to move data from the SPI data register or the RX FIFO to the memory location that users designated until the RXBNE flag is cleared to 0 The RXBNE flag will be asserted when the receive buffer is not empty in the non FIFO mode or the data contained in the RX FIFO is equal to or greater than the level defined by the RXFTLS field in the FIFO mode For a more detailed description a...

Page 457: ... 0 RW 0 RW 0 RW 0 RW 0 Bits Field Descriptions 15 12 SELHT Chip Select Hold Time 0x0 1 2 SCK 0x1 1 SCK 0x2 3 2 SCK 0x3 2 SCK Note that SELHT is for master mode only 11 8 GUADT Guard Time GUADTEN 1 0x0 1 SCK 0x1 2 SCK 0x2 3 SCK Note that GUADT is for master mode only 7 GUADTEN Guard Time Enable 0 Guard Time is 1 2 SCK 1 When this bit is set guard time can be controlled by GUADT Note that GUADTEN is...

Page 458: ...effect 3 SELOEN Slave Select Output Enable 0 Set the SEL signal to the input mode for multi master mode 1 Set the SEL signal to the output mode for slave select The SELOEN is only available in the master mode to set the SEL signal as an input or output signal When the SEL signal is configured to operate in the output mode it is used as a slave select signal in either the hardware or software mode ...

Page 459: ...0 9 8 Reserved MODE SELM FIRSTBIT SELAP FORMAT Type Reset RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 7 6 5 4 3 2 1 0 Reserved DFL Type Reset RW 0 RW 0 RW 0 RW 0 Bits Field Descriptions 14 MODE Master or Slave Mode 0 Slave mode 1 Master mode 13 SELM Slave Select Mode 0 SEL signal is controlled by software asserted or de asserted by the SSELC bit 1 SEL signal is controlled by hardware generated automaticall...

Page 460: ...Data is captured on the second SCK clock edge 3 0 DFL Data Frame Length Selects the data transfer frame from 1 bit to 16 bits DFL 3 0 SPI Serial Mode SPI Dual Mode 0001 1 bit 0010 2 bits 0011 3 bits 0100 4 bits 0101 5 bits 0110 6 bits 0111 7 bits 1000 8 bits 16 bits 1001 9 bits 1111 15 bits 0000 16 bits Notes 1 The total number of data bits is determined by the DFL field configuration together wit...

Page 461: ... Enable 5 MFIEN Mode Fault Interrupt Enable 0 Disable 1 Enable 4 ROIEN Read Overrun Interrupt Enable 0 Disable 1 Enable 3 WCIEN Write Collision Interrupt Enable 0 Disable 1 Enable 2 RXBNEIEN RX Buffer Not Empty Interrupt Enable 0 Disable 1 Enable An interrupt is generated when the RXBNE flag is set and RXBNEIEN is set In the FIFO mode the interrupt being generated depends upon the RX FIFO trigger ...

Page 462: ...25 24 Reserved Type Reset 23 22 21 20 19 18 17 16 Reserved Type Reset 15 14 13 12 11 10 9 8 CP Type Reset RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 7 6 5 4 3 2 1 0 CP Type Reset RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 Bits Field Descriptions 15 0 CP SPI Clock Prescaler The SPI clock SCK is determined by the following equation fSCK fPCLK 2 CP 1 where the CP ranges is from 0 to 65535 Note For the SPI ...

Page 463: ...Type Reset 15 14 13 12 11 10 9 8 DR Type Reset RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 7 6 5 4 3 2 1 0 DR Type Reset RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 Bits Field Descriptions 15 0 DR Data Register The SPI data register is used to store the serial bus transmitted or received data In the non FIFO mode writing data into the SPI data register will also load the data into the data transmission bu...

Page 464: ...hen SEL changes to an active level and is reset when SEL changes to an inactive level 7 TO Time Out flag 0 No RX FIFO time out 1 RX FIFO time out has occurred Once the time out counter value is equal to the TOC field setting in the SPIFTOCR register the time out flag will be set and an interrupt will be generated if the TOIEN bit in the SPIIER register is enabled This bit is cleared by writing 1 N...

Page 465: ...r is not empty 1 TX buffer and TX shift register both are empty 0 TXBE TX Buffer Empty flag 0 TX buffer is not empty 1 TX buffer is empty In the FIFO mode this bit if set indicates that the number of data contained in TX FIFO is equal to or less than the trigger level specified by the TXFTLS field in the SPIFCR register SPI FIFO Control Register SPIFCR This register contains the related SPI FIFO c...

Page 466: ...ger level is 0 0001 Trigger level is 1 1000 Trigger level is 8 Others Reserved The TXFTLS field is used to specify the TX FIFO trigger level When the number of data contained in the TX FIFO is equal to or less than the trigger level defined by the TXFTLS field the TXBE flag will be set SPI FIFO Status Register SPIFSR This register contains the relevant SPI FIFO status Offset 0x01C Reset value 0x00...

Page 467: ...W 0 RW 0 RW 0 RW 0 Bits Field Descriptions 15 0 TOC Time Out Counter Compare Value The time out counter starts to count from 0 after the SPI RX FIFO receives a data and the counter value is reset once the data is read from the SPIDR register by software or another new data is received If the FIFO does not receive new data or the software does not read data from the SPIDR register the time out coun...

Page 468: ...ART module includes an 8 level transmit FIFO TX FIFO and an 8 level receive FIFO RX FIFO Software can detect a USART error status by reading the USART Status Interrupt Flag Register USRSIFR The status includes the condition of the transfer operations as well as several error conditions resulting from Parity Overrun Framing and Break events The USART includes a programmable baud rate generator whic...

Page 469: ...frame error FIFO Receive FIFO 8 level Transmit FIFO 8 level Supports PDMA Interface the PDMA related describes are only available for the HT32F54243 HT32F54253 devices Functional Descriptions Serial Data Format The USART module performs a parallel to serial conversion on data that is written to the transmit FIFO registers and then sends the data with the following format Start bit 7 9 LSB MSB firs...

Page 470: ...t Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7 Parity Bit WLS 1 0 b00 PBE 0 WLS 1 0 b01 PBE 0 WLS 1 0 b00 PBE 1 WLS 1 0 b10 PBE 0 WLS 1 0 b01 PBE 1 Figure 170 USART Serial Data Format Baud Rate Generation The baud rate for the USART receiver and transmitter are both set with the same values The baud rate divisor BRD has the following relationship with the USART clock which is known as CK_ USART Baud Ra...

Page 471: ...00 Table 55 Baud Rate Deviation Error Calculation CK_USART 48 MHz Baud Rate CK_USART 48 MHz No Kbps Actual BRD Deviation Error Rate 1 2 4 2 4 20000 0 00 2 9 6 9 6 5000 0 00 3 19 2 19 2 2500 0 00 4 57 6 57 6 833 0 04 5 115 2 115 1 417 0 08 6 230 4 230 8 208 0 16 7 460 8 461 5 104 0 16 8 921 6 923 1 52 0 16 9 2250 2285 7 21 1 59 10 3000 3000 0 16 0 00 Table 56 Baud Rate Deviation Error Calculation C...

Page 472: ...tive with a logic low state when the receive data register is empty It means that the receiver is ready to receive a new data When the RX FIFO reaches the trigger level which is specified by configuring the RXTL field in the USRFCR register the USART RTS pin is inactive with a logic high state Figure 215 shows the example of RTS flow control Start Bit Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit N Parity Bit...

Page 473: ... Bit Bit 0 Figure 174 USART CTS Flow Control IrDA The USART IrDA mode is provided for half duplex point to point wireless communication The USART module includes an integrated modulator and demodulator which allow a wireless communication using infrared transceivers The transmitter specifies a logic data 0 as a high pulse and a logic data 1 as a low level while the Receiver specifies a logic data ...

Page 474: ...is bit duration The IrDAPSC value must be set to be greater than or equal to 0x01 then the IrDA receiver demodulation operation can function properly The IrDAPSC value can be adjusted to meet the USART baud rate setting to filter the IrDA received glitch noise of which the width is smaller than the prescaler setting duration IrDA Low Power Mode In the IrDA low power mode the transmitted IrDA pulse...

Page 475: ...age Without this common reference the transceiver may interpret the differential signals incorrectly This enhances the noise rejection capabilities of the RS485 interface The USART RTS pin is used to control the external RS485 transceiver whose polarity can be selected by configuring the TXENP bit in the RS485 Control Register named RS485CR when the USART operates in the RS485 mode RS485 Auto Dire...

Page 476: ... register Regardless of the URRXEN value in the USRCR register all the received data with a parity bit 0 will be ignored until the first address byte is detected with a parity bit 1 and then the received address byte will be stored in the RX FIFO Once the first address data is detected and stored in the RX FIFO the RSADD flag in the USRSIFR register will be set and generate an interrupt if the RSA...

Page 477: ...l duplex style in the USART Synchronous Master Mode i e data transmission and reception both occur at the same time and only support master mode The USART CTS pin is the synchronous USART transmitter clock output In this mode no clock pulses will be sent to the CTS pin during the start bit parity bit and stop bit duration The CPS bit in the Synchronous Control Register SYNCR can be used to determi...

Page 478: ... D5 D6 Parity D0 D1 D2 D3 D4 D5 D6 Parity Start Stop USART TX From Master to Slave USART RX From Slave to Master Clock CPO 0 Clock CPO 1 CPS 1 WLS 1 0 b00 PBE 1 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 Start Stop USART TX From Master to Slave USART RX From Slave to Master Clock CPO 0 Clock CPO 1 CPS 0 WLS 1 0 b01 PBE 0 D0 D1 D2 D3 D4 D5 D6 Parity D0 D1 D2 D3 D4 D5 D6 Parity Start Stop USART...

Page 479: ...ansmit or receive mode respectively When the data to be transmitted in the USART Transmit FIFO is less than the TX FIFO threshold level specified by the TXTL field in the USRFCR register and the TXDMAEN bit is set to 1 the PDMA function will be activated to move data from a source location into the USART TX FIFO Similarly when the received data amount in the receive FIFO is equal to the RX FIFO th...

Page 480: ...escriptions 8 0 DB Reading data from this receiver buffer register will return the data from the receive FIFO The receive FIFO has a capacity of up to 8 9 bits By reading this register the USART will return a 7 8 and 9 bit received data The DB field bit 8 is valid for the 9 bit mode only and is fixed at 0 for the 8 bit mode For the 7 bit mode the DB 6 0 field contains the available bits Writing da...

Page 481: ...d indicates the pin status that is controlled by hardware flow control function 14 BCB Break Control Bit When this bit is set 1 the serial data output on the USART TX pin will be forced to the Spacing State logic 0 This bit acts only on the USART TX output pin and has no effect on the transmitter logic 13 SPE Stick Parity Enable 0 Disable stick parity 1 Stick Parity bit is transmitted This bit is ...

Page 482: ...length is selected 9 8 WLS Word Length Select 00 7 bits 01 8 bits 10 9 bits 11 Reserved 7 RXDMAEN USART RX DMA Enable 0 Disable 1 Enable 6 TXDMAEN USART TX DMA Enable 0 Disable 1 Enable 5 URRXEN USART RX Enable 0 Disable 1 Enable 4 URTXEN USART TX Enable 0 Disable 1 Enable 3 HFCEN Hardware Flow Control Function Enable 0 Disable 1 Enable 2 TRSM Transfer Mode Selection This bit is used to select the...

Page 483: ...S RX FIFO Status The RXFS field shows the current number of data contained in the RX FIFO 0000 RX FIFO is empty 0001 RX FIFO contains 1 data 1000 RX FIFO contains 8 data Others Reserved 19 16 TXFS TX FIFO Status The TXFS field shows the current number of data contained in the TX FIFO 0000 TX FIFO is empty 0001 TX FIFO contains 1 data 1000 TX FIFO contains 8 data Others Reserved 7 6 RXTL RX FIFO Th...

Page 484: ... 30 29 28 27 26 25 24 Reserved Type Reset 23 22 21 20 19 18 17 16 Reserved Type Reset 15 14 13 12 11 10 9 8 Reserved CTSIE RXTOIE Type Reset RW 0 RW 0 7 6 5 4 3 2 1 0 RSADDIE BIE FEIE PEIE OEIE TXCIE TXDEIE RXDRIE Type Reset RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 Bits Field Descriptions 9 CTSIE CTS Clear To Send Interrupt Enable 0 Disable 1 Enable If this bit is set an interrupt will be generated...

Page 485: ... in the USRSIFR register is set 3 OEIE Overrun Error Interrupt Enable 0 Disable 1 Enable If this bit is set an interrupt will be generated when the OEI bit in the USRSIFR register is set 2 TXCIE Transmit Complete Interrupt Enable 0 Disable 1 Enable If this bit is set an interrupt will be generated when the TXC bit in the USRSIFR register is set 1 TXDEIE Transmit Data Empty Interrupt Enable 0 Disab...

Page 486: ...1 to this bit clears the flag 9 RSADD RS485 Address Detection 0 Address is not detected 1 Address is detected This bit will be set to 1 when the receiver detects the address An interrupt will be generated if the RSADDIE bit in the USRIER register is set Writing 1 to this bit clears the flag Note This bit is only used in the RS485 mode by setting the MODE field in the USRCR register 8 TXC Transmit ...

Page 487: ...to 1 whenever the received data input is held in the spacing state logic 0 for longer than a full word transmission time which is the total time of start bit data bits parity stop bits duration Writing 1 to this bit clears the flag 3 FEI Framing Error Indicator This bit will be set 1 whenever the next character to be read in the RX FIFO does not have a valid stop bit which means the stop bit follo...

Page 488: ...nsmitter Time Guard The transmitter time guard counter is driven by the baud rate clock When the TX FIFO transmits data the counter is reset and then starts to count after a word transmission has completed Only when the counter content is equal to the TG value are further word transmission transactions allowed 7 RXTOEN Receive FIFO Time Out Counter Enable 0 RX FIFO Time Out Counter is disabled 1 R...

Page 489: ... driven by the USART clock named as CK_ USART The counting period is specified by the IrDAPSC field The IrDAPSC field must be set to a value equal to or greater than 0x01 for normal debounce counter operation If the pulse width is less than the duration specified by the IrDAPSC field the pulse will be considered as glitch noise and discarded 00000000 Reserved cannot be used 00000001 CK_USART clock...

Page 490: ...20 19 18 17 16 Reserved Type Reset 15 14 13 12 11 10 9 8 ADDMATCH Type Reset RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 7 6 5 4 3 2 1 0 Reserved RSAAD RSNMM TXENP Type Reset RW 0 RW 0 RW 0 Bits Field Descriptions 15 8 ADDMATCH RS485 Auto Address Match value The field contains the address match value for the RS485 auto address detection operation mode 2 RSAAD RS485 Auto Address Detection Operation Mod...

Page 491: ... 0 RW 0 Bits Field Descriptions 3 CPO Clock Polarity 0 CTS SCK pin idle state is low 1 CTS SCK pin idle state is high This bit can be used to select the polarity of the clock output on the USART CTS SCK pin in the synchronous mode Works in conjunction with the CPS bit to specify the desired clock idle state 2 CPS Clock Phase 0 Data is captured on the first clock edge 1 Data is captured on the seco...

Page 492: ...4 Reset value 0x0000_0010 31 30 29 28 27 26 25 24 Reserved Type Reset 23 22 21 20 19 18 17 16 Reserved Type Reset 15 14 13 12 11 10 9 8 BRD Type Reset RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 7 6 5 4 3 2 1 0 BRD Type Reset RW 0 RW 0 RW 0 RW 1 RW 0 RW 0 RW 0 RW 0 Bits Field Descriptions 15 0 BRD Baud Rate Divider The 16 bits define the USART clock divider ratio Baud Rate CK_USART BRD Where the CK_US...

Page 493: ...TSTR This register controls the USART debug mode Offset 0x028 Reset value 0x0000_0000 31 30 29 28 27 26 25 24 Reserved Type Reset 23 22 21 20 19 18 17 16 Reserved Type Reset 15 14 13 12 11 10 9 8 Reserved Type Reset 7 6 5 4 3 2 1 0 Reserved LBM Type Reset RW 0 RW 0 Bits Field Descriptions 1 0 LBM Loopback Test Mode Select 00 Normal Operation 01 Reserved 10 Automatic Echo Mode 11 Loopback Mode ...

Page 494: ...ransmit shift register TSR and a receive data register RDR and receive shift register RSR Software can detect a UART error status by reading the UART Status Interrupt Flag Register URSIFR The status includes the condition of the transfer operations as well as several error conditions resulting from Parity Overrun Framing and Break events The UART includes a programmable baud rate generator which i...

Page 495: ...2 Stop bits The Start bit has the opposite polarity of the data line idle state The Stop bit is the same as the data line idle state and provides a delay before the next start situation Both the Start and Stop bits are used for data synchronization during the asynchronous data transmission The UART module also performs a serial to parallel conversion on the data that is read from the receive data ...

Page 496: ...e the CK_UART clock is the APB clock connected to the UART while the BRD range is from 16 to 65535 CK_UART BRD 18 Reference Divisor Clock Start Bit Bit0 Bit1 Bit2 Bit3 Bit4 Bitn Parity Bit Stop Bit Next Start Bit n 7 8 Figure 182 UART Clock CK_UART and Data Frame Timing Table 58 Baud Rate Deviation Error Calculation CK_UART 40 MHz Baud Rate CK_UART 40 MHz No Kbps Actual BRD Deviation Error Rate 1 ...

Page 497: ...2 115 2 521 0 03 6 230 4 230 8 260 0 16 7 460 8 461 5 130 0 16 8 921 6 923 1 65 0 16 9 2250 2222 2 27 1 23 10 3000 3000 0 20 0 00 Interrupts and Status The UART can generate interrupts when the following events occur and the corresponding interrupt enable bits are set Receiver line status interrupts The interrupts are generated when the UART receiver overrun error parity error framing error and br...

Page 498: ...has been in the UART receive data register RDR and the RXDMAEN bit is set to 1 the PDMA function will be activated to move data from the UART receive data register RDR to a specific destination location For a more detailed description about the PDMA configurations refer to the PDMA chapter Register Map The following table shows the UART registers and reset values The PDMA related describes are onl...

Page 499: ... 12 11 10 9 8 Reserved DB Type Reset RW 0 7 6 5 4 3 2 1 0 DB Type Reset RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 Bits Field Descriptions 8 0 DB By reading this register the UART will return a 7 8 and 9 bit received data The DB field bit 8 is valid for the 9 bit mode only and is fixed at 0 for the 8 bit mode For the 7 bit mode the DB 6 0 field contains the available bits By writing to this register ...

Page 500: ...stick parity 1 Stick Parity bit is transmitted This bit is only available when the PBE bit is set to 1 If both the PBE and SPE bits are set to 1 and the EPE bit is cleared to 0 the transmitted parity bit will be stuck to 1 However when the PBE and SPE bits are set to 1 and also the EPE bit is set to 1 the transmitted parity bit will be stuck to 0 12 EPE Even Parity Enable 0 Odd number of logic 1 s...

Page 501: ... interrupt function The UART module generates interrupts to the controller when the corresponding events occur and the corresponding interrupt enable bits are set Offset 0x00C Reset value 0x0000_0000 31 30 29 28 27 26 25 24 Reserved Type Reset 23 22 21 20 19 18 17 16 Reserved Type Reset 15 14 13 12 11 10 9 8 Reserved Type Reset 7 6 5 4 3 2 1 0 Reserved BIE FEIE PEIE OEIE TXCIE TXDEIE RXDRIE Type R...

Page 502: ...e If this bit is set an interrupt will be generated when the OEI bit in the URSIFR register is set 2 TXCIE Transmit Complete Interrupt Enable 0 Disable 1 Enable If this bit is set an interrupt will be generated when the TXC bit in the URSIFR register is set 1 TXDEIE Transmit Data Register Empty Interrupt Enable 0 Disable 1 Enable If this bit is set an interrupt will be generated when the TXDE bit ...

Page 503: ... of the transmit data register is transferred to the transmit shift register TSR An interrupt will be generated if the TXDEIE bit in the URIER register is set to 1 This bit is cleared by a write to the URDR register with new data 5 RXDR RX Data Ready 0 Receive data register is empty 1 The received data in receive data register is ready to read This bit is set by hardware when the content of the re...

Page 504: ...ll not be transferred to the receive data register The OEI bit is used to indicate event as soon as it happens Writing 1 to this bit clears the flag UART Divider Latch Register URDLR The register is used to determine the UART clock divided ratio to generate the appropriate baud rate Offset 0x024 Reset value 0x0000_0010 31 30 29 28 27 26 25 24 Reserved Type Reset 23 22 21 20 19 18 17 16 Reserved Ty...

Page 505: ...is register controls the UART debug mode Offset 0x028 Reset value 0x0000_0000 31 30 29 28 27 26 25 24 Reserved Type Reset 23 22 21 20 19 18 17 16 Reserved Type Reset 15 14 13 12 11 10 9 8 Reserved Type Reset 7 6 5 4 3 2 1 0 Reserved LBM Type Reset RW 0 RW 0 Bits Field Descriptions 1 0 LBM Loopback Test Mode Select 00 Normal Operation 01 Reserved 10 Automatic Echo Mode 11 Loopback Mode ...

Page 506: ...e PDMA channel transfer is split into multiple block transactions and the size of a block is equal to the block length multiplied by the data width This function is only available for the HT32F54243 HT32F54253 devices Features 6 unidirectional PDMA channels Memory to peripheral peripheral to memory and memory to memory data transfer 8 bit 16 bit and 32 bit width data transfer Software and hardware...

Page 507: ...s Therefore one PDMA channel only can service one peripheral at the same time The related registers of the PDMA channel are limited to be accessed with 32 bit operation otherwise a system hard fault event will occur PDMA Request Mapping The multiple requests from the peripherals ADC SPI I2 C USART and so on are simply logically ANDed before entering the PDMA which means that only one request must ...

Page 508: ...dium and low which can be configured by the application software The PDMA also provides two methods to determine the channel priority One is determined by application software configuration and the other is determined by the fixed hardware channel number The PDMA arbitration processor will first check the software configuring channel priority level used to request the PDMA to provide the data tran...

Page 509: ... transfer of the relevant dedicated PDMA channel will be triggered when a software request occurs It is recommended that the PDMA channel is configured to have a lower priority level and a smaller block length which is requested by the software for memory to memory data copy applications Address Mode The PDMA provides three kinds of address modes which are the linear address circular address and f...

Page 510: ...the corresponding start value after the current PDMA channel data transfer has totally completed The channel n will still be activated and the next relative PDMA request can be serviced without any re configuration using the application software Transfer Interrupt There are five transfer events during which the interrupts can be asserted for each PDMA channel These are the block transaction end BE...

Page 511: ...0 PDMACH2TSR 0x040 PDMA Channel 2 Transfer Size Register 0x0000_0000 PDMACH2CTSR 0x044 PDMA Channel 2 Current Transfer Size Register 0x0000_0000 PDMA Channel 3 Registers PDMACH3CR 0x048 PDMA Channel 3 Control Register 0x0000_0000 PDMACH3SADR 0x04C PDMA Channel 3 Source Address Register 0x0000_0000 PDMACH3DADR 0x050 PDMA Channel 3 Destination Address Register 0x0000_0000 PDMACH3TSR 0x058 PDMA Chann...

Page 512: ...when a transfer is complete If this bit is cleared to 0 the channel n current address and the channel n current transfer size will remain unchanged and the PDMA channel n will be disabled after a transfer completion 10 FIXAENn Channel n Fixed Address Enable control 0 Disable fixed address function in the circular address mode 1 Enable fixed address function in the circular address mode Note that t...

Page 513: ...ss Mode selection 0 Linear address mode 1 Circular address mode In linear address mode the current destination address value can be increased or decreased determined by the DSTAINCn bit value during a complete transfer In the circular address mode the current destination address value can be increased or decreased which is also determined by the DSTAINCn bit value during a block transfer and will ...

Page 514: ...A channel n function for the next transfer request instead of automatically being cleared by hardware after a transfer has finished PDMA Channel n Source Address Register PDMACHnSADR n 0 5 This register specifies the source address of the PDMA channel n Offset 0x004 0 0x01C 1 0x034 2 0x04C 3 0x064 4 0x07C 5 Reset value 0x0000_0000 31 30 29 28 27 26 25 24 SADRn Type Reset RW 0 RW 0 RW 0 RW 0 RW 0 R...

Page 515: ...x050 3 0x068 4 0x080 5 Reset value 0x0000_0000 31 30 29 28 27 26 25 24 DADRn Type Reset RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 23 22 21 20 19 18 17 16 DADRn Type Reset RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 15 14 13 12 11 10 9 8 DADRn Type Reset RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 7 6 5 4 3 2 1 0 DADRn Type Reset RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 Bits Field Descriptions 31 0 DADRn Chan...

Page 516: ... 20 19 18 17 16 BLKCNTn Type Reset RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 15 14 13 12 11 10 9 8 Reserved Type Reset 7 6 5 4 3 2 1 0 BLKLENn Type Reset RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 Bits Field Descriptions 31 16 BLKCNTn Channel n Block Transaction Count BLKCNTn represents the number of block transactions for a channel n complete transfer The capacity of a complete transfer is the product...

Page 517: ...n Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 CBLKCNTn Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 Reserved Type Reset 7 6 5 4 3 2 1 0 Reserved Type Reset Bits Field Descriptions 31 16 CBLKCNTn Channel n Current Block Count The CBLKCNTn field is a 16 bit read only value indicating the number of data blocks that remain to be transferred Af...

Page 518: ...in the PDMAISCR register A Transfer error will occur when the PDMA accesses a system reserved address space or when the PDMA receives a request but the corresponding transfer capacity is equal to zero 28 23 18 13 8 3 TCISTAn Channel n Transfer Complete Interrupt Status n 0 5 0 No Transfer Completion Occurs 1 Transfer Completion Occurs This bit is set by hardware and is cleared by writing a 1 into ...

Page 519: ... 18 17 16 TCICLR4 HTICLR4 BEICLR4 GEICLR4 TEICLR3 TCICLR3 HTICLR3 BEICLR3 Type Reset WC 0 WC 0 WC 0 WC 0 WC 0 WC 0 WC 0 WC 0 15 14 13 12 11 10 9 8 GEICLR3 TEICLR2 TCICLR2 HTICLR2 BEICLR2 GEICLR2 TEICLR1 TCICLR1 Type Reset WC 0 WC 0 WC 0 WC 0 WC 0 WC 0 WC 0 WC 0 7 6 5 4 3 2 1 0 HTICLR1 BEICLR1 GEICLR1 TEICLR0 TCICLR0 HTICLR0 BEICLR0 GEICLR0 Type Reset WC 0 WC 0 WC 0 WC 0 WC 0 WC 0 WC 0 WC 0 Bits Fi...

Page 520: ... the related interrupts of the PDMA channel 0 5 Offset 0x130 Reset value 0x0000_0000 31 30 29 28 27 26 25 24 Reserved TEIE5 TCIE5 HTIE5 BEIE5 GEIE5 TEIE4 Type Reset RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 23 22 21 20 19 18 17 16 TCIE4 HTIE4 BEIE4 GEIE4 TEIE3 TCIE3 HTIE3 BEIE3 Type Reset RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 15 14 13 12 11 10 9 8 GEIE3 TEIE2 TCIE2 HTIE2 BEIE2 GEIE2 TEIE1 TCIE1 Type Reset R...

Page 521: ...n Block Transaction End Interrupt Enable control n 0 5 0 Block Transaction End interrupt is disabled 1 Block Transaction End interrupt is enabled This bit is set and cleared by software 25 20 15 10 5 0 GEIEn Channel n Global Transfer Event Interrupt Enable control n 0 5 0 Global Transfer Event interrupt is disabled 1 Global Transfer Event interrupt is enabled This bit is set and cleared by softwar...

Page 522: ... the truncated division are related in the following way A B Q R Where A is Dividend B is Divisor Q is Quotient and R is Remainder Divider requires a software trigger start signal by controlling the START bit in the CR register The divider calculation complete flag will be set to 1 after 8 clock cycles however if the divisor register data is zero during the calculation the division by zero error f...

Page 523: ... the calculation start control bit Offset 0x000 Reset value 0x0000_0008 31 30 29 28 27 26 25 24 Reserved Type Reset 23 22 21 20 19 18 17 16 Reserved Type Reset 15 14 13 12 11 10 9 8 Reserved Type Reset 7 6 5 4 3 2 1 0 Reserved COM ZEF Reserved START Type Reset RO 1 RO 0 RW 0 Bits Field Descriptions 3 COM Calculation Complete Flag 0 Data are invalid 1 New data are valid When this bit is set to 1 by...

Page 524: ... DDR Type Reset RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 Bits Field Descriptions 31 0 DDR This bit field is used to specify the dividend of the divider calculation Divisor Data Register DSR The register contains the divisor of the divider Offset 0x008 Reset value 0x0000_0000 31 30 29 28 27 26 25 24 DSR Type Reset RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 23 22 21 20 19 18 17 16 DSR Type Reset RW 0 RW...

Page 525: ... Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 Bits Field Descriptions 31 0 QTR This bit field is used to store the queotient of the divider calculation result Remainder Data Register RMR The register contains the remainder of the divider calculation result Offset 0x010 Reset value 0x0000_0000 31 30 29 28 27 26 25 24 RMR Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RM...

Page 526: ...e calculated earlier that means data stream contains a data error CRC Control Register CRC Seed Register B3 B2 B1 B0 MUX 1 s COMP BIT REVERSE CCITT 16 POLY CRC 16 POLY CRC 32 POLY MUX MUX CRC REG 1 s COMP BIT REVERSE BYTE REVERSE CRC FSM AHB Bus CRC Data Register CRC Sum Register BYTE REVERSE Figure 187 CRC Block Diagram Features Supports CRC16 polynomial 0x8005 X16 X15 X2 1 Supports CCITT CRC16 p...

Page 527: ...epends on data width 4 AHB clock cycles for 32 bit data input 2 AHB clock cycles for 16 bit data input 1 AHB clock cycle for 8 bit data input Byte and Bit Reversal for CRC Computation The byte reordering and byte level bit reversal operation can be occurred before the data is used in the CRC calculation or after the CRC checksum output They are configurable using the corresponding setting field of...

Page 528: ... the CRC checksum register CRCCSR Register Map The following table shows the CRC registers and reset values Table 66 CRC Register Map Register Offset Description Reset Value CRCCR 0x000 CRC Control Register 0x0000_0000 CRCSDR 0x004 CRC Seed Register 0x0000_0000 CRCCSR 0x008 CRC Checksum Register 0x0000_0000 CRCDR 0x00C CRC Data Register 0x0000_0000 Register Descriptions CRC Control Register CRCCR ...

Page 529: ...mial 00 CRC CCITT 0x1021 01 CRC 16 0x8005 1x CRC 32 0x04C11DB7 CRC Seed Register CRCSD This register is used to specify the CRC seed Offset 0x004 Reset value 0x0000_0000 31 30 29 28 27 26 25 24 SEED Type Reset WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 23 22 21 20 19 18 17 16 SEED Type Reset WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 15 14 13 12 11 10 9 8 SEED Type Reset WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO...

Page 530: ...31 0 CHKSUM CRC Checksum Data Get the CRC 16 32 bit checksum result from this register according to the polynomial setting in the CRCCR register after all data are written to the CRCDR register CRC Data Register CRCDR This register is used to specify the CRC input data Offset 0x00C Reset value 0x0000_0000 31 30 29 28 27 26 25 24 CRCDATA Type Reset WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 23 22 21 2...

Page 531: ... In a complete frame period tframe the enabled COMs will be scanned from the lower to the higher Taking an example of where four 8 segment LEDs are used and where COM0 COM5 COM6 and COM7 are enabled Here COM0 COM5 COM6 and the COM7 will be scanned successively in this sequence within a complete frame period The scanning time of each COM port is equal to 1 4 tframe which is subdivided into the dead...

Page 532: ...OMyEN bit in the LEDCER register Configure the required COMy and SEGx pins for the LEDC functions using the AFIO function Set the current drive capability of the COMy and SEGx Select the COMy and SEGx output polarity by configuring the LEDPCR register Select the dead time clock number by the DEADNUM bit field in the LEDDTCR register Initialise the LEDDR register The LEDEN bit in the LEDCR is set h...

Page 533: ... reason it may be necessary to invert the SEGx or COMy outputs in applications which can be implemented by configuring the SEGx or COMy polarity control bits The SEGxPOL bit is used to control the SEGx polarity If SEGxPOL is set to 1 then SEGx will be an inverted output The COMyPOL bit is used to control the COMy polarity If COMyPOL is set to 1 then COMy will be an inverted output The following wi...

Page 534: ...e 8 segment Digital Display NPN BJT Connection SEGx output low and COMy output high LED on COMy output low LED off Due to the I O drive capability limitation an external transistor is needed to increase the current drive capability if using this connection method The register configurations are as follows Set SEGxPOL 1 and COMyPOL 1 the output is inverted Set DTYNUM 1 0 b11 the period of each digi...

Page 535: ... NPN BJT Timing Common Cathode 8 segment Digital Display Connection NPN Transistor SEG output high and COM output high LED on COM output low LED off Connect an external transistor to prevent the LED current from affecting the device The register configurations are as follows Set SEGxPOL 1 and COMyPOL 1 the output is inverted Set DTYNUM 1 0 b11 the period of each digital display scan is 64 CK_LED c...

Page 536: ... Cathode 8 segment Digital Display NPN Transistor Timing Common Anode 8 segment Digital Display PNP BJT Connection SEG output low and COM output low LED on COM output high LED off The register configurations are as follows Set SEGxPOL 1 the output is inverted Set COMyPOL 0 the output is non inverted Set DTYNUM 1 0 b11 the period of each digital display scan is 64 CK_LED clocks The selected COMs ar...

Page 537: ...T Timing LEDC Frame Interrupt The frame interrupt can be enabled after the pixel data of the last COM duty is latched Users can update the pixel data or adjust the dead time duty in the interrupt service routine The Frame interrupt flag FIF in the LEDSR register is set by hardware and reset by software by writing a 1 to it CK_LED SEGx SEGxPOL 0 1 N frame 64 clocks DTYNUM 11 N 4 C0Sx COM Duty 59 cl...

Page 538: ...r the HT32F54243 HT32F54253 the maximum value of N is 12 The duty clock number can be configured as 8 16 32 or 64 by the DTYNUM 1 0 bit field in the LEDDTCR register The fCK_LED is calculated by the following formula The fclock source can be selected to be sourced from LSI LSE or PCLK fCK_LED fclock source LEDPS 1 Examples 1 If the CK_LED clock source fclock source is 32 768 kHz DTYNUM 1 0 b11 LED...

Page 539: ...gister 0x0000_0000 LEDSR 0x010 LED Status Register 0x0000_0000 LEDDTCR 0x014 LED Dead Time Control Register 0x0000_0000 LEDDR0 0x018 LED Data Register 0 0x0000_0000 LEDDR1 0x01C LED Data Register 1 0x0000_0000 LEDDR2 0x020 LED Data Register 2 0x0000_0000 LEDDR3 0x024 LED Data Register 3 0x0000_0000 LEDDR4 0x028 LED Data Register 4 0x0000_0000 LEDDR5 0x02C LED Data Register 5 0x0000_0000 LEDDR6 0x0...

Page 540: ...set RW 0 RW 0 RW 0 RW 0 7 6 5 4 3 2 1 0 Reserved LEDEN Type Reset RW 0 Bits Field Descriptions 27 16 LEDPS LEDC Clock Prescaler 0x000 CK_LED PCLK 1 0x001 CK_LED PCLK 2 0x002 CK_LED PCLK 3 0xFFF CK_LED PCLK 4096 13 12 DTYNUM Duty Clock Numbers 00 8 CK_LED clocks 01 16 CK_LED clocks 10 32 CK_LED clocks 11 64 CK_LED clocks Assuming that N digital displays are used the number of COMs is N Each digital...

Page 541: ...e LED COM Enable Register LEDCER This register is used to control the COMy enable y 0 11 Offset 0x004 Reset value 0x0000_0000 31 30 29 28 27 26 25 24 Reserved Type Reset 23 22 21 20 19 18 17 16 Reserved Type Reset 15 14 13 12 11 10 9 8 Reserved COM11EN COM10EN COM9EN COM8EN Type Reset RW 0 RW 0 RW 0 RW 0 7 6 5 4 3 2 1 0 COM7EN COM6EN COM5EN COM4EN COM3EN COM2EN COM1EN COM0EN Type Reset RW 0 RW 0 R...

Page 542: ... 17 16 SEG7POL SEG6POL SEG5POL SEG4POL SEG3POL SEG2POL SEG1POL SEG0POL Type Reset RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 15 14 13 12 11 10 9 8 Reserved COM11POL COM10POL COM9POL COM8POL Type Reset RW 0 RW 0 RW 0 RW 0 7 6 5 4 3 2 1 0 COM7POL COM6POL COM5POL COM4POL COM3POL COM2POL COM1POL COM0POL Type Reset RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 Bits Field Descriptions 23 16 SEGxPOL SEGx Output P...

Page 543: ...ter LEDIER This register is used to control the frame interrupt enable Offset 0x00C Reset value 0x0000_0000 31 30 29 28 27 26 25 24 Reserved Type Reset 23 22 21 20 19 18 17 16 Reserved Type Reset 15 14 13 12 11 10 9 8 Reserved Type Reset 7 6 5 4 3 2 1 0 Reserved FIEN Type Reset RW 0 Bits Field Descriptions 0 FIEN Frame Interrupt Enable 0 Disable 1 Enable ...

Page 544: ...frame interrupt flag Offset 0x010 Reset value 0x0000_0000 31 30 29 28 27 26 25 24 Reserved Type Reset 23 22 21 20 19 18 17 16 Reserved Type Reset 15 14 13 12 11 10 9 8 Reserved Type Reset 7 6 5 4 3 2 1 0 Reserved FIF Type Reset WC 0 Bits Field Descriptions 0 FIF Frame interrupt flag 0 No frame interrupt occurs 1 Frame interrupt occurs Set by hardware and reset by software writing 1 ...

Page 545: ...0000 0 CK_LED clock 000001 1 CK_LED clock 000010 2 CK_LED clocks 000011 3 CK_LED clocks 111111 63 CK_LED clocks COM duty clock number Duty clock number Dead time clock number The dead time clock number should be less than duty clock number The maximum clock number of the dead time varies and is dependent upon the duty clock number If DTYNUM bits are set to 00 that is the duty cycle clock is 8 CK_L...

Page 546: ...sented by SEGx and COMy are to be illuminated x 0 7 y n 0 11 offset 0x018 0x044 Reset value 0x0000_0000 31 30 29 28 27 26 25 24 Reserved Type Reset 23 22 21 20 19 18 17 16 Reserved Type Reset 15 14 13 12 11 10 9 8 Reserved Type Reset 7 6 5 4 3 2 1 0 CnS7 CnS6 CnS5 CnS4 CnS3 CnS2 CnS1 CnS0 Type Reset RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 Bits Field Descriptions 7 0 CnSx LED Pixel Data x 0 7 n 0 1...

Page 547: ...ber M0 to M5 For the HT32F54243 HT32F54253 having a module number M0 to M6 Each module is a fully independent set of four Touch Keys and each Touch Key has its own oscillator Function Description When a finger touches or is in proximity to a touch pad the capacitance of the pad will increase By using this capacitance variation to change slightly the frequency of the internal sense oscillator touch...

Page 548: ...key module 16 bit C F counter touch key function 16 bit counter 5 bit time slot unit period counter in all modules will be automatically cleared when the TKST bit is cleared to zero but the 8 bit programmable time slot counter will not be cleared The overflow time is set by users When the TKST bit changes from low to high the 16 bit C F counter touch key function 16 bit counter 5 bit time slot uni...

Page 549: ... oscillator internal capacitor value for the time slot 0 selected key will again be read from the MnKmCPR register Then the 16 bit C F counter value will be written into the relevant location of the time slot 3 scanned key in the TKMnKmCNTR register After all the selected keys are scanned the TKRCOV bit will be set high and the TKBUSY bit will be cleared to zero as well as an auto scan mode operat...

Page 550: ... by hardware Notes 1 When MnTSS 1 0 0 the time slot clock is selected from TKCLK 32 TKCLK 64 or TKCLK 128 the reference oscillator clock does not need to be enabled the MnROEN bit will not be automatically set to high 2 When a specific module is enabled its corresponding oscillator is automatically enabled the MnROEN is automatically set high by the hardware Since the module 0 reference clock is a...

Page 551: ...ion Flowchart Start Write Ref OSC Capacitor value to TKMnROCPR Touch Key Manual Scan Operation Start Set Start bit TKST 0 1 Busy flag TKBUSY 1 All Time Slot Counter overflow TKRCOV 0 Initiate Time Slot 16 bit C F Counter All Time Slot 16 bit C F Counter start to count Time Slot 16 bit C F Counter keep counting TKRCOV 1 Touch key busy flag TKBUSY 0 Generate Interrupt request flag Read C F counter v...

Page 552: ... Time Slot 16 bit C F Counter All Time Slot counter 16 bit C F counter start to count Time Slot 16 bit C F Counter keep counting Yes TKRCOV 1 Generate Interrupt request flag Read C F counter value from the TKMn16D_Km bit field Touch key scan end Set TKST 1 0 End Load Ref OSC internal Capacitor value from the TKMnRO_Km bit field Store C F counter value to the TKMn16D_Km bit field All key scan finis...

Page 553: ...1 0 by software End Load Ref OSC internal Capacitor value from the TKMnRO_Km bit filed Store C F counter value to the TKMn16D_Km bit filed Touch key busy flag TKBUSY 0 16 bit C F counter threshold Value Yes All module scan finish MCU Hold Optional TKTH 1 Last scan in PST cycle No Yes Change next key Scan triger period Yes TKRCOV 1 No No Yes No For Time Slot Yes Last scan in PST cycle No Read C F c...

Page 554: ...eference Oscillator Capacitor Register 0x0000_0000 TKMnK3CPR 0x100 n 1 0x010 Touch Key Module n Key 3 Capacitor Register 0x0000_0000 TKMnK2CPR 0x100 n 1 0x014 Touch Key Module n Key 2 Capacitor Register 0x0000_0000 TKMnK1CPR 0x100 n 1 0x018 Touch Key Module n Key 1 Capacitor Register 0x0000_0000 TKMnK0CPR 0x100 n 1 0x01C Touch Key Module n Key 0 Capacitor Register 0x0000_0000 TKMnCFCNTR 0x100 n 1 ...

Page 555: ...Key Clock Source Selection 0 PCLK 1 32 kHz from LSI 15 13 RODLY Reference Oscillator Stable Delay Time Adjust for Touch Key 000 4 Reference oscillator clock default 001 2 Reference oscillator clock 010 4 Reference oscillator clock 011 8 Reference oscillator clock 100 16 Reference oscillator clock 101 32 Reference oscillator clock 110 64 Reference oscillator clock 111 4 Reference oscillator clock 1...

Page 556: ... TASMTO TKEY 1 Note A Periodic scan timer time out cycle scans N times N TASMTO TKEY 1 Default Scan as follows 00 TASMTO 2 N 2 1 01 TASMTO 4 N 4 1 10 TASMTO 8 N 8 1 11 TASMTO 16 N 16 1 If ASMTO 2 0 b010 Periodic scan timer time out period TASMTO 215 fLIRC fLIRC 32 kHz TASMTO 1 024 s These bits are used to determine the touch key scan period and only available when the touch key function is configu...

Page 557: ...ion will be implemented automatically on a periodic basis which can be determined by the ASMP1 ASMP0 bits in the TKCR register Only at the end of the last scan operation in the Periodic auto scan mode time out cycle TASMTO the 16 bit C F counter content for all scanned keys will be written into the corresponding TKMnKCFGR In addition when any key C F counter value is less than the lower threshold ...

Page 558: ... 0 TK16D Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 Bits Field Descriptions 15 0 TK16D Touch Key 16 bit Counter Value This 16 bit counter can be used to calibrate the reference or key oscillator frequency When the touch key time slot counter overflows in the manual scan mode this 16 bit counter will be stopped and the counter content will be unchanged However this 16 bit counter content wi...

Page 559: ...30 29 28 27 26 25 24 Reserved Type Reset 23 22 21 20 19 18 17 16 Reserved Type Reset 15 14 13 12 11 10 9 8 Reserved Type Reset 7 6 5 4 3 2 1 0 TKTMR Type Reset RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 Bits Field Descriptions 7 0 TKTMR 8 bit Time Slot Counter Reload Value The touch key time slot counter reload register is used to determine the touch key time slot overflow time Time slot counter over...

Page 560: ...KRCOVE TKTHE Type Reset RW 0 RW 0 RW 0 RW 0 Bits Field Descriptions 3 TKRCOVWUEN Time Slot Counter Overflow Interrupt Wake up Function Control 0 Disable 1 Enable If the TKRCOVWUEN is high the device can be woken up from deep sleep modes when the time slot counter overflow interrupt occurs 2 TKTHWUEN Touch Key Threshold Match Interrupt Wake up Function Control 0 Disable 1 Enable If the TKTHWUEN is ...

Page 561: ...ng the Touch Key scan processing In the manual scan mode this bit is cleared to 0 automatically when when all module time slot counters is overflow In the auto scan mode this bit is cleared to 0 automatically when the touch key scan operation is completed In the periodic auto scan mode this bit is cleared to 0 automatically when the last scan operation in the Periodic auto scan mode time out cycle...

Page 562: ...ally cleared but the 8 bit time slot counter will be reloaded from the 8 bit time slot counter preload register When the touch key auto scan operation is completed the TKRCOV bit and the Touch Key TKRCOV Interrupt request flag TKRCOVF will be set and all modules key and reference oscillators will automatically stop All touch key modules 16 bit C F counter touch key function 16 bit counter 5 bit ti...

Page 563: ...rol 0 Disable 1 Enable In the manual scan mode this bit is used to enable disable the touch key module n reference oscillator The MnROEN bit is set by software and is unaffected by the TKST bit setting If the module n reference oscillator is enabled it will be disabled automatically when the TKBUSY bit is changed from high to low In the auto scan mode or the periodic auto scan mode this bit is con...

Page 564: ...w the MnKOEN bit will automatically be cleared to zero to disable the key oscillator 5 MnDFEN Touch Key Module n Multi frequency Control 0 Disable 1 Enable 3 MnSOFC Touch Key Module n C F Oscillator Frequency Hopping Function Control Selection 0 The frequency hopping function is controlled by MnSOF bit field 1 The frequency hopping function is controlled by hardware regardless of the MnSOF bit fie...

Page 565: ...h Key Module n Time Slot 3 key Scan Selection 00 Key 0 01 Key 1 10 Key 2 11 Key 3 These bits are used to select the desired scan key in time slot 3 in the auto scan mode or the periodic auto scan mode The settings for these bits are invalid when the TKMOD bit field is b01 21 20 MnSK2 Touch Key Module n Time Slot 2 Key Scan Selection 00 Key 0 01 Key 1 10 Key 2 11 Key 3 These bits are used to select...

Page 566: ...hold comparison 1 Upper threshold comparison 10 MnK2THS Touch Key Module n Key 2 Upper or Lower Threshold Comparison Selection 0 Lower threshold comparison 1 Upper threshold comparison 9 MnK1THS Touch Key Module n Key 1 Upper or Lower Threshold Comparison Selection 0 Lower threshold comparison 1 Upper threshold comparison 8 MnK0THS Touch Key Module n Key 0 Upper or Lower Threshold Comparison Selec...

Page 567: ...than upper threshold 1 Less than lower threshold or larger than upper threshold This bit is cleared to 0 by writing 1 2 MnK2THF Touch Key Module n Key 2 Upper or Lower Threshold Comparison Flag 0 Not less than lower threshold or not larger than upper threshold 1 Less than lower threshold or larger than upper threshold This bit is cleared to 0 by writing 1 1 MnK1THF Touch Key Module n Key 1 Upper o...

Page 568: ...cillator capacitor value Offset 0x100 n 1 0x00C Reset value 0x0000_0000 31 30 29 28 27 26 25 24 Reserved Type Reset 23 22 21 20 19 18 17 16 Reserved Type Reset 15 14 13 12 11 10 9 8 Reserved TKMnRO Type Reset RW 0 RW 0 7 6 5 4 3 2 1 0 TKMnRO Type Reset RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 Bits Field Descriptions 9 0 TKMnRO Touch Key Module n Reference Oscillator Capacitor Value The reference os...

Page 569: ...KMnRO_K3 Type Reset RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 Bits Field Descriptions 9 0 TKMnRO_K3 Touch Key Module n Key 3 Reference Oscillator Capacitor Value Touch Key Module n Key 2 Capacitor Register TKMnK2CPR This register specifies the module n Key 2 reference oscillator capacitor value Offset 0x100 n 1 0x014 Reset value 0x0000_0000 31 30 29 28 27 26 25 24 Reserved Type Reset 23 22 21 20 19 ...

Page 570: ...KMnRO_K1 Type Reset RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 Bits Field Descriptions 9 0 TKMnRO_K1 Touch Key Module n Key 1 Reference Oscillator Capacitor Value Touch Key Module n Key 0 Capacitor Register TKMnK0CPR This register specifies the module n Key 0 reference oscillator capacitor value Offset 0x100 n 1 0x01C Reset value 0x0000_0000 31 30 29 28 27 26 25 24 Reserved Type Reset 23 22 21 20 19 ...

Page 571: ... 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 7 6 5 4 3 2 1 0 TKMn16D Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 Bits Field Descriptions 15 0 TKMn16D Touch Key Module n 16 bit C F Counter Value This 16 bit C F counter will be stopped and the counter content will be kept unchanged when the touch key time slot counter overflows in the manual scan mode However this 16 bit C F counter content will be clear...

Page 572: ...ns 15 0 TKMn16D_K3 Touch Key Module n Key 3 16 bit C F Counter Value The TKMn16D_K3 bit field will be cleared when the corresponding module n Key 3 is disabled Touch Key Module n Key 2 Counter Register TKMnK2CNTR This register contains the touch key module n Key 2 16 bit C F counter value Offset 0x100 n 1 0x028 Reset value 0x0000_0000 31 30 29 28 27 26 25 24 Reserved Type Reset 23 22 21 20 19 18 1...

Page 573: ...ns 15 0 TKMn16D_K1 Touch Key Module n Key 1 16 bit C F Counter Value The TKMn16D_K1 bit field will be cleared when the corresponding module n Key 1 is disabled Touch Key Module n Key 0 Counter Register TKMnK0CNTR This register contains the touch key module n Key 0 16 bit C F counter value Offset 0x100 n 1 0x030 Reset value 0x0000_0000 31 30 29 28 27 26 25 24 Reserved Type Reset 23 22 21 20 19 18 1...

Page 574: ... 0 7 6 5 4 3 2 1 0 TK3MnTH16 Type Reset RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 Bits Field Descriptions 15 0 TK3MnTH16 Touch Key Module n Key 3 Threshold Value Touch Key Module n Key 2 Threshold Register TKMnK2THR This register specifies the touch key module n Key 2 threshold value Offset 0x100 n 1 0x038 Reset value 0x0000_0000 31 30 29 28 27 26 25 24 Reserved Type Reset 23 22 21 20 19 18 17 16 Re...

Page 575: ... 0 7 6 5 4 3 2 1 0 TK1MnTH16 Type Reset RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 Bits Field Descriptions 15 0 TK1MnTH16 Touch Key Module n Key 1 Threshold Value Touch Key Module n Key 0 Threshold Register TKMnK0THR This register specifies the touch key module n Key 0 threshold value Offset 0x100 n 1 0x040 Reset value 0x0000_0000 31 30 29 28 27 26 25 24 Reserved Type Reset 23 22 21 20 19 18 17 16 Re...

Page 576: ...s mentioned herein are used solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable without further modification nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise Holtek s products are not authorized for use as critical components in life support devices ...

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