
Rev. 1.00
354 of 576
January 28, 2022
32-Bit Arm
®
Cortex
®
-M0+ MCU
HT32F54231/HT32F54241/HT32F54243/HT32F54253
15 Motor Control T
imer (MCTM)
Timer Event Generator Register – EVGR
This register contains the software event generation bits.
Offset:
0x078
Reset value: 0x0000_0000
31
30
29
28
27
26
25
24
Reserved
Type/Reset
23
22
21
20
19
18
17
16
Reserved
Type/Reset
15
14
13
12
11
10
9
8
Reserved
BRKG
TEVG
UEV2G
UEV1G
Type/Reset
WO 0 WO 0 WO 0 WO 0
7
6
5
4
3
2
1
0
Reserved
CH3CCG CH2CCG CH1CCG CH0CCG
Type/Reset
WO 0 WO 0 WO 0 WO 0
Bits
Field
Descriptions
[11]
BRKG
Software Break Event Generation
The break event BEV can be generated by setting this bit. It is automatically cleared
by hardware.
0: No action
1: The BRKIF flag is set and then the CHMOE bit will be cleared
[10]
TEVG
Trigger Event Generation
The trigger event TEV can be generated by setting this bit. It is cleared by hardware
automatically.
0: No action
1: The TEVIF flag is set
[9]
UEV2G
Update Event 2 Generation
The update event 2 UEV2 can be generated by setting this bit. It is cleared by
hardware automatically.
0: No action
1: Update the CHxE, CHxNE and CHxOM bits when COMPRE bit in the CTR
register is set to 1
[8]
UEV1G
Update Event 1 Generation
The update event 1 UEV1 can be generated by setting this bit. It is cleared by
hardware automatically.
0: No action
1: Reinitialise the counter
The counter value returns to 0 or the CRR preload value, depending on the
counter mode in which the current timer is being used. An update operation on any
related registers will also be executed. For a more detailed description, refer to the
corresponding section.