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Rev. 1.00
370 of 576
January 28, 2022
32-Bit Arm
®
Cortex
®
-M0+ MCU
HT32F54231/HT32F54241/HT32F54243/HT32F54253
16 Single-Channel T
imer (SCTM)
Slave Controller
The SCTM can be synchronized with an external trigger in several modes including the Restart
mode, the Pause mode and the Trigger mode which is selected by the SMSEL field in the MDCFR
register. The trigger input of these modes comes from the STI signal which is selected by the
TRSEL field in the TRCFR register. The operation modes in the Slave Controller are described in
the accompanying sections.
Trigger Controller
STI
Trigger Event
Slave
Controller
Reset/Stop/Start Counter
SMSEL
Restart/Pause/Trigger Mode
Figure 120. Slave Controller Diagram
Restart Mode
The counter and its prescaler can be reinitialized in response to a rising edge of the STI signal.
When an STI rising edge occurs, the update event software generation bit named UEVG will
automatically be asserted by hardware and the trigger event flag will also be set. Then the counter
and prescaler will be reinitialized. Although the UEVG bit is set to 1 by hardware, the update event
does not really occur. It depends upon whether the update event disable control bit UEVDIS is set
to 1 or not. If the UEVDIS is set to 1 to disable the update event to occur, there will no update event
be generated, however the counter and prescaler are still reinitialized when the STI rising edge
occurs. If the UEVDIS bit in the CNTCFR register is cleared to enable the update event to occur,
an update event will be generated together with the STI rising edge, then all the preloaded registers
will be updated.
CK_CNT
STI
UEVG bit
(reset counter)
27
CNTR
(Up-counting)
28
29
30
31
0
1
2
TEVIF
Trigger Event
Timer Counter Reload Register CRR = 32
STI source signal
(polarity=0)
STI source signal
(polarity=1)
Sync.
Figure 121. SCTM in Restart Mode