Hitachi 41
Table 2.18
Operation Code Map (cont)
Instruction Code
Fx: 0000
Fx: 0001
Fx: 0010
Fx: 0011–1111
MSB
LSB MD: 00
MD: 01
MD: 10
MD: 11
0100 Rn
Fx
0001
SHLR Rn
CMP/PZ Rn
SHAR Rn
0100 Rn
Fx
0010
STS.L MACH,
@–Rn
STS.L MACL,
@–Rn
STS.L PR,
@–Rn
0100 Rn
Fx
0011
STC.L
SR,@–Rn
STC.L
GBR,@–Rn
STC.L
VBR,@–Rn
0100 Rn
Fx
0100
ROTL Rn
ROTCL Rn
0100 Rn
Fx
0101
ROTR Rn
CMP/PL Rn
ROTCR Rn
0100 Rm
Fx
0110
LDS.L
@Rm+,MACH
LDS.L
@Rm+,MACL
LDS.L
@Rm+,PR
0100 Rm
Fx
0111
LDC.L
@Rm+,SR
LDC.L
@Rm+,GBR
LDC.L
@Rm+,VBR
0100 Rn
Fx
1000
SHLL2 Rn
SHLL8 Rn
SHLL16 Rn
0100 Rn
Fx
1001
SHLR2 Rn
SHLR8 Rn
SHLR16 Rn
0100 Rm
Fx
1010
LDS Rm,MACH
LDS Rm,MACL
LDS Rm,PR
0100 Rn
Fx
1011
JSR @Rn
TAS.B @Rn
JMP @Rn
0100 Rm
Fx
1100
0100 Rm
Fx
1101
0100 Rn
Fx
1110
LDC Rm,Sr
LDC Rm,GBR
LDC Rm,VBR
0100 Rn
Rm
1111
MAC.W @Rm+,@Rn+
0101 Rn
Rm
disp
MOV.L @(disp:4,Rm),Rn
0110 Rn
Rm
00MD
MOV.B @Rm,Rn
MOV.W @Rm,Rn
MOV.L @Rm,Rn
MOV Rm,Rn
0110 Rn
Rm
01MD
MOV.B @Rm+,Rn MOV.W @Rm+,Rn MOV.L @Rm+,Rn NOT Rm,Rn
0110 Rn
Rm
10MD
SWAP.B Rm,Rn
SWAP.W Rm,Rn
NEGC Rm,Rn
NEG Rm,Rn
0110 Rn
Rm
11MD
EXTU.B Rm,Rn
EXTU.W Rm,Rn
EXTS.B Rm,Rn
EXTS.W Rm,Rn
0111 Rn
imm
ADD #imm:8,Rn
1000 00MD Rn
disp
MOV.B R0,
@(disp:4,Rn)
MOV.W R0,
@(disp:4,Rn)
1000 01MD Rm
disp
MOV.B
@(disp:4,
Rm),R0
MOV.W
@(disp:4,
Rm),R0
Summary of Contents for SH7095
Page 1: ...SH7095 Hardware User Manual ...
Page 23: ...12 Hitachi ...
Page 63: ...52 Hitachi ...
Page 77: ...66 Hitachi ...
Page 105: ...94 Hitachi Figure 5 14 Pipeline Operation when Interrupts are Enabled by Changing the SR ...
Page 127: ...116 Hitachi ...
Page 152: ...Hitachi 141 Figure 7 8 Example of 32 Bit Data Width SRAM Connection ...
Page 157: ...146 Hitachi Figure 7 13 Synchronous DRAM 32 bit Device Connection ...
Page 161: ...150 Hitachi Figure 7 15 Basic Burst Read Timing Auto Precharge ...
Page 167: ...156 Hitachi Figure 7 20 Burst Read Timing Bank Active Same Row Address ...
Page 168: ...Hitachi 157 Figure 7 21 Burst Read Timing Bank Active Different Row Addresses ...
Page 169: ...158 Hitachi Figure 7 22 Write Timing No Precharge ...
Page 170: ...Hitachi 159 Figure 7 23 Write Timing Bank Active Same Row Address ...
Page 180: ...Hitachi 169 Figure 7 29 Example of a DRAM Connection 32 Bit Data Width ...
Page 190: ...Hitachi 179 Figure 7 36 Example of Pseudo SRAM Connection 1 M pseudo SRAM ...
Page 191: ...180 Hitachi Figure 7 37 Example of Pseudo SRAM Connection 4 M pseudo SRAM ...
Page 209: ...198 Hitachi Figure 7 50 Master and Partial Share Master Connections ...
Page 231: ...220 Hitachi ...
Page 287: ...276 Hitachi ...
Page 307: ...296 Hitachi Note For a CPU writing H AA55 to FRC Figure 11 2 FRC Access Operation Write ...
Page 308: ...Hitachi 297 Note For an FRC reading from a CPU H AA55 Figure 11 3 FRC Access Operation Read ...
Page 333: ...322 Hitachi ...
Page 370: ...Hitachi 359 Figure 13 12 Sample Flowchart for Receiving Multiprocessor Serial Data ...
Page 371: ...360 Hitachi Figure 13 12 Sample Flowchart for Receiving Multiprocessor Serial Data cont ...
Page 395: ...384 Hitachi ...
Page 402: ...Hitachi 391 Figure 15 6 PLL Synchronization Settling Timing ...
Page 408: ...Hitachi 397 Figure 15 13 Bus Release Timing Slave Mode With PLL1 Off ...
Page 436: ...Hitachi 425 Figure 15 33 Synchronous DRAM Mode Register Write Cycle TRP 1 Cycle ...
Page 437: ...426 Hitachi Figure 15 34 Synchronous DRAM Mode Register Write Cycle TRP 2 Cycles ...
Page 449: ...438 Hitachi Figure 15 46 DRAM CAS Before RAS Refresh Cycle TRP 1 Cycle TRAS 2 Cycles PLL On ...
Page 454: ...Hitachi 443 Figure 15 51 DRAM CAS Before RAS Refresh Cycle TRP 1 Cycle TRAS 2 Cycles PLL Off ...
Page 461: ...450 Hitachi Figure 15 58 Pseudo SRAM Auto Refresh Cycle PLL On TRP 1 Cycle TRAS 2 Cycles ...
Page 462: ...Hitachi 451 Figure 15 59 Pseudo SRAM Self Refresh Cycle PLL On TRP 1 Cycle TRAS 2 Cycles ...
Page 467: ...456 Hitachi Figure 15 64 Pseudo SRAM Auto Refresh Cycle PLL Off TRP 1 Cycle TRAS 2 Cycles ...
Page 468: ...Hitachi 457 Figure 15 65 Pseudo SRAM Self Refresh Cycle PLL Off TRP 1 Cycle TRAS 2 Cycles ...
Page 471: ...460 Hitachi Figure 15 68 Interrupt Vector Fetch Cycle PLL On No Waits ...
Page 472: ...Hitachi 461 Figure 15 69 Interrupt Vector Fetch Cycle PLL Off No Waits ...
Page 473: ...462 Hitachi Figure 15 70 Interrupt Vector Fetch Cycle 1 External Wait Cycle ...
Page 474: ...Hitachi 463 Figure 15 71 Address Monitor Cycle ...
Page 490: ...Hitachi 479 B 2 Register Chart ...