110 Hitachi
Table 6.3
Data Access Cycle Addresses and Operand Size Comparison Conditions
Access Size
Address Compared
Longword
Compare break address register bits 31–2 to address bus bits 31–2
Word
Compare break address register bits 31–1 to address bus bits 31–1
Byte
Compare break address register bits 31–0 to address bus bits 31–0
3.
When the data value is included in the break conditions on B channel:
When the data value is included in the break conditions, specify either longword. word or byte
as the operand size of the break bus cycle registers (BBRA, BBRB). When data values are
included in break conditions, a break interrupt is generated when the address conditions and
data conditions both match. To specify byte data for this case, set the same data in the two
bytes at bits 15–8 and bits 7–0 of the break data register B (BDRB) and break data mask
register B (BDMRB). When word or byte is set, bits 31–16 of BDRB and BDMRB are
ignored.
6.3.4
Break on External Bus Cycle
1.
Enable the external bus break enable bit (the EBBE bit of the BRCR) to generate a break for
the bus cycle generated by the external bus master when the bus is released. This can be done
with all masters and all slaves.
2.
Address and read/write can be set for external buses, but size cannot be specified. Setting
sizes of byte/word/longword will be ignored. Also, no distinction can be made between
instruction fetch and data access for external bus cycles. All cycles are considered data access
cycles, so set 1 in bits IDA1 and IDB1 in BBRA and BBRB.
3.
External input of addresses uses A26–A0, so set bits 31–27 of the break address registers
(BARA, BARB) to 0, or set bits 31–27 of the break address mask registers (BAMRA,
BAMRB) to 1 to mask the addresses not input.
4.
When the conditions set for the external bus cycle are satisfied, the CMFPA and CMFPB bits
are set for the respective channels.
6.3.5
Program Counter (PC) Values Saved
1.
Break on Instruction Fetch (Before Execution): The program counter (PC) value saved to the
stack in user break interrupt exception processing is the address that matches the break
condition. The user break interrupt is generated before the fetched instruction is executed. If a
break condition is set on an instruction that follows an interrupt-disabled instruction, however,
the break occurs before the execution of instruction that accepts the next interrupt is executed,
so the PC value saved is the address of the break.
2.
Break on Instruction Fetch (After Execution): The program counter (PC) value saved to the
stack in user break interrupt exception processing is the address executed after the one that
matches the break condition. The fetched instruction is executed and the user break interrupt
Summary of Contents for SH7095
Page 1: ...SH7095 Hardware User Manual ...
Page 23: ...12 Hitachi ...
Page 63: ...52 Hitachi ...
Page 77: ...66 Hitachi ...
Page 105: ...94 Hitachi Figure 5 14 Pipeline Operation when Interrupts are Enabled by Changing the SR ...
Page 127: ...116 Hitachi ...
Page 152: ...Hitachi 141 Figure 7 8 Example of 32 Bit Data Width SRAM Connection ...
Page 157: ...146 Hitachi Figure 7 13 Synchronous DRAM 32 bit Device Connection ...
Page 161: ...150 Hitachi Figure 7 15 Basic Burst Read Timing Auto Precharge ...
Page 167: ...156 Hitachi Figure 7 20 Burst Read Timing Bank Active Same Row Address ...
Page 168: ...Hitachi 157 Figure 7 21 Burst Read Timing Bank Active Different Row Addresses ...
Page 169: ...158 Hitachi Figure 7 22 Write Timing No Precharge ...
Page 170: ...Hitachi 159 Figure 7 23 Write Timing Bank Active Same Row Address ...
Page 180: ...Hitachi 169 Figure 7 29 Example of a DRAM Connection 32 Bit Data Width ...
Page 190: ...Hitachi 179 Figure 7 36 Example of Pseudo SRAM Connection 1 M pseudo SRAM ...
Page 191: ...180 Hitachi Figure 7 37 Example of Pseudo SRAM Connection 4 M pseudo SRAM ...
Page 209: ...198 Hitachi Figure 7 50 Master and Partial Share Master Connections ...
Page 231: ...220 Hitachi ...
Page 287: ...276 Hitachi ...
Page 307: ...296 Hitachi Note For a CPU writing H AA55 to FRC Figure 11 2 FRC Access Operation Write ...
Page 308: ...Hitachi 297 Note For an FRC reading from a CPU H AA55 Figure 11 3 FRC Access Operation Read ...
Page 333: ...322 Hitachi ...
Page 370: ...Hitachi 359 Figure 13 12 Sample Flowchart for Receiving Multiprocessor Serial Data ...
Page 371: ...360 Hitachi Figure 13 12 Sample Flowchart for Receiving Multiprocessor Serial Data cont ...
Page 395: ...384 Hitachi ...
Page 402: ...Hitachi 391 Figure 15 6 PLL Synchronization Settling Timing ...
Page 408: ...Hitachi 397 Figure 15 13 Bus Release Timing Slave Mode With PLL1 Off ...
Page 436: ...Hitachi 425 Figure 15 33 Synchronous DRAM Mode Register Write Cycle TRP 1 Cycle ...
Page 437: ...426 Hitachi Figure 15 34 Synchronous DRAM Mode Register Write Cycle TRP 2 Cycles ...
Page 449: ...438 Hitachi Figure 15 46 DRAM CAS Before RAS Refresh Cycle TRP 1 Cycle TRAS 2 Cycles PLL On ...
Page 454: ...Hitachi 443 Figure 15 51 DRAM CAS Before RAS Refresh Cycle TRP 1 Cycle TRAS 2 Cycles PLL Off ...
Page 461: ...450 Hitachi Figure 15 58 Pseudo SRAM Auto Refresh Cycle PLL On TRP 1 Cycle TRAS 2 Cycles ...
Page 462: ...Hitachi 451 Figure 15 59 Pseudo SRAM Self Refresh Cycle PLL On TRP 1 Cycle TRAS 2 Cycles ...
Page 467: ...456 Hitachi Figure 15 64 Pseudo SRAM Auto Refresh Cycle PLL Off TRP 1 Cycle TRAS 2 Cycles ...
Page 468: ...Hitachi 457 Figure 15 65 Pseudo SRAM Self Refresh Cycle PLL Off TRP 1 Cycle TRAS 2 Cycles ...
Page 471: ...460 Hitachi Figure 15 68 Interrupt Vector Fetch Cycle PLL On No Waits ...
Page 472: ...Hitachi 461 Figure 15 69 Interrupt Vector Fetch Cycle PLL Off No Waits ...
Page 473: ...462 Hitachi Figure 15 70 Interrupt Vector Fetch Cycle 1 External Wait Cycle ...
Page 474: ...Hitachi 463 Figure 15 71 Address Monitor Cycle ...
Page 490: ...Hitachi 479 B 2 Register Chart ...