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an AC operating margin is assured. When the master side synchronous DRAM is read from the
partial-share master, however, address and control line output requires an extra cycle, and input of
read data requires an extra cycle. The CAS latency setting within the bus controller should be 2
higher than the actual synchronous DRAM CAS latency. If the clock cycle is long and is
sufficiently long relative to the time for addresses, control signals and write signals from the
partial-share master to reach the synchronous DRAM on the master side through the buffer and to
the time for read data from the synchronous DRAM on the master side to reach the partial-share
master through the buffer, if the respective setup time limits can be satisfied, then there is no need
to delay by one cycle clock signal synchronously with the clock. In this case, the previously
described latch is not needed.

When a processor in the partial-share master mode accesses the CS2 space, it performs the
following procedure. The BREQ signal is asserted at the clock fall to request the bus from the
master. The BACK signal is sampled at every clock fall, and when an assertion is received, the
access cycle starts at the next clock rise. After the access ends, BREQ is negated at the clock fall.
Control of the buffer when a CS2 space device is being accessed from the partial-share master
references the BREQ and BACK signals. Notification that the bus is enabled for use is conducted
by the BACK connected to the partial-share master, but the BACK signal may be negated while
the bus is in use when the master requires the bus back to service a refresh or the like. For this
reason, the BREQ signal must be monitored to see whether the partial-share master can continue
using the bus after the BACK is asserted. For address buffers, after the address buffer is turned on
by the detection of a BACK assertion, the buffer remains on until the BREQ is negated. When
BREQ is negated, the buffer goes off. When the buffer is slow going off and it conflicts with the
start of the access cycle at the master, the BREQ signal output from the partial-share master as part
of the buffer control circuit must be delayed a clock and input to the BRLS signal.

When the bus is released after the CS2 space is accessed in the partial-share master mode, the bus
will be released after waiting the time required for auto precharge if the CS2 space was
synchronous DRAM. Other spaces always have the bus themselves, so there is no precharge of
CS3 space memory upon release after a CS2 space bus request, even when DRAM, synchronous
DRAM or pseudo SRAM is connected to the CS3 space. Partial-share master mode does not
refresh CS2 (it is ignored).

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Summary of Contents for SH7095

Page 1: ...SH7095 Hardware User Manual ...

Page 2: ...ate the characteristics and performance of Hitachi s semiconductor products Hitachi assumes no responsibility for any intellectual property claims or other problems that may result from applications based on the examples described herein 5 No license is granted by implication or otherwise under any patents or other rights of any third party or Hitachi Ltd 6 MEDICAL APPLICATIONS Hitachi s products ...

Page 3: ...n Memory 16 2 2 3 Immediate Data Format 17 2 3 Instruction Features 17 2 3 1 RISC Type Instruction Set 17 2 3 2 Addressing Modes 20 2 3 3 Instruction Format 23 2 4 Instruction Set 27 2 4 1 Instruction Set by Classification 27 2 4 2 Operation Code Map 40 2 5 Processing States 42 2 5 1 State Transitions 42 2 5 2 Power Down State 44 Section 3 Operating Mode 47 3 1 Operating Mode of the On chip Clock ...

Page 4: ...es are Not Accepted 63 4 6 1 Immediately after a Delay Branch Instruction 64 4 6 2 Immediately after an Interrupt Disabled Instruction 64 4 7 Stack Status after Exception Processing Ends 64 4 8 Notes on Use 65 4 8 1 Value of Stack Pointer SP 65 4 8 2 Value of Vector Base Register VBR 65 4 8 3 Address Errors Caused by Stacking of Address Error Exception Processing 65 4 8 4 Accessing Registers durin...

Page 5: ... 1 3 Register Configuration 97 6 2 Register Descriptions 98 6 2 1 Break Address Register A BARA 98 6 2 2 Break Address Mask Register A BAMRA 99 6 2 3 Break Bus Cycle Register A BBRA 100 6 2 4 Break Address Register B BARB 102 6 2 5 Break Address Mask Register B BAMRB 102 6 2 6 Break Data Register B BDRB 102 6 2 7 Break Data Mask Register B BDMRB 103 6 2 8 Bus Break Register B BBRB 104 6 2 9 Break ...

Page 6: ...Ordinary Space 139 7 4 1 Basic Timing 139 7 4 2 Wait State Control 143 7 5 Synchronous DRAM Interface 145 7 5 1 Synchronous DRAM Direct Connection 145 7 5 2 Address Multiplex 147 7 5 3 Burst Read 148 7 5 4 Single Read 151 7 5 5 Write 152 7 5 6 Bank Active 154 7 5 7 Refreshes 160 7 5 8 Power On Sequence 163 7 5 9 Phase Shift by PLL 165 7 6 DRAM Interface 168 7 6 1 DRAM Direct Connection 168 7 6 2 A...

Page 7: ...210 8 4 4 The TAS Instruction 211 8 4 5 Pseudo LRU and Cache Replacement 211 8 4 6 Cache Initialization 213 8 4 7 Associative Purges 213 8 4 8 Data Array Access 214 8 4 9 Address Array Access 214 8 5 Cache Use 215 8 5 1 Initialization 215 8 5 2 Purge of Specific Lines 216 8 5 3 Cache Data Coherency 217 8 5 4 Two Way Cache Mode 218 8 5 5 Usage Notes 218 Section 9 Direct Memory Access Controller DMA...

Page 8: ...Between On Chip SCI and External Memory 274 9 5 Notes 274 Section 10 Division Unit 277 10 1 Overview 277 10 1 1 Features 277 10 1 2 Block Diagram 277 10 1 3 Register Configuration 278 10 2 Description of Registers 279 10 2 1 Divisor Register DVSR 279 10 2 2 Dividend Register L for 32 Bit division DVDNT 279 10 2 3 Division Control Register DVCR 280 10 2 4 Vector Number Setting Register VCRDIV 281 1...

Page 9: ...ag OVF Set Timing 302 11 5 Interrupt Sources 303 11 6 Example of Using the FRT 303 11 7 Notes on Use 304 Section 12 Watchdog Timer WDT 309 12 1 Overview 309 12 1 1 Features 309 12 1 2 Block Diagram 310 12 1 3 Pin Configuration 310 12 1 4 Register Configuration 311 12 2 Register Descriptions 311 12 2 1 Watchdog Timer Counter WTCNT 311 12 2 2 Watchdog Timer Control Status Register WTCSR 312 12 2 3 R...

Page 10: ...tion 341 13 3 1 Overview 341 13 3 2 Operation in Asynchronous Mode 344 13 3 3 Multiprocessor Communication 354 13 3 4 Clocked Synchronous Operation 362 13 4 SCI Interrupt Sources and the DMAC 371 13 5 Notes on Use 371 Section 14 Power Down Modes 375 14 1 Overview 375 14 1 1 Power Down Modes 375 14 1 2 Register 376 14 2 Description of Register 377 14 2 1 Standby Control Register SBYCR 377 14 3 Slee...

Page 11: ...ming 388 15 3 2 Control Signal Timing 392 15 3 3 Bus Timing 398 15 3 4 DMAC Timing 464 15 3 5 Free Running Timer Timing 465 15 3 6 Watchdog Timer Timing 466 15 3 7 Serial Communications Interface Timing 467 15 3 8 AC Characteristics Measurement Conditions 468 Appendix A Pin States 469 Appendix B List of Register 471 B 1 List of I O Register 471 B 2 Register Chart 479 Appendix C External Dimensions...

Page 12: ...M and pseudo SRAM As a result the high speed CPU and various peripheral functions enable designers to construct high performance systems with advanced functionality at low cost even in applications such as real time control that require very high speeds impossible with conventional microprocessors 1 1 1 Features of the SH7095 CPU Original Hitachi architecture 32 bit internal data paths General reg...

Page 13: ...ode Standby mode Module stop mode Interrupt Five external interrupt pins NMI IRL0 to IRL3 and IRL0 to IRL3 pins set 15 controller INTC external interrupt levels Eleven internal interrupt sources DMAC 2 DIVU 1 FRT 3 WDT 1 SCI 4 REF 1 Sixteen programmable priority levels Vector numbers settable in every internal interrupt source Auto vector or external vector selectable as external interrupt vector ...

Page 14: ...DRAM synchronous DRAM and pseudo SRAM areas Tp cycles can be generated to assure RAS precharge time Address multiplexing is supported internally so DRAM and synchronous DRAM can be connected directly Outputs chip select signals CS0 to CS3 for each area DRAM synchronous DRAM pseudo SRAM refresh function controller BSC Programmable refresh interval Supports CAS before RAS refresh and self refresh mo...

Page 15: ...ing Timer FRT 1 Channel Selects input from three internal external clocks Input capture and output compare Counter overflow compare match and input capture interrupt Watchdog Timer WDT 1 Channel Watchdog timer or interval timer can be switched Count overflow can generate an internal reset external signal or interrupt Power on reset or manual reset can be selected as the internal reset Serial Commu...

Page 16: ...Hitachi 5 1 2 Block Diagram Figure 1 1 is a block diagram of the SH7095 Figure 1 1 Block Diagram ...

Page 17: ...6 Hitachi 1 3 Description of Pins 1 3 1 Pin Arrangement Note Do not connect anything to pins labeled N C Figure 1 2 Pin Arrangement 144 Pin Plastic QFP ...

Page 18: ... Ground 7 D15 I O Data bus 8 D16 I O Data bus 9 D17 I O Data bus 10 D18 I O Data bus 11 D19 I O Data bus 12 VCC I Power 13 D20 I O Data bus 14 VSS I Ground 15 D21 I O Data bus 16 D22 I O Data bus 17 D23 I O Data bus 18 VCC I Power 19 D24 I O Data bus 20 VSS I Ground 21 D25 I O Data bus 22 D26 I O Data bus 23 D27 I O Data bus 24 VCC I Power 25 D28 I O Data bus 26 VSS I Ground 27 D29 I O Data bus 28...

Page 19: ... A8 I O Address bus 40 VCC I Power 41 A9 I O Address bus 42 VSS I Ground 43 A10 I O Address bus 44 A11 I O Address bus 45 A12 I O Address bus 46 A13 I O Address bus 47 A14 I O Address bus 48 VCC I Power 49 A15 I O Address bus 50 VSS I Ground 51 A16 I O Address bus 52 A17 I O Address bus 53 A18 I O Address bus 54 VCC I Power 55 A19 I O Address bus 56 VSS I Ground 57 A20 I O Address bus 58 A21 I O A...

Page 20: ...e start 77 RD WR I O Read write 78 VSS I Ground 79 RAS CE O RAS for DRAM and synchronous DRAM CE for pseudo SRAM 80 CAS OE O CAS for synchronous DRAM OE for pseudo SRAM 81 CASHH DQMUU WE3 O Most significant byte selection signal for memory 82 CASHL DQMUL WE2 O Second byte selection signal for memory 83 CASLH DQMLU WE1 O Third byte selection signal for memory 84 VCC I Power 85 CASLL DQMLL WE0 O Lea...

Page 21: ...ut 102 TxD O Serial data output 103 SCK I O Serial clock input output 104 VCC PLL I Power for on chip PLL 105 MD0 I Operating mode pin 106 VSS PLL I Ground for on chip PLL 107 MD1 I Operating mode pin 108 CAP1 O External capacitance pin for PLL 109 CAP2 O External capacitance pin for PLL 110 MD2 I Operating mode pin 111 CKPACK O Clock pause acknowledge output 112 CKPREQ CKM I Clock pause request i...

Page 22: ...nterrupt source input 127 IRL2 I External interrupt source input 128 IRL1 I External interrupt source input 129 IRL0 I External interrupt source input 130 D0 I O Data bus 131 D1 I O Data bus 132 VCC I Power 133 D2 I O Data bus 134 VSS I Ground 135 D3 I O Data bus 136 D4 I O Data bus 137 D5 I O Data bus 138 D6 I O Data bus 139 VCC I Power 140 D7 I O Data bus 141 VSS I Ground 142 D8 I O Data bus 143...

Page 23: ...12 Hitachi ...

Page 24: ...eral instructions use R0 as a fixed source or destination register R15 is used as the hardware stack pointer SP Saving and recovering the status register SR and program counter PC in exception processing is accomplished by referencing the stack using R15 Notes 1 R0 functions as an index register in the indirect indexed register addressing mode and indirect indexed GBR addressing mode In some instr...

Page 25: ...de to transfer data to the registers of on chip peripheral modules The vector base register functions as the base address of the exception processing vector area including interrupts Figure 2 2 Control Registers 2 1 3 System Registers System registers consist of four 32 bit registers high and low multiply and accumulate registers MACH and MACL the procedure register PR and the program counter PC f...

Page 26: ...Value General registers R0 R14 Undefined R15 SP Value of the stack pointer in the vector address table Control registers SR Bits I3 I0 are 1111 H F reserved bits are 0 and other bits are undefined GBR Undefined VBR H 00000000 System registers MACH MACL PR Undefined PC Value of the program counter in the vector address table 2 2 Data Formats 2 2 1 Data Format in Registers Register operands are alwa...

Page 27: ... access of CSZ space area 2 in little endian format which enables the microprocessor to share memory with processors that access memory in little endian format The microprocessor arranges byte data differently for little endian and the more usual big endian format Figure 2 5 Byte Word and Longword Alignment 2 2 3 Immediate Data Format Byte immediate data resides in an instruction code Immediate da...

Page 28: ...It also is handled as longword data Table 2 2 Sign Extension of Word Data SH7095 Series CPU Description Example of Conventional CPU MOV W disp PC R1 ADD R1 R0 DATA WH 1234 Data is sign extended to 32 bits and R1 becomes H 00001234 It is next operated upon by an ADD instruction ADD W H 1234 R0 Note disp PC accesses the address of the immediate data Load Store Architecture Basic operations are execu...

Page 29: ...TRGET0 when R0 R1 and to TRGET1 when R0 R1 CMP W R1 R0 BGE TRGET0 BLT TRGET1 ADD 1 R0 CMP EQ 0 R0 BT TRGET T bit is not changed by ADD T bit is set when R0 0 The program branches if R0 0 SUB W 1 R0 BEQ TRGET Immediate Data Byte immediate data resides in instruction code Word or longword immediate data is not input via instruction codes but is stored in a memory table An immediate data transfer ins...

Page 30: ...d by 16 bit or 32 bit displacement the pre existing displacement value is placed in the memory table Loading the immediate data when the instruction is executed transfers that value to the register and the data is accessed in the indirect indexed register addressing mode table 2 7 Table 2 7 16 32 Bit Displacement Accessing Classification SH7095 Series CPU Example of Conventional CPU 16 bit displac...

Page 31: ...ffective address is the content of register Rn A constant is added to the content of Rn after the instruction is executed 1 is added for a byte operation 2 for a word operation and 4 for a longword operation Rn After the instruction executes Byte Rn 1 Rn Word Rn 2 Rn Longword Rn 4 Rn Pre decrement indirect register addressing Rn The effective address is the value obtained by subtracting a constant...

Page 32: ...or a longword operation Byte Rn disp Word Rn disp 2 Longword Rn disp 4 Indirect indexed register addressing R0 Rn The effective address is the Rn value plus R0 Rn R0 Indirect GBR addressing with displacement disp 8 GBR The effective address is the GBR value plus an 8 bit displacement disp The value of disp is zero extended and remains the same for a byte opera tion is doubled for a word operation ...

Page 33: ...he same for a byte operation is doubled for a word operation and is quadrupled for a longword operation For a longword operation the lowest two bits of the PC value are masked Word PC disp 2 Longword PC H FFFFFFFC disp 4 PC relative addressing disp 8 The effective address is the PC value sign extended with an 8 bit displacement disp doubled and added to the PC value PC disp 2 disp 12 The effective...

Page 34: ...ructions are zero extended imm 8 The 8 bit immediate data imm for the MOV ADD and CMP EQ instructions are sign extended imm 8 Immediate data imm for the TRAPA instruction is zero extended and is quadrupled 2 3 3 Instruction Format The instruction format table table 2 9 refers to the source operand and the destination operand The meaning of the operand depends on the instruction code The symbols ar...

Page 35: ...ister or system register nnnn Direct registerSTS MACH Rn nnnn Indirect register JMP Rn Control register or system register nnnn Indirect pre decrement register STC L SR Rn nnnn PC relative using Rn BRAF Rn m format mmmm Direct registerControl register or system register LDC Rm SR mmmm Indirect post increment register Control register or system register LDC L Rm SR ...

Page 36: ... mmmm Indirect post increment register nnnn Direct registerMOV L Rm Rn mmmm Direct registernnnn Indirect pre decrement register MOV L Rm Rn mmmm Direct registernnnn Indirect indexed register MOV L Rm R0 Rn md format mmmmdddd indirect register with displacement R0 Direct register MOV B disp Rn R0 nd4 format R0 Direct register nnnndddd Indirect register with displacement MOV B R0 disp Rn nmd format ...

Page 37: ... displacement R0 Direct register MOVA disp PC R0 dddddddd PC relative BF label d12 format dddddddddddd PC relative BRA label label disp PC nd8 format dddddddd PC relative with displacement nnnn Direct registerMOV L disp PC Rn i format iiiiiiii Immediate Indirect indexed GBR AND B imm R0 GBR iiiiiiii Immediate R0 Direct register AND imm R0 iiiiiiii Immediate TRAPA imm ni format iiiiiiii Immediate n...

Page 38: ...nary addition 33 operations ADDC Binary addition with carry ADDV Binary addition with overflow check CMP cond Comparison DIV1 Division DIV0S Initialization of signed division DIV0U Initialization of unsigned division DMULS Signed double length multiplication DMULU Unsigned double length multiplication DT Decrement and test EXTS Sign extension EXTU Zero extension MAC Multiply accumulate double leng...

Page 39: ...ROTCR One bit right rotation with T bit SHAL One bit arithmetic left shift SHAR One bit arithmetic right shift SHLL One bit logical left shift SHLLn n bit logical left shift SHLR One bit logical right shift SHLRn n bit logical right shift Branch 9 BF Conditional branch conditional branch with delay T 0 11 BT Conditional branch conditional branch with delay T 1 BRA Unconditional branch BRAF Uncondi...

Page 40: ...r down state STC Storing control register data STS Storing system register data TRAPA Trap exception handling Total 61 142 Table 2 11 shows the format for instruction codes operation and execution states used in tables 2 12 to 2 17 which list the minimum number of clock cycles required for execution In practice the number of execution cycles increases when the instruction fetch is in contention wi...

Page 41: ...ND of each bit Logical OR of each bit Exclusive OR of each bit Logical NOT of each bit n n n bit shift Execution cycle Value when no wait states are inserted 1 T bit Value of T bit after instruction is executed An em dash in the column means no change Notes 1 Instruction execution cycles The execution cycles shown in the table are minimums The actual number of cycles may be increased when Contenti...

Page 42: ... Rm Rn 1 MOV B Rm Rn 0010nnnnmmmm0100 Rn 1 Rn Rm Rn 1 MOV W Rm Rn 0010nnnnmmmm0101 Rn 2 Rn Rm Rn 1 MOV L Rm Rn 0010nnnnmmmm0110 Rn 4 Rn Rm Rn 1 MOV B Rm Rn 0110nnnnmmmm0100 Rm Sign extension Rn Rm 1 Rm 1 MOV W Rm Rn 0110nnnnmmmm0101 Rm Sign extension Rn Rm 2 Rm 1 MOV L Rm Rn 0110nnnnmmmm0110 Rm Rn Rm 4 Rm 1 MOV B R0 disp Rn 10000000nnnndddd R0 disp Rn 1 MOV W R0 disp Rn 10000001nnnndddd R0 disp 2 ...

Page 43: ...sp GBR 11000001dddddddd R0 disp 2 GBR 1 MOV L R0 disp GBR 11000010dddddddd R0 disp 4 GBR 1 MOV B disp GBR R0 11000100dddddddd disp GBR Sign extension R0 1 MOV W disp GBR R0 11000101dddddddd disp 2 GBR Sign extension R0 1 MOV L disp GBR R0 11000110dddddddd disp 4 GBR R0 1 MOVA disp PC R0 11000111dddddddd disp 4 PC R0 1 MOVT Rn 0000nnnn00101001 T Rn 1 SWAP B Rm Rn 0110nnnnmmmm1000 Rm Swap the bottom...

Page 44: ...m Rn 0011nnnnmmmm0011 If Rn Rm with signed data 1 T 1 Comparison result CMP HI Rm Rn 0011nnnnmmmm0110 If Rn Rm with unsigned data 1 T 1 Comparison result CMP GT Rm Rn 0011nnnnmmmm0111 If Rn Rm with signed data 1 T 1 Comparison result CMP PZ Rn 0100nnnn00010001 If Rn 0 1 T 1 Comparison result CMP PL Rn 0100nnnn00010101 If Rn 0 1 T 1 Comparison result CMP STR Rm Rn 0010nnnnmmmm1100 If Rn and Rm have...

Page 45: ...d Rn 1 EXTU B Rm Rn 0110nnnnmmmm1100 A byte in Rm is zero extended Rn 1 EXTU W Rm Rn 0110nnnnmmmm1101 A word in Rm is zero extended Rn 1 MAC L Rm Rn 0000nnnnmmmm1111 Signed operation of Rn Rm MAC MAC 32 32 64 bit 3 2 to 4 MAC W Rm Rn 0100nnnnmmmm1111 Signed operation of Rn Rm MAC MAC 16 16 64 64 bit 3 2 MUL L Rm Rn 0000nnnnmmmm0111 Rn Rm MACL 32 32 32 bit 2 to 4 MULS W Rm Rn 0010nnnnmmmm1111 Signe...

Page 46: ... Bit AND Rm Rn 0010nnnnmmmm1001 Rn Rm Rn 1 AND imm R0 11001001iiiiiiii R0 imm R0 1 AND B imm R0 GBR 11001101iiiiiiii R0 GBR imm R0 GBR 3 NOT Rm Rn 0110nnnnmmmm0111 Rm Rn 1 OR Rm Rn 0010nnnnmmmm1011 Rn Rm Rn 1 OR imm R0 11001011iiiiiiii R0 imm R0 1 OR B imm R0 GBR 11001111iiiiiiii R0 GBR imm R0 GBR 3 TAS B Rn 0100nnnn00011011 If Rn is 0 1 T 1 MSB of Rn 4 Test result TST Rm Rn 0010nnnnmmmm1000 Rn Rm...

Page 47: ...1 MSB ROTCR Rn 0100nnnn00100101 T Rn T 1 LSB SHAL Rn 0100nnnn00100000 T Rn 0 1 MSB SHAR Rn 0100nnnn00100001 MSB Rn T 1 LSB SHLL Rn 0100nnnn00000000 T Rn 0 1 MSB SHLR Rn 0100nnnn00000001 0 Rn T 1 LSB SHLL2 Rn 0100nnnn00001000 Rn 2 Rn 1 SHLR2 Rn 0100nnnn00001001 Rn 2 Rn 1 SHLL8 Rn 0100nnnn00011000 Rn 8 Rn 1 SHLR8 Rn 0100nnnn00011001 Rn 8 Rn 1 SHLL16 Rn 0100nnnn00101000 Rn 16 Rn 1 SHLR16 Rn 0100nnnn0...

Page 48: ... 2 PC PC if T 0 nop 3 1 BT S label 10001101dddddddd If T 1 disp 2 PC PC if T 0 nop 2 1 BRA label 1010dddddddddddd Delayed branch disp 2 PC PC 2 BRAF Rn 0000nnnn00100011 Delayed branch Rn PC PC 2 BSR label 1011dddddddddddd Delayed branch PC PR disp 2 PC PC 2 BSRF Rn 0000nnnn00000011 Delayed branch PC PR Rn PC PC 2 JMP Rn 0100nnnn00101011 Delayed branch Rn PC 2 JSR Rn 0100nnnn00001011 Delayed branch...

Page 49: ...m SR 0100mmmm00000111 Rm SR Rm 4 Rm 3 LSB LDC L Rm GBR 0100mmmm00010111 Rm GBR Rm 4 Rm 3 LDC L Rm VBR 0100mmmm00100111 Rm VBR Rm 4 Rm 3 LDS Rm MACH 0100mmmm00001010 Rm MACH 1 LDS Rm MACL 0100mmmm00011010 Rm MACL 1 LDS Rm PR 0100mmmm00101010 Rm PR 1 LDS L Rm MACH 0100mmmm00000110 Rm MACH Rm 4 Rm 1 LDS L Rm MACL 0100mmmm00010110 Rm MACL Rm 4 Rm 1 LDS L Rm PR 0100mmmm00100110 Rm PR Rm 4 Rm 1 NOP 0000...

Page 50: ...0010010 Rn 4 Rn MACL Rn 1 STS L PR Rn 0100nnnn00100010 Rn 4 Rn PR Rn 1 TRAPA imm 11000011iiiiiiii PC SR stack area imm PC 8 Note The number of execution states before the chip enters the sleep mode Instruction states The values shown for the execution cycles are minimums The actual number of cycles may be increased when Contention occurs between instruction fetch and data access The destination re...

Page 51: ...T Rn 0000 Rn Fx 1010 STS MACH Rn STS MACL Rn STS PR Rn 0000 Rn Fx 1011 0000 Rn Rm 11MD MOV B R0 Rm Rn MOV W R0 Rm Rn MOV L R0 Rm Rn MAC L Rm Rn 0001 Rn Rm disp MOV L Rm disp 4 Rn 0010 Rn Rm 00MD MOV B Rm Rn MOV W Rm Rn MOV L Rm Rn 0010 Rn Rm 01MD MOV B Rm Rn MOV W Rm Rn MOV L Rm Rn DIV0S Rm Rn 0010 Rn Rm 10MD TST Rm Rn AND Rm Rn XOR Rm Rn OR Rm Rn 0010 Rn Rm 11MD CMP STR Rm Rn XTRCT Rm Rn MULU W R...

Page 52: ...2 Rn SHLL8 Rn SHLL16 Rn 0100 Rn Fx 1001 SHLR2 Rn SHLR8 Rn SHLR16 Rn 0100 Rm Fx 1010 LDS Rm MACH LDS Rm MACL LDS Rm PR 0100 Rn Fx 1011 JSR Rn TAS B Rn JMP Rn 0100 Rm Fx 1100 0100 Rm Fx 1101 0100 Rn Fx 1110 LDC Rm Sr LDC Rm GBR LDC Rm VBR 0100 Rn Rm 1111 MAC W Rm Rn 0101 Rn Rm disp MOV L disp 4 Rm Rn 0110 Rn Rm 00MD MOV B Rm Rn MOV W Rm Rn MOV L Rm Rn MOV Rm Rn 0110 Rn Rm 01MD MOV B Rm Rn MOV W Rm R...

Page 53: ...A imm 8 1100 01MD disp MOV B disp 8 GBR R0 MOV W disp 8 GBR R0 MOV L disp 8 GBR R0 MOVA disp 8 PC R0 1100 10MD imm TST imm 8 R0 AND imm 8 R0 XOR imm 8 R0 OR imm 8 R0 1100 11MD imm TST B imm 8 R0 GBR AND B imm 8 R0 GBR XOR B imm 8 R0 GBR OR B imm 8 R0 GBR 1101 Rn disp MOV L disp 8 PC Rn 1110 Rn imm MOV imm 8 Rn 1111 2 5 Processing States 2 5 1 State Transitions The CPU has five processing states re...

Page 54: ...Transitions between Processing States Reset State The CPU resets in the reset state This occurs when the RES pin level goes low When the NMI pin is high the result is a power on reset when it is low a manual reset will occur ...

Page 55: ...ram execution states the CPU also has a power down state in which CPU operation halts lowering power consumption table 2 19 There are two power down state modes sleep mode and standby mode Sleep Mode When standby bit SBY in the standby control register SBYCR is cleared to 0 and a SLEEP instruction executed the CPU moves from program execution state to sleep mode The on chip peripheral modules othe...

Page 56: ...y control register SBYCR By using this function the power consumption can be reduced The external pins of the on chip peripheral modules in module standby are reset and all registers except DMAC MULT and DIVU are initialized The master enable bit bit 0 of the DMAC s DMAOR register is initialized to 0 Module standby function is cleared by clearing the MSTP4 MSTP0 bits to 0 When MULT has entered the...

Page 57: ...de Execute SLEEP instruction with SBY bit set to 1 in SBYCR Halt Halt Halt and initialize 1 Held Undefine d 1 NMI 2 Power on reset 3 Manual reset Module standby function SH7095 only MSTP4 MSTP0 bits of SBYCR set to 1 Run Run MULT is halted Supply of clock to affected module is halted and module initialized 2 Held Held Clear bits MSTP 4 0 of SBYCR to 0 Notes 1 Differs depending on peripheral module...

Page 58: ...width specification power down mode transition and operation of the on chip cache memory are controlled 3 1 Operating Mode of the On chip Clock Pulse Generator 3 1 1 Clock Pulse Generator The block diagram of the on chip clock pulse generator is shown in figure 3 1 Figure 3 1 Block Diagram of Clock Pulse Generator ...

Page 59: ...mode MD1 I MD2 I CKPREQ CKM I In modes that only use PLL circuit 1 this pin is used as the clock pause request pin CKPACK O Indicates that a clock pause request has been received Note See section 14 4 4 Clock Pause Function for more information PLL Circuit 1 In high speed operation the phase difference between reference clocks and operating clocks in the LSI affects the interface margin with perip...

Page 60: ...it 1 synchronizes the input clocks with internal clocks Mode 5 1 0 1 The CKIO pin inputs clocks having a frequency equivalent to the object operating frequency The PLL circuit 1 shifts the phases of the input clocks and internal clocks by 90 degrees Mode 6 1 1 0 Clocks having a frequency equivalent to that of clocks input from the CKIO pin are used The PLL circuit 1 does not operate When one of cl...

Page 61: ...n combination and functions are listed in table 3 3 Do not switch the MD4 and MD3 pins while they are operating Switching them will cause operating errors Table 3 3 Bus Width of the CS0 Area Pin MD4 MD3 Function 0 0 8 bit bus width is selected 0 1 16 bit bus width is selected 1 0 32 bit bus width is selected 1 1 Illegal setting ...

Page 62: ...g mode is used to switch between master and slave modes See section 7 Bus State Controller for more information about the master and slave modes Table 3 4 Switching between the Master and Slave Modes Pin MD5 Operating Mode Level applied 1 Slave mode 0 Master mode 3 4 Cache Control Register See section 8 Cache ...

Page 63: ...52 Hitachi ...

Page 64: ...ror Interrupt NMI User break IRL IRL1 IRL15 set with IRL3 IRL2 IRL1 IRL0 pins On chip peripheral modules Division unit DIVU Direct memory access controller DMAC Watchdog timer WDT Compare match interrupt part of the bus state controller Serial communications interface SCI 16 bit free running timer FRT Instructions Trap instruction TRAPA General illegal instructions undefined code Illegal slot inst...

Page 65: ...ectly following a delay branch instruction delay slot or of instructions that rewrite the PC When exception processing starts the CPU operates as follows 1 Exception processing triggered by reset The initial values of the program counter PC and stack pointer SP are fetched from the exception processing vector table PC and SP are respectively the H 00000000 and H 00000004 addresses for power on res...

Page 66: ...ts Table 4 4 lists vector table address calculations Table 4 3 Exception Processing Vector Table Exception Sources Vector Numbers Vector Table Address Offset Vector Addresses Power on reset PC 0 H 00000000 H 00000003 Vector number 4 SP 1 H 00000004 H 00000007 Manual reset PC 2 H 00000008 H 0000000B SP 3 H 0000000C H 0000000F General illegal instruction 4 H 00000010 H 00000013 VBR vector Reserved b...

Page 67: ...eral module 3 0 4 255 4 H 00000000 H 00000003 H 000003FC H 000003FF Notes 1 When 1110 is input to the IRL3 IRL2 IRL1 and IRL0 pins an IRL1 interrupt results When 0000 is input an IRL15 interrupt results 2 External vector number fetches can be performed without using the auto vector numbers in this table 3 The vector numbers and vector table address offsets for each on chip peripheral module interr...

Page 68: ...f all on chip peripheral modules except the bus state controller BSC user break controller UBC and frequency changing register are initialized Use the power on reset when turning the power on Table 4 5 Types of Resets Conditions for Transition to Reset Status Internal Status Type NMI Pin RES CPU On Chip Peripheral Module Power on reset High Low Initialize Initialize Manual reset Low Low Initialize...

Page 69: ...manual reset For reliable reset the RES pin should be kept at low for at least 20 clock cycles During manual reset the CPU internal status is initialized Registers of all on chip peripheral modules except the bus state controller BSC user break controller UBC and the frequency changing register are initialized Since the BSC is not affected the DRAM and synchronous DRAM refresh control functions re...

Page 70: ...word data accessed from other than a longword boundary Address error occurs Access of cache purge space address array read write space or on chip I O space by PC relative addressing Address error occurs Access of cache purge space address array read write space data array read write space or on chip I O space by a TAS B instruction Address error occurs Byte data accessed in on chip peripheral modu...

Page 71: ...d the program starts executing from that address The jump that occurs is not a delay branch 4 4 Interrupts 4 4 1 Interrupt Sources Table 4 7 shows the sources that start up interrupt exception processing These are divided into NMI user breaks IRL and on chip peripheral modules Each interrupt source is allocated a different vector number and vector table address offset See section 5 Interrupt Contr...

Page 72: ...ype Priority Level Comment NMI 16 Fixed priority level Cannot be masked User break 15 Fixed priority level IRL 1 15 Set with IRL3 IRL0 pins On chip peripheral module 0 15 Set with interrupt priority level setting registers A and B IPRA and IPRB 4 4 3 Interrupt Exception Processing When an interrupt occurs its priority level is ascertained by the interrupt controller INTC NMI is always accepted but...

Page 73: ...ctions that rewrite the PC JMP JSR BRA BSR RTS RTE BT BF TRAPA BF S BT S BSRF BRAF General illegal instructions Undefined code anywhere besides in a delay slot 4 5 2 Trap Instructions When a TRAPA instruction is executed trap instruction exception processing starts up The CPU operates as follows 1 The status register SR is saved to the stack 2 The program counter PC is saved to the stack The PC va...

Page 74: ...gal Instructions When undefined code placed anywhere other than immediately after a delay branch instruction i e in a delay slot is decoded general illegal instruction exception processing starts up The CPU handles general illegal instructions the same as illegal slot instructions Unlike processing of illegal slot instructions however the program counter value stored is the start address of the un...

Page 75: ... decoded interrupts are not accepted Address errors are accepted 4 7 Stack Status after Exception Processing Ends The status of the stack after exception processing ends is as listed in table 4 11 Table 4 11 Types of Stack Status after Exception Processing Ends Type Stack Status Address error SP Address of instruction after executed instruction 32 bits SR 32 bits Trap instruction SP Address of ins...

Page 76: ...ocessing is ended but address errors will continue to occur To ensure that address error exception processing does not go into an endless loop no address errors are accepted at that point This allows program control to be shifted to the address error exception service routine and enables error processing When an address error occurs during exception processing stacking the stacking bus cycle write...

Page 77: ...66 Hitachi ...

Page 78: ... level registers the priorities of on chip peripheral module interrupts can be set in 16 levels for different request sources Settable vector numbers for on chip peripheral module interrupts two vector number setting registers enable on chip peripheral module interrupt vector numbers to be set with values 0 127 by the interrupt source The IRL interrupt vector number setting method can be selected ...

Page 79: ...t priority level setting DIVU Division unit registers A and B FRT Free running timer VCRWDT Vector number setting register WDT SCI Serial communications interface VCRA D Vector number setting registers A D WDT Watchdog timer SR Status register REF Refresh request within bus state controller Figure 5 1 INTC Block Diagram ...

Page 80: ...errupt acceptance level output pins A3 A0 O When in external vector mode output an interrupt level signal when an IRL interrupt is accepted External vector fetch pins IVECF O Display indicating external vector read cycle External vector number input pins D7 D0 I Input external vector number 5 1 4 Register Configuration The INTC has the eight registers shown in table 5 2 These registers determine v...

Page 81: ... H 0000 See the sections 9 Direct Memory Access Controller and 10 Division Unit for more information on VCRDIV VCRDMA0 and VCRDMA1 5 2 Interrupt Sources There are four types of interrupt sources NMI user breaks IRL and on chip peripheral modules Each interrupt has a priority expressed as a priority level 0 to 16 with 0 the lowest and 16 the highest Giving an interrupt a priority level of 0 masks i...

Page 82: ...IRL priority levels and auto vector numbers When an IRL interrupt is accepted in external vector mode the IRL interrupt level is output from the interrupt acceptance level output pins A3 A0 The external vector fetch pin IVECF is also asserted The external vector number is read from pins D7 D0 at this time Figures 5 2 and 5 3 show interrupt connection examples IRL interrupt exception processing set...

Page 83: ...72 Hitachi Figure 5 2 Example of Connections for External Vector Mode Interrupts Figure 5 3 Example of Connections for Auto Vector Mode Interrupts ...

Page 84: ...errupt fetch cycle for the external vector mode During this cycle CS0 CS3 stay high A26 A4 output undefined values The WAIT pin is sampled but programmable waits are not valid Figure 5 4 External Vector Mode Interrupt Vector Fetch Cycle ...

Page 85: ...le address offsets and interrupt priorities Each interrupt source is allocated a different vector number and vector table address offset Vector table addresses are calculated from vector numbers and address offsets In interrupt exception processing the exception service routine start address is fetched from the vector table indicated by the vector table address See table 4 4 Calculating Exception ...

Page 86: ...nitial Value IPR Bit Numbers Setting Unit Vector No Vector Table Address Default Priority NMI 16 11 VBR vector High User break 15 12 No 4 IRL15 15 71 1 IRL14 14 IRL13 13 70 1 IRL12 12 IRL11 11 69 1 IRL10 10 IRL9 9 68 1 IRL8 8 IRL7 7 67 1 IRL6 6 IRL5 5 66 1 IRL4 4 IRL3 3 65 1 IRL2 2 IRL1 1 64 1 DIVU OVFI 0 15 0 IPRA 15 12 0 127 2 Low ...

Page 87: ...erved 128 255 Low Notes 1 An external vector number fetch can be performed without using the auto vector numbers shown in this table The external vector numbers are 0 127 2 Vector numbers are set in the on chip vector number register 3 REF is the refresh control unit within the bus state controller 5 3 Description of Registers 5 3 1 Interrupt Priority Level Setting Register A IPRA Interrupt priori...

Page 88: ...ur bits so levels 0 15 can be set The same level is set for both DMAC channels When interrupts occur simultaneously channel 0 has priority Bits 7 to 4 Watchdog timer WDT interrupt priority level WDTIP3 WDTIP0 These bits set the watchdog timer WDT interrupt priority level and bus state controller BSC interrupt priority level There are four bits so levels 0 15 can be set When WDT and BSC interrupts ...

Page 89: ...alue should always be 0 Table 5 5 shows the relationship between on chip peripheral module interrupts and interrupt priority level setting registers Table 5 5 Interrupt Request Sources and IPRA IPRB Register Bits 15 to 12 Bits 11 to 8 Bits 7 to 4 Bits 3 to 0 IPRA DIVU DMAC0 DMAC1 WDT Reserved IPRB SCI FRT Reserved Reserved As table 5 5 shows two or three on chip peripheral modules are assigned to ...

Page 90: ...always read 0 The write value should always be 0 Bits 14 to 8 Watchdog timer WDT interval interrupt vector number WITV6 WITV0 These bits set the vector number for the interval interrupt ITI of the watchdog timer WDT There are seven bits so the value can be set between 0 and 127 Bits 6 to 0 Bus state controller BSC compare match interrupt vector number BCMV6 BCMV0 These bits set the vector number f...

Page 91: ...Bits 6 to 0 Serial communication interface SCI receive data full interrupt vector number SRXV6 SRXV0 These bits set the vector number for the serial communication interface SCI receive data full interrupt RXI There are seven bits so the value can be set between 0 and 127 5 3 5 Vector Number Setting Register B VCRB The vector number setting register B VCRB is a 16 bit read write register that sets ...

Page 92: ...re interrupt and output compare interrupt vector numbers 0 127 VCRC is initialized to H 0000 on reset It is not initialized in standby mode Bit 15 14 13 12 11 10 9 8 Bit name FICV6 FICV5 FICV4 FICV3 FICV2 FICV1 FICV0 Initial value 0 0 0 0 0 0 0 0 R W R R W R W R W R W R W R W R W Bit 7 6 5 4 3 2 1 0 Bit name FOCV6 FOCV5 FOCV4 FOCV3 FOCV2 FOCV1 FOCV0 Initial value 0 0 0 0 0 0 0 0 R W R R W R W R W ...

Page 93: ...interrupt OVI There are seven bits so the value can be set between 0 and 127 Tables 5 6 and 5 7 show the relationship between on chip peripheral module interrupts and interrupt vector number setting registers Table 5 6 Interrupt Request Source and Vector Number Setting Registers Bit Register 14 8 6 0 Vector number setting register WDT Interval interrupt WDT Compare match interrupt BSC Vector numbe...

Page 94: ...umber setting register DIV Overflow interrupts for divider unit Vector number setting register DMAC0 Channel 0 transfer end interrupt for DMAC Vector number setting register DMAC1 Channel 1 transfer end interrupt for DMAC 5 3 8 Interrupt Control Register ICR The ICR is a 16 bit register that sets the input signal detection mode of the external interrupt input pin NMI and indicates the input signal...

Page 95: ...or numbers are set to 71 and the IRL1 vector number is set to 64 When the mode is external vector a value between 0 and 127 can be input as the vector number from the external vector number input pins D7 D0 Bit 0 VECMD Description 0 Auto vector mode set internally Initial value 1 External vector mode external input 5 4 Interrupt Operation 5 4 1 Interrupt Sequence The sequence of interrupt operatio...

Page 96: ...m the interrupt controller when it decodes the next instruction to be executed Instead of executing the decoded instruction the CPU starts interrupt exception processing 5 SR and PC are saved onto the stack 6 The priority level of the accepted interrupt is copied to the interrupt mask level bits I3 to I0 in the status register SR 7 When external vector mode is specified for the IRL interrupt the v...

Page 97: ...0 Status register interrupt mask bit Note The vector number is only read from an external source when an external vector number is specified for the IRL interrupt vector number Figure 5 5 Interrupt Sequence Flowchart ...

Page 98: ...n destination instruction Figure 5 6 Stack after Interrupt Exception Processing 5 5 Interrupt Response Time Table 5 8 indicates the interrupt response time which is the time from the occurrence of an interrupt request until interrupt exception processing starts and fetching of the first instruction of the interrupt service routine begins Figure 5 7 shows the pipeline when an IRL interrupt is accep...

Page 99: ... instruction follows however the time may be even longer Time from interrupt exception processing SR and PC saves and vector address fetches until fetch of first instruction of exception service routine starts 5 m1 m2 m3 Interrupt Total 7 m1 m2 m3 10 m1 m2 m3 response Minimum 10 13 Maximum 11 2 m1 m2 m3 m4 14 2 m1 m2 m3 m4 Note m1 m4 are the number of states needed for the following memory accesse...

Page 100: ...e interrupt controller to the CPU as interrupt requests The noise canceler cancels noise that changes in short cycles The CPU samples the interrupt requests between executing instructions During this period the noise canceler output changes according to the level of the noise removed pins so the pin level must be held until the CPU samples This means that interrupt sources must not be cleared insi...

Page 101: ... a module stop on interrupts from modules that have the module stop function when the possibility remains that an interrupt request may be output 2 As shown in figure 5 10 the point at which the NMI request is cleared is the state following the decoding stage for the instruction that replaces the interrupt exception processing ...

Page 102: ...hronization Returning from interrupt processing with an RTE instruction Figure 5 11 shows how a minimum interval of 1 cycle is required between the read instruction used for synchronization and the RTE instruction A read instruction for synchronization and a minimum of 1 instruction should thus be executed between the source clear and the RTE instruction Changing the level during interrupt process...

Page 103: ...92 Hitachi Figure 5 11 Pipeline Operation during Return with RTE Figure 5 12 Pipeline Operation when Interrupts are Enabled by Changing the SR ...

Page 104: ...le is required after the read instruction used for synchronization before interrupts are accepted even when an RTE instruction is executed A read instruction for synchronization should thus be executed between the source clear and the RTE instruction Changing the level during interrupt processing Figure 5 14 shows how a minimum interval of 2 cycles is required between the synchronization instructi...

Page 105: ...94 Hitachi Figure 5 14 Pipeline Operation when Interrupts are Enabled by Changing the SR ...

Page 106: ...ries UBCs 6 1 1 Features The features of the user break controller are listed below The following break compare conditions can be set Two break channels channel A channel B User break interrupts can be requested using either independent or sequential condition for the two channels sequential breaks are channel A then channel B Address Data channel B only Bus master CPU cycle DMA cycle external bus...

Page 107: ...ister AH L BBRA Break bus cycle register A BARBH L Break address register BH L BAMRBH L Break address mask register BH L BDRBH L Break data register BH L BDMRBH L Break data mask register BH L BBRB Break bus cycle register B BRCR Break control register Figure 6 1 User Break Controller Block Diagram ...

Page 108: ... BDRBL R W H 0000 H FFFFFF72 16 Break data mask register BH BDMRBH R W H 0000 H FFFFFF74 16 32 Break data mask register BL BDMRBL R W H 0000 H FFFFFF76 16 Break bus cycle register B BBRB R W H 0000 H FFFFFF68 16 32 Break control register BRCR R W H 0000 H FFFFFF78 16 32 Notes 1 Initializes by power on reset Values held for standby manual resets produce undefined values 2 No byte access permitted S...

Page 109: ... R W R W R W R W R W R W R W R W Bit 7 6 5 4 3 2 1 0 Bit name BAA7 BAA6 BAA5 BAA4 BAA3 BAA2 BAA1 BAA0 Initial value 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W The two break address registers A break address register AH BARAH and break address register AL BARAL together form a single group Both are 16 bit read write registers BARAH stores the upper bits bits 31 to 16 of the address of the ...

Page 110: ...AMA9 BAMA8 Initial value 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W Bit 7 6 5 4 3 2 1 0 Bit name BAMA7 BAMA6 BAMA5 BAMA4 BAMA3 BAMA2 BAMA1 BAMA0 Initial value 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W The two break address mask registers A BAMRA break address mask register AH BAMRAH and break address mask register AL BAMRAL together form a single group Both are 16 bit read write...

Page 111: ... 2 3 Break Bus Cycle Register A BBRA Bit 15 14 13 12 11 10 9 8 Bit name Initial value 0 0 0 0 0 0 0 0 R W R R R R R R R R Bit 7 6 5 4 3 2 1 0 Bit name CPA1 CPA0 IDA1 IDA0 RWA1 RWA0 SZA1 SZA0 Initial value 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W The break bus cycle register A BBRA is a 16 bit read write register that selects the following four channel A break conditions 1 CPU cycle peri...

Page 112: ...ycles 1 Break on both CPU and peripheral cycles Bits 5 and 4 Instruction Fetch Data Access Select A IDA1 IDA0 These bits select whether to break channel A on instruction fetch and or data access cycles Bit 5 IDA1 Bit 4 IDA0 Description 0 0 No channel A user break interrupt occurs initial value 1 Break only on instruction fetch cycles 1 0 Break only on data access cycles 1 Break on both instruction...

Page 113: ...ta access It is not determined by the bus width of the space being accessed 6 2 4 Break Address Register B BARB The channel B break address register has the same bit configuration as BARA 6 2 5 Break Address Mask Register B BAMRB The channel B break address mask register has the same bit configuration as BAMRA 6 2 6 Break Data Register B BDRB BDRBH Bit 15 14 13 12 11 10 9 8 Bit name BDB31 BDB30 BD...

Page 114: ... BDRBL specifies the bottom half bits 15 0 A power on reset initializes BDRBH and BDRBL to H 0000 BDRBH Bits 15 to 0 Break Data B 31 to 16 BDB31 to BDB16 These bits store the top half bits 31 16 of the data that is the break condition for break channel B BDRBL Bits 15 to 0 Break Data B 15 to 0 BDB15 to BDB0 These bits store the bottom half bits 15 0 of the data that is the break condition for brea...

Page 115: ...16 BDMB31 to BDMB16 These bits specify whether bits B 31 16 BDB31 to BDB16 of the channel B break data set in BDRBH are masked or not BDMRBL Bits 15 to 0 Break Data Mask B 15 to 0 BDMB15 to BDMB0 These bits specify whether bits B 15 0 BDB15 to BDB0 of the channel B break data set in BDRBL are masked or not Bits 31 0 BDMBn Description 0 Channel B break address bit BDBn is included in the break cond...

Page 116: ...rmines whether to include data bus on channel B in comparison conditions It also has a condition match flag that is set when conditions match A power on reset initializes BRCR to H 0000 Bit 15 CPU condition match flag A CMFCA Set to 1 when the conditions for CPU bus cycle that are break conditions set in channel A are met Not cleared to 0 Bit 15 CMFCA Description 0 Channel A CPU cycle conditions d...

Page 117: ... in break conditions Bit 12 UBC mode UMD Selects SH7000 series compatible mode or SH7095 mode Bit 12 UMD Description 0 Compatible mode for SH7000 series UBCs initial value 1 SH7095 mode Bit 11 Reserved bits This bit always reads 0 The write value should always be 0 Bit 10 PC break select A PCBA Selects whether to place the channel A break in the instruction fetch cycle before or after instruction ...

Page 118: ...eripheral cycle conditions have matched user break interrupt generated Bit 5 Reserve bit Reserved bit This bit always reads 0 The write value should always be 0 Bit 4 Sequence condition select SEQ Selects whether to handle the channel A and B conditions independently or sequentially Bit 4 SEQ Description 0 Compare channel A and B conditions independently initial value 1 Compare channel A and B con...

Page 119: ...t with 00 The respective conditions are set in the bits of the registers of the BRCR 2 When the set conditions are satisfied the UBC sends a user break interrupt request to the interrupt controller When conditions match up the CPU condition match flags CMFCA CMFCB and peripheral condition match flags CMFPA CMFPB for the respective channels are set 3 The interrupt controller checks the user break i...

Page 120: ...n first accepts the interrupt 4 When the condition stipulates after execution the instruction set with the break condition is executed and then the interrupt is generated prior to the execution of the next instruction As with pre execution breaks this cannot be used with overrun fetch instructions When this kind of break is set for a delay branch instruction or an interrupt disabled instruction su...

Page 121: ...es but size cannot be specified Setting sizes of byte word longword will be ignored Also no distinction can be made between instruction fetch and data access for external bus cycles All cycles are considered data access cycles so set 1 in bits IDA1 and IDB1 in BBRA and BBRB 3 External input of addresses uses A26 A0 so set bits 31 27 of the break address registers BARA BARB to 0 or set bits 31 27 o...

Page 122: ...6 BBRB H 0054 BDRB H 00000000 BDMRB H 00000000 BRCR H 1400 Conditions set A ch B ch independent mode A ch Address H 00000404 address mask H 00000000 Bus cycle CPU instruction fetch after execution read operand size not included in conditions B ch Address H 00008010 address mask H 00000006 Data H 00000000 data mask H 00000000 Bus cycle CPU instruction fetch before execution read operand size not in...

Page 123: ...ruction fetch is not a write cycle A user break interrupt is not generated for channel B because the instruction fetch is for an odd address D Register settings BARA H 00037226 BAMRA H 00000000 BBRA H 005A BARB H 0003722E BAMRB H 00000000 BBRB H 0056 BDRB H 00000000 BDMRB H 00000000 BRCR H 1010 Conditions set A ch to B ch sequential mode A ch Address H 00037226 address mask H 00000000 Bus cycle CP...

Page 124: ...nstruction fetch read operand size not included in conditions B ch Address H 00055555 address mask H 00000000 Data H 00007878 data mask H 00000F0F Bus cycle peripheral data access write byte For channel A a user break interrupt does not occur since no instruction fetch occurs in the DMAC cycle For channel B a user break interrupt occurs when the DMAC writes H 7 where means don t care as byte at H ...

Page 125: ...dresses when setting instruction fetch and after execution as break conditions and when executing in steps the UBC s exception processing service routine should not cause a match of addresses with the UBC 6 When the emulator is used the UBC is used on the emulator system side to implement the emulator s break function This means none of the UBC functions can be used when the emulator is being used...

Page 126: ... if instruction is overrun fetched and not executed as during branching Does not break if instruction is overrun fetched and not executed as during branching Conditions match in longword access when set for address other than longword boundaries 4n address Does not break Breaks Conditions match in word access when set for addresses other than word boundaries 2n addresses Does not break Breaks ...

Page 127: ...116 Hitachi ...

Page 128: ...ce 8 16 or 32 bits Wait state insertion can be controlled for each space Outputs control signals for each space Cache Cache areas and cache through areas can be selected by access address When a cache access misses 16 bytes are read consecutively in 4 byte units because of cache fill writes use the write through system Cache through accesses are accessed by access size Refresh Supports CAS before ...

Page 129: ...s received In partial master mode only CS2 space is shared with other CPUs all other spaces can be accessed at any time In slave mode the external bus is accessed when a bus use request is output and a bus use permission is received Refresh counter can be used as an interval timer Interrupt request generated upon compare match CMI interrupt request signal 7 1 2 Block Diagram Figure 7 1 shows the B...

Page 130: ...t control register RTCNT Refresh timer counter BCR Bus control register RTCOR Refresh time constant register MCR Individual memory control register RTCSR Refresh timer control status register Figure 7 1 BSC Block Diagram ...

Page 131: ...nchronous with column address output in DRAM synchronous DRAM and pseudo SRAM accesses When the bus is released the BS becomes an input for address monitoring of external bus cycles CS0 CS3 O Hi Z Chip select Signal that selects area specified by A26 and A25 RD WR WE I O I Read write signal Signal that indicates access cycle direction read write Connected to WE pin when a DRAM synchronous DRAM is ...

Page 132: ...gnal is low WAIT I Ignore Hardware wait input BACK BRLS I I Bus use enable input in partial master or slave BACK Bus release request input in total master BRLS BREQ BGR O O Bus request output in partial master or slave BREQ Bus grant output in total master BGR CKE O O Synchronous DRAM clock enable control Signal for supporting synchronous DRAM self refresh IVECF O Hi Z Interrupt vector fetch DREQ0...

Page 133: ...2 32 Notes 1 This address is for 32 bit accesses for 16 bit accesses add 2 2 16 bit access is for read only 7 1 5 Address Map The SH7095 address map which has a memory space of 256 Mbytes is divided into four spaces The types and data width of devices that can be connected are specified for each space The overall space address map is listed in table 7 3 Since the spaces of the cache area and the c...

Page 134: ...4000000 to H 25FFFFFF CS2 space cache through area Ordinary space or synchronous DRAM 32 Mbytes H 26000000 to H 27FFFFFF CS3 space cache through area Ordinary space synchronous DRAM DRAM or pseudo DRAM 32 Mbytes H 28000000 to H 3FFFFFFF Reserved H 40000000 to H 47FFFFFF Associative purge space 128 Mbytes H 48000000 to H 5FFFFFFF Reserved H 60000000 to H 7FFFFFFF Address array read write space 512 ...

Page 135: ...R The MASTER bit is used to check the settings of the bus arbitration function set by the mode settings with the external input pin It is a read only bit Bit 15 MASTER Description 0 Master mode 1 Slave mode Bits 14 13 and 3 Reserved bits These bits always read 0 Bit 12 Endian Specification of Area 2 ENDIAN For big Endian the MSB of byte data is the lowest byte address and byte data goes in order t...

Page 136: ...s of these fields are effective when the bits that specify the respective area waits in the wait control registers W21 W20 and W31 W30 specify long waits i e 11 Bit 9 AHLW1 Bit 8 AHLW0 Description 0 0 3 waits 1 4 waits 1 0 5 waits 1 6 waits Initial value Bits 7 6 Long Wait Specification of Area 1 A1LW1 A1LW0 When the basic memory interface setting is area 1 the wait specifications of these fields ...

Page 137: ...is ordinary space 1 Areas 2 and 3 are synchronous DRAM spaces 1 0 Reserved do not set 1 Reserved do not set 7 2 2 Bus Control Register 2 BCR2 Bit 15 14 13 12 11 10 9 8 Bit name Initial value 0 0 0 0 0 0 0 0 R W R R R R R R R R Bit 7 6 5 4 3 2 1 0 Bit name A3SZ1 A3SZ0 A2SZ1 A2SZ0 A1SZ1 A1SZ0 Initial value 1 1 1 1 1 1 0 0 R W R W R W R W R W R W R W Initialize BCR2 after a power on reset and do not ...

Page 138: ...Z1 A2SZ0 Effective only when setting ordinary space Bit 5 A2SZ1 Bit 4 A2SZ0 Description 0 0 Reserved do not set 1 Byte 8 bits size 1 0 Word 16 bits size 1 Longword 32 bits size Initial value Bits 3 2 Bus Size Specification of Area 1 A1SZ1 A1SZ0 Bit 3 A1SZ1 Bit 2 A1SZ0 Description 0 0 Reserved do not set 1 Byte 8 bits size 1 0 Word 16 bits size 1 Longword 32 bits size Initial value Bits 1 0 Reserve...

Page 139: ...h is slow to turn the read buffer off and fast memories and I O interfaces Even when access is to the same area idle cycles must be inserted when a read access is followed immediately by a write access The idle cycles to be inserted comply with the area specification of the previous access IW31 IW21 IW11 IW01 IW30 IW20 IW10 IW00 Description 0 0 No idle cycle 1 Inserts one idle cycle 1 0 Inserts tw...

Page 140: ... is specified by wait control W31 and W30 and W21 and W20 respectively W31 W21 W30 W20 Description 0 0 1 cycle 1 2 cycles 1 0 3 cycles 1 4 cycles With synchronous DRAM external wait input is ignored regardless of setting When area 3 is pseudo SRAM the number of cycles from BS signal assertion to the end of cycle is specified by wait control W31 and W30 Bit 7 W31 Bit 6 W30 Description 0 0 2 cycles ...

Page 141: ...m number of cycles after RAS is negated before next assert When pseudo SRAM is connected specifies the minimum number of cycles after CE is negated before next assert When synchronous DRAM is connected specifies the minimum number of cycles after precharge until bank active command is output See section 7 5 Synchronous DRAM Interface for details Bit 15 TRP Description 0 1 cycle Initial value 1 2 c...

Page 142: ...s TRAS the OE width for pseudo SRAM is TRAS 1 cycle After an auto refresh command is issued the synchronous DRAM does not issue a bank active command for TRAS 2 cycles regardless of the TRP bit setting For synchronous DRAMs there is no RAS assertion period but there is a limit for the time from the issue of a refresh command until the next access This value is set to adhere to this limit Commands ...

Page 143: ...interface Bit 7 AMX2 Bit 5 AMX1 Bit 4 AMX0 Description 0 0 0 8 bit column address DRAM 1 9 bit column address DRAM 1 0 10 bit column address DRAM 1 11 bit column address DRAM 1 0 0 Reserved do not set 1 Reserved do not set 1 0 Reserved do not set 1 Reserved do not set For synchronous DRAM interface Bit 7 AMX2 Bit 5 AMX1 Bit 4 AMX0 Description 0 0 0 16 Mbit DRAM 1M 16 bits 1 16 Mbit DRAM 2M 8 bits ...

Page 144: ... RFSH bit is 1 self refresh mode is entered immediately after the RMD bit is set to 1 When the RFSH bit is 1 and this bit is 0 a CAS before RAS refresh or auto refresh is performed at the interval set in the 8 bit interval timer When a refresh request occurs during an external area access the refresh is performed after the access cycle is completed When set for self refresh self refresh mode is en...

Page 145: ...lag CMF This status flag which indicates that the values of RTCNT and RTCOR match is set cleared under the following conditions Bit 7 CMF Description 0 RTCNT and RTCOR match Clear condition After RTCSR is read when CMF is 1 0 is written in CMF 1 RTCNT and RTCOR do not match Set condition RTCNT RTCOR Bit 6 Compare Match Interrupt Enable CMIE Enables or disables an interrupt request caused by the CM...

Page 146: ...fresh Timer Counter RTCNT Bit 15 14 13 12 11 10 9 8 Bit name Initial value 0 0 0 0 0 0 0 0 R W R R R R R R R R Bit 7 6 5 4 3 2 1 0 Bit name Initial value 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W The 8 bit counter RTCNT counts up with input clocks The clock select bit of RTCSR selects an input clock RTCNT values can always be read written by the CPU When RTCNT matches RTCOR RTCNT is clea...

Page 147: ...sly until the CMF bit of the RTSCR is cleared When the CMF bit clears it only affects the interrupt it is not cleared by the refresh request When a refresh is performed and refresh requests are counted using interrupts a refresh can be set simultaneously with the interval timer interrupt Bits 15 8 Reserved bits These bits always read 0 The write value should always be 0 7 3 Access Size and Data Al...

Page 148: ...undary 4n 2 address instruction fetches are performed in longword units from 4n address Figures 7 2 7 4 show the relationship between device data widths and access units Figure 7 2 32 Bit External Devices and Their Access Units Ordinary Figure 7 3 16 Bit External Devices and Their Access Units Ordinary ...

Page 149: ...and D7 D0 to the most significant bytes When support software like the compiler or linker does not support switching the instruction code and constants in the program do not become little Endian For this reason be careful not to place programming or constants in the CS2 space When instructions or data in other CS spaces are used by transferring it to CS2 space with the SH7095 there is no problem b...

Page 150: ...le The CSn signal is negated by the fall of clock T2 to ensure the negate period The negate period is thus half a cycle when accessed at the minimum pitch The access size is not specified during a read The correct access start address will be output to the LSB of the address but since no access size is specified the read will always be 32 bits for 32 bit devices and 16 bits for 16 bit devices For ...

Page 151: ...buffers the RD signal must be used for data output in the read direction When RD WR signals do not perform accesses the LSI stays in read status so there is a danger of conflicts occurring with output when this is used to control the external data buffer Figure 7 7 Basic Timing of Ordinary Space Access Figure 7 8 shows an example of a 32 bit data width SRAM connection figure 7 9 a 16 bit data widt...

Page 152: ...Hitachi 141 Figure 7 8 Example of 32 Bit Data Width SRAM Connection ...

Page 153: ...142 Hitachi Figure 7 9 Example of 16 Bit Data Width SRAM Connection Figure 7 10 Example of 8 Bit Data Width SRAM Connection ...

Page 154: ...n of BCR1 can be made independently for CS0 and CS1 spaces but the same value must be specified for CS2 and CS3 spaces All WCR specifications are independent A Tw cycle as long as the number of specified cycles is inserted as a wait cycle at the wait timing for ordinary access space shown in figure 7 11 Figure 7 11 Wait Timing of Ordinary Space Access Software Wait Only When the wait is specified ...

Page 155: ...mpled at the clock rise External waits should not be inserted however into word accesses of devices such as ordinary space and burst ROM that have a 8 bit bus width byte size Control waits in such cases with software only Figure 7 12 Wait State Timing of Ordinary Space Access Wait States from WAIT Signal ...

Page 156: ...ignals for directly connecting synchronous DRAM are RAS CE CAS OE RD WR CS2 or CS3 DQMUU DQMUL DQMLU DQMLL and CKE signals Signals other than CS2 and CS3 are common to every area and signals other than CKE are valid and fetched only when CS2 or CS3 is true Therefore synchronous DRAM of multiple areas can be connected in parallel CKE is negated only when a self refresh is performed to low level oth...

Page 157: ...146 Hitachi Figure 7 13 Synchronous DRAM 32 bit Device Connection ...

Page 158: ...inal value regardless of multiplexing When SZ 0 the data width on the synchronous DRAM side is 16 bits and the LSB of the device s address pins A0 specifies word address The A0 of the synchronous DRAM is thus connected to the A1 pin of the SH7095 the rest of the connection proceeding in the same order beginning with the A1 pin to the A2 pin When SZ 1 the data width on the synchronous DRAM side is ...

Page 159: ... A16 A17 2 A19 A20 A21 AMX2 AMX0 settings of 100 101 and 110 are reserved so do not use them When SZ 0 the settings 001 and 010 are reserved as well so do not use them either Notes 1 L H is a bit used to specify commands It is fixed to L or H by the access mode 2 Specifies bank address 7 5 3 Burst Read Figure 7 15 shows the timing chart for burst reads In the following example 2 synchronous DRAMs ...

Page 160: ...ency is 2 or more a Tap cycle equal to the TRP specification 1 is generated During the Tap cycle no commands other than NOP are issued to the same bank Figure 7 16 shows an example of burst read timing when RCD is 1 W31 W30 is 01 and TRP is 1 With the synchronous DRAM cycle when the bus cycle starts in the ordinary space access the BS signal asserted for 1 cycle is asserted in each of cycles Td1 T...

Page 161: ...150 Hitachi Figure 7 15 Basic Burst Read Timing Auto Precharge ...

Page 162: ...fer by DMAC and the transfer unit is something other than 16 bytes Figure 7 17 shows the timing of a single address read Because the synchronous DRAM is set to the burst read single write mode the read data output continues after the required data is received To avoid data conflict an empty read cycle is performed from Td2 to Td4 after the required data is read in Td1 and the device waits for the ...

Page 163: ...6 byte boundaries when performing DMA transfers that specify synchronous DRAM as the source Figure 7 17 Single Read Timing Auto Precharge 7 5 5 Write Unlike synchronous DRAM reads synchronous DRAM writes are single writes Figure 7 18 shows the basic timing chart for write accesses After the ACTV command Tr a WRITA command is issued in Tc to perform an auto precharge In the write cycle the write da...

Page 164: ...it for the precharge during read accesses the issuing of any new commands to the same bank during this period is delayed by adding a cycle Trw1 to wait until the precharge is started up The number of cycles in the Trw1 cycle can be specified using the TRWL bit of the MCR Figure 7 18 Basic Write Cycle Timing Auto Precharge ...

Page 165: ...me row address P1 and the average number of cycles from the end of one access to the next access tA When tA is longer than tAP the delay waiting for the precharge during a read becomes invisible If tA is longer than tRWL tAP the delay waiting for the precharge also becomes invisible during writes The differences between the bank active mode and basic access speeds in these cases are the number of ...

Page 166: ...ng as the same row address continues to be accessed when only accesses to the respective banks of the CS3 space are considered Accesses to other CS spaces during this period have no effect When an access occurs to a different row address while the bank is active figure 7 21 or figure 7 24 will be substituted for figures 7 20 and 7 23 after this is detected Both banks will become inactive even in t...

Page 167: ...156 Hitachi Figure 7 20 Burst Read Timing Bank Active Same Row Address ...

Page 168: ...Hitachi 157 Figure 7 21 Burst Read Timing Bank Active Different Row Addresses ...

Page 169: ...158 Hitachi Figure 7 22 Write Timing No Precharge ...

Page 170: ...Hitachi 159 Figure 7 23 Write Timing Bank Active Same Row Address ...

Page 171: ...a function to control refreshes of synchronous DRAM Auto refreshes can be performed by setting the MCR s RMD bit to 0 and the RFSH bit to 1 When the synchronous DRAM is not accessed for a long period of time set the RFSH bit and RMODE bit both to 1 to start up the self refresh mode which uses low consumption power to maintain data ...

Page 172: ... the count up starts up again Figure 7 25 shows the timing for the auto refresh cycle First a PALL command is issued during the Tp cycle to change all the banks from active to precharge states A REF command is then issued in the Trr cycle After the Trr cycle no new commands are output for the number of cycles specified in the TRAS bit of the MCR 2 cycles The TRAS bit must be set to satisfy the ref...

Page 173: ...e this time must be reflected in the initial RTCNT setting When the RTCNT value is set to RTCOR 1 the refresh can be started immediately If the standby function of the SH7095 is used after the self refresh is set to enter the standby mode the self refresh state continues the self refresh state will also be maintained after returning from a standby using an NMI Manual reset cannot be used to get ou...

Page 174: ...the value to be set is X the bus state controller operates by writing to address X H FFFF8000 from the CPU which allows the value X to be written to the synchronous DRAM mode register Data is ignored at this time but mode is written using word as the size Write any data in word size to the following addresses to set for the burst read single write supported by the SH7095 a CAS latency of 1 to 3 a ...

Page 175: ...onous DRAM is turned on When the pulse width of the reset signal is longer than the idle time the mode register may be set immediately without problem The dummy auto refresh cycle must run at least as long as the number set by the manufacturer usually 8 After setting the auto refresh it is usual for this to occur naturally during the various initializations but there is a way to set the interval w...

Page 176: ...internal clock Sampling of the signals input by the synchronous DRAM and output of the read data however starts with the rising edge of the external clock figure 7 28 When the internal clock of the SH7095 and external clock are synchronized signal transmission from the SH7095 to the synchronous DRAM has a 1 cycle margin The transmission of read data from the synchronous DRAM to the SH7095 however ...

Page 177: ...AM and transmission from the SH7095 to the synchronous DRAM each takes 3 4 cycle Given this using a clock whose phase is shifted 90 degrees from the external clock using a PLL as the internal clock can ensure a margin of safety When using a PLL it is important to note that the synchronous DRAM does not contain an on chip PLL When using the external clock input clock mode instability in the clock s...

Page 178: ...Hitachi 167 a Phase Shifted 90 by PLL b Phase Shift Using PLL is 0 Figure 7 28 Phase Shift with the PLL ...

Page 179: ...n can be used to directly connect the SH7095 to the DRAM The data width of an interface can be 16 or 32 bits figures 7 29 and 7 30 Two CAS 16 bit DRAMs can be connected since CAS is used to control byte access The RAS CASHH CASHL CASLH CASLL and RD WR signals are used to connect the DRAM When the data width is 16 bits CASHH and CASHL are not used In addition to ordinary read and write access burst...

Page 180: ...Hitachi 169 Figure 7 29 Example of a DRAM Connection 32 Bit Data Width ...

Page 181: ...ng which can be selected using the MCR s AMX1 AMX0 bits Table 7 5 illustrates the relationship between AMX1 AMX0 bits and address multiplexing Address multiplexing is performed on address output pins A13 A1 The original addresses are output to the pins A26 A14 During DRAM accesses AMX2 is reserved so set it to 0 Table 7 5 Relationship between AMX1 AMX0 and Address Multiplexing AMX1 AMX0 No of Colu...

Page 182: ...ic DRAM access timing Tp is the precharge cycle Tr is the RAS assert cycle Tc1 is the CAS assert cycle and Tc2 is the read data fetch cycle When accesses are consecutive the Tp cycle of the next access overlaps the Tc2 cycle of the previous access so accesses can be performed at a minimum of 3 cycles each ...

Page 183: ... Access Timing 7 6 4 Wait State Control When the clock frequency is raised 1 cycle may not always be sufficient for all states to end as the basic access does Setting bits in the WCR and MCR enable the state to be lengthened Figure ...

Page 184: ... to the RCD bit of the MCR The number of cycles from CAS assert to the end of access can be extended from 1 cycle to 3 cycles by setting the W31 W30 bits of the WCR When anything other than 00 is set in W31 and W30 the external wait pin WAIT is also sampled so the number of cycles becomes even longer Figure 7 33 shows the timing of wait state control using the WAIT pin In either case when consecut...

Page 185: ...ed page mode for use when continuously accessing the same row that enables fast access of data by changing only the column address after the row address is output Select ordinary access or high speed page mode by setting the burst enable bit BE in the MCR Figure 7 34 shows the timing of burst operation in the high speed page mode When performing burst access cycles can be inserted using the wait s...

Page 186: ...e however write cycles to ordinary space during RAS down will simultaneously start up an erroneous write access to the DRAM This means that when no external devices that writes other than DRAM are connected a DRAM can be directly interfaced using RAS down When the RAS down mode is used the refresh cycle must be less than the maximum DRAM RAS assert time tRAS when the refresh cycle is longer than t...

Page 187: ...termined by the input clock selected in CKS2 CKS0 of the RTCSR and the value set in the RTCOR Set the values of RTCOR and CKS2 CKS0 so they satisfy the refresh interval specifications of the DRAM being used First set the RTCOR RTCNT and the RMODE and RFSH bits of the MCR then set the CKS2 CKS0 bits When a clock is selected with the CKS2 CKS0 bits RTCNT starts counting up from the value at that tim...

Page 188: ...me in refresh cycles follows the TRP bit of the MCR Figure 7 35 Refresh Cycle Timing 7 6 7 Power On Sequence When DRAM is being used after the power is turned on dummy CAS before RAS refresh cycles longer than the waiting time during which accesses cannot be performed 100 µs or 200 µs minimum and a prescribed number that follows it usually 8 are requested The bus state controller does not perform ...

Page 189: ...ls used for connecting pseudo SRAM are the CE OE WE3 WE2 WE1 and WE0 signals The WE3 and WE2 signals are not used when the data width is 16 bits When a non multiplexed pseudo SRAM is connected the RD signal is also used In addition to ordinary read and write access burst access using the static column access function is also supported Figure 7 36 shows an example of connections to a 1 M pseudo SRA...

Page 190: ...Hitachi 179 Figure 7 36 Example of Pseudo SRAM Connection 1 M pseudo SRAM ...

Page 191: ...180 Hitachi Figure 7 37 Example of Pseudo SRAM Connection 4 M pseudo SRAM ...

Page 192: ...arge cycle Tr is the CE assert cycle Tc1 is the write data output BS is the assert cycle and Tc2 is the read data fetch cycle When accesses are consecutive the precharge cycle Tp of the next access overlaps the Tc2 cycle of the previous access so accesses can be performed in a minimum of 3 cycles each ...

Page 193: ...clock frequency is raised 1 cycle may not always be sufficient for all states to end as the basic access does Setting bits in the WCR and MCR enable the state to be lengthened Figure 7 39 shows an example of lengthening a state using settings The Tp cycle that ensures sufficient ...

Page 194: ...1 and W30 the external wait pin WAIT is also sampled so the number of cycles can be made even longer Figure 7 40 shows the timing of wait state control using the WAIT pin In either case when consecutive accesses occur the Tp of one access overlaps with the Tc2 of the previous access The RCD bit of the MCR is set to 0 for a pseudo SRAM interface but when set to 1 the number of cycles from the CE as...

Page 195: ...pseudo SRAM can access data at high speed by changing only the column address and leaving CE asserted This function is called the static column mode Select between ordinary access and burst mode using static column mode by setting the burst enable bit BE in the MCR Figure 7 41 shows the timing of burst operation using static column mode When performing burst access cycles can be inserted using the...

Page 196: ...d by the input clock selected in CKS2 CKS0 of the RTCSR and the value set in the RTCOR Set the values of RTCOR and CKS2 CKS0 so they satisfy the refresh interval specifications of the pseudo SRAM being used First set the RTCOR RTCNT and the RMODE and RFSH bits of the MCR then set the CKS2 CKS0 bits When a clock is selected with the CKS2 CKS0 bits RTCNT starts counting up from the value at that tim...

Page 197: ... the RMODE and RFSH bits to 1 During the self refresh the pseudo SRAM cannot be accessed To clear the self refresh set either the RMODE or RFSH bit to 0 After self refresh mode is cleared issuing of commands is inhibited for 1 auto refresh cycle When more time than this is required to return from self refresh write the program so that there are no accesses to the pseudo SRAM including auto refresh...

Page 198: ... timing of nibble accesses to burst ROM Set for two wait cycles The access is basically the same as an ordinary access but when the first cycle ends only the address is changed The CS0 signal is not negated enabling the next access to be conducted without a T1 cycle for ordinary space access From the second time on the T1 cycle is omitted so access is 1 cycle faster than ordinary accesses Currentl...

Page 199: ...6 byte transfers longword accesses are repeated 4 times When one or more wait states are set for a burst ROM access the WAIT pin is sampled When the burst ROM is set and 0 indicated for waits there are 2 access cycles from the second time on Figure 7 46 shows the timing Figure 7 44 Burst ROM Nibble Access 2 Wait States ...

Page 200: ...it bus width byte access T1 Tw T2 Tw T2 16 bit bus width longword access T1 Tw T2 16 bit bus width word access T1 Tw T2 16 bit bus width byte access T1 Tw T2 32 bit bus width longword access T1 Tw T2 32 bit bus width word access T1 Tw T2 32 bit bus width byte access Figure 7 45 Data Width and Burst ROM Access 1 Wait State ...

Page 201: ...y a write from the SH7095 When the SH7095 is writing continuously if the format is always to have the direction of the data from the SH7095 to other memory there are no particular problems Neither is there any particular problem if the following read access is to the same CS space since data is output from the same data buffer After a read is performed from CS3 space by the IW31 and IW30 bits of t...

Page 202: ...us arbitration is being performed an open cycle is inserted for arbitration so no wait is inserted between cycles figure 7 47 Figure 7 47 Waits between Access Cycles 7 10 Bus Arbitration The SH7095 has a bus arbitration function that when a bus release request is received from an external device releases the bus to that device after the bus cycle being executed is completed In addition it also has...

Page 203: ... also bus requests from external devices while in the master mode The priority for bus requests when they occur simultaneously is highest to lowest refresh requests bus requests from external devices DMAC and CPU When the bus is being passed between slave and master all bus control signals are negated before the bus is released to prevent the connected devices from operating in error Once the bus ...

Page 204: ...nal indicating that the slave has released the bus it negates the BGR to high level and begins using the bus When the bus is released all output and I O signals related to the bus interface are changed to high impedance except for the CKE of the synchronous DRAM interface the BGR of bus arbitration and DMA transfer control signals DACK0 and DACK1 When the DRAM or pseudo SRAM has finished prechargi...

Page 205: ...need to request that the bus be released when a refresh request occurs If the slave is something designed by an individual user however an attempt may be made to produce multiple bus accesses consecutively to reduce the overhead required for bus arbitration When a slave that requires a total time for consecutive multiple bus accesses in excess of the refresh period is connected design it so that t...

Page 206: ...e following clock rise and the bus cycle starts The last signal negated when the access cycle ended is synchronously with the clock rise Half a cycle after the clock rise the BREQ signal is negated the master notified that the bus is released and one cycle later the address and data output buffers turned off high impedance At the following clock fall the control signals become high impedance Figur...

Page 207: ... of connections between the partial share master mode and a chip in master mode On the master mode side the CS3 space is connected to synchronous DRAM and the CS0 space to ROM On the partial share master mode side the CS0 space is connected to ROM the master side synchronous DRAM is connected to the CS2 space and the CS3 space is connected to dedicated synchronous DRAM The partial share master is ...

Page 208: ...negated at the clock fall Control of the buffer when a CS2 space device is being accessed from the partial share master references the BREQ and BACK signals Notification that the bus is enabled for use is conducted by the BACK connected to the partial share master but the BACK signal may be negated while the bus is in use when the master requires the bus back to service a refresh or the like For t...

Page 209: ...198 Hitachi Figure 7 50 Master and Partial Share Master Connections ...

Page 210: ... on address multiplexing 7 5 2 7 10 5 Master and Slave Coordination Roles must be shared between the master and slave to control system resources without contradictions DRAM synchronous DRAM and pseudo SRAM must be initialized before use When using standby operation to lower power consumption burdens must also be shared This SH7095 was designed with the idea that the master mode device would handl...

Page 211: ...DMAC that is the bus master ends the access in a longword unit since the access request is canceled by the manual reset This means that when a manual reset comes in during a cache fill the cache contents can no longer be guaranteed During a manual reset the RTCNT does not count up so no refresh request is generated The refresh cycle does not start up To preserve the data of the DRAM synchronous DR...

Page 212: ... to use the Internal bus it notifies the CPU that the write is completed without waiting for the actual writing to the on chip peripheral module or off the chip to end When it does not have the right to use the internal bus as when it is being used by the DMAC or the like it waits until it gets the bus before notifying the CPU of completion Accesses to cache through areas and on chip peripheral mo...

Page 213: ...ta read must be able to use the internal bus and external bus to be output externally The external bus is not needed to access on chip peripheral modules with the CPU or DMAC but it is needed to output trace data This means that when the emulator is used in the trace data fetch mode internal access operations of the CPU or DMAC are not performed in parallel with the external bus cycle so extra exe...

Page 214: ... of an instruction or data does not use cache Each line of cache memory consists of 16 bytes Cache memory is always updated in line units Four 32 bit accesses are required to update a line Since the number of entries is 64 the six bits A9 to A4 in each address determine the entry A four way set associative configuration is used so up to four different instructions data can be stored in the cache e...

Page 215: ...s used for cache control The cache control register CCR must be set and the cache must be initialized before use Bit 7 6 5 4 3 2 1 0 Bit name W1 W0 CP TW OD ID CE Initial value 0 0 0 0 0 0 0 0 R W R W R W R R W R W R W R W R W Bits 7 and 6 Way Specification W1 to W0 W1 and W0 specify the way when an address array is directly accessed by address specification 00 Way 0 Initial value 01 Way 1 10 Way ...

Page 216: ...n if the cache is missed Cache data is however read or updated during cache hits OD is valid only when CE is 1 0 Data replaced Initial value 1 Data not replaced even when cache missed in data access Bit 1 Instruction Replacement Disable ID ID is the bit for disabling instruction replacement When this bit is 1 an instruction fetched from external memory is not written to the cache even if the cache...

Page 217: ...dresses output from the CPU A match to the tag address of a way is called a cache hit In proper use the tag addresses of each way differ from each other but and the tag address of only one way will match When none of the way tag addresses match it is called a cache miss Tag addresses of entries with valid bits of 0 will not match in any case When a cache hit occurs data is read from the data array...

Page 218: ...Hitachi 207 EX Instruction execution MA Memory Access WB Write back Figure 8 3 Reading during a Cache Hit ...

Page 219: ... starts with whatever address output to the internal address bus will make the longword that contains the address to be read from the cache come last as the byte address within the line as the order 4 The data read on the internal data bus is written sequentially to the cache data array When the last data is written to the cache data array it is simultaneously written to the cache data bus and the...

Page 220: ...hey match the write data output to the cache data bus in the following cycle is written to the data array When they do not match nothing is written to the cache data array The write address is output to the internal address bus 1 cycle later than the cache address bus The write data is similarly output to the internal data bus 1 cycle later than the cache data bus The CPU waits until the writes on...

Page 221: ...o the cache data bus The read of the cache through area is only performed on the address in question For write operations the write data on the cache data bus is output to the internal data bus Writes on the cache through area are compared to the address tag except for the fact that nothing is written to the data array the operation is the same as the write shown in figure 8 7 EX Instruction execu...

Page 222: ... Replacement When a cache miss occurs during a read the data of the missed address is read from 1 line 16 bytes of memory and replaced This makes it important to decide which of the ways to replace It is likely that the way least recently used has the highest probability of being the next to be accessed This algorithm for replacing ways is called least recently used replace algorithm or LRU The ha...

Page 223: ...e used to rewrite When this is done be sure not to write a value other than 0 as the LRU information When the CCR s OD bit or ID bit are 1 neither will replace the cache even if a cache miss occurs during data read or instruction fetch Instead of replacing the missed address data is read and directly transferred to the CPU The two way mode of the cache set by the CCR s TW bit can only be implement...

Page 224: ...This means that the prefetched instructions are read from the cache To do a proper purge write 0 to the CCR s CE bit then disable the cache and purge Since the CCR s CE bit is cleared to 0 by a power on reset or manual reset the cache can be purged immediately by a reset 8 4 7 Associative Purges Associative purges invalidate 1 line 16 bytes corresponding to specific address contents when the conte...

Page 225: ...on H C0000C00 to H C0000FFF When the two way mode is being used the area H C0000000 to H C00007FF is accessed as 2 kbytes of on chip RAM When the cache is disabled the area H C0000000 to H C0000FFF can be used as 4 kbyte of on chip RAM When the contents of the way being used as cache is rewritten using a data array access the contents of external memory and cache will not match so this method shou...

Page 226: ... value to be written then written LRU information is written from data but 0 should always be written to prevent malfunctions V Valid bit Figure 8 11 Address Array Access 8 5 Cache Use 8 5 1 Initialization In reset cache memory is not initialized Therefore the cache must be initialized by software before use Cache initialization clears to 0 the address array valid bit and all LRU information The a...

Page 227: ...itten address area must be purged All entries of the cache can be purged by setting the CP bit of the CCR to 1 However it is efficient to purge only specific lines if only limited number of entries are be purged An associative purge is used to purge specific lines Since cache lines are 16 bytes purges are performed in a 16 byte units The four ways are checked simultaneously and only lines holding ...

Page 228: ...ncy can be maintained When data that extends over multiple words such as a structure is rewritten however interrupts are generated at the rewrites which can lower performance This method is most appropriate for cases in which it is difficult to predict and detect the timing of data updates and the update frequency is low To purge the cache using program logic the data updates are detected by the p...

Page 229: ...eplacement as specified by the LRU information The conditions for updating the LRU information are the same as for four way mode except that the number of ways is two Ways 0 and 1 when they are a 2 kbyte RAM are accessed through the data array Figure 8 14 shows the address mapping Figure 8 14 Address Mapping of 2 kbyte RAM in the Two Way Mode 8 5 5 Usage Notes Standby Disable the cache before ente...

Page 230: ...Hitachi 219 reason change the contents of the cache control register while disabling the cache or after the cache is disabled ...

Page 231: ...220 Hitachi ...

Page 232: ...16M transfers With cache hits CPU instruction processing and DMA operation can proceed in parallel The maximum transfer rate for synchronous DRAM burst transfers is 38 Mbytes sec f 28 7 MHz Single address mode transfers Either the transfer source or transfer destination peripheral device is accessed by a DACK signal selectable while the other is accessed by address One transfer unit of data is tra...

Page 233: ...ther by edge or by level and by either active low or active high Requests from on chip peripheral modules serial communications interface SCI Auto request the transfer request is generated automatically within the DMAC Selectable bus modes Cycle steal mode or burst mode Selectable channel priority levels Fixed or round robin mode CPU can be asked for interrupt when data transfer ends 9 1 2 Block D...

Page 234: ... DMA transfer counter register CHCRn DMA channel control register VCRDMAn DMA vector register DEIn Request for interrupt at end of DMA transfer to CPU RXI Receive data full interrupt transfer request of on chip SCI TXI Transmit data full interrupt transfer request of on chip SCI n 0 to 1 Figure 9 1 DMAC Block Diagram ...

Page 235: ... transfer request acknowledge output from channel 0 to external device 1 DMA transfer request DREQ1 I DMA transfer request input from external device to channel 1 DMA transfer request acknowledge DACK1 O DMA transfer request acknowledge output from channel 1 to external device 9 1 4 Register Configuration Table 9 2 summarizes the DMAC registers The DMAC has a total of 13 registers Each channel has...

Page 236: ...ndefined H FFFFFF94 32 DMA transfer count register 1 TCR1 R W Undefined H FFFFFF98 32 DMA channel control register 1 CHCR1 R W 1 H 00000000 H FFFFFF9C 32 DMA vector number register N1 VCRDMA1R W 1 Undefined H FFFFFFA8 32 DMA request response selection control register 1 DRCR1 R W 1 H 00 H FFFFFE72 8 3 Shared DMA operation register DMAOR R W 2 H 00000000 H FFFFFFB0 32 Notes 1 Writing permitted only...

Page 237: ...gisters that specify the destination address of a DMA transfer During a DMA transfer these registers indicate the next destination address In single address mode DAR is ignored in transfers from memory mapped external devices or external memory to external devices with DACK The value after resets is undefined Values are held in standby mode and during module standbys 9 2 3 DMA Transfer Count Regis...

Page 238: ... 0 to clear the flag DMA channel control registers 0 and 1 CHCR0 and CHCR1 are 32 bit read write registers that control the DMA transfer mode They also indicate DMA transfer status Only the bottom 16 of the 32 bits are effective They are written as 32 bit values including the top 16 bits Write the initial values to the top 16 bits They always read 0 The registers are initialized to H 00000000 by a...

Page 239: ... to 00 by resets and the standby mode Values are held during a module standby Bit 13 SM1 Bit 12 SM0 Description 0 0 Fixed source address 16 for 16 byte transfer size Initial value 1 Source address is incremented 1 for byte transfer size 2 for word transfer size 4 for longword transfer size 16 for 16 byte transfer size 1 0 Source address is decremented 1 for byte transfer size 2 for word transfer s...

Page 240: ...ing a module standby Bit 8 AM Description 0 DACK output in read cycle transfer from memory to device Initial value 1 DACK output in write cycle transfer from device to memory Bit 7 Acknowledge Level Bit AL This bit selects whether the DACK signal is an active high signal or an active low signal The AL bit is initialized to 0 by reset and in the standby mode Values are held during a module standby ...

Page 241: ...ines whether or not to request a CPU interrupt at the end of a DMA transfer When the IE bit is set to 1 an interrupt DEI is requested from the CPU when the TE bit is set The IE bit is initialized to 0 by reset and in the standby mode Values are held during a module standby Bit 2 IE Description 0 Interrupt disabled Initial value 1 Interrupt enabled Bit 1 Transfer End Flag Bit TE Indicates that the ...

Page 242: ...g this bit to 0 The DE bit is initialized to 0 by reset and in the standby mode Values are held during a module standby Bit 0 DE Description 0 DMA transfer disabled Initial value 1 DMA transfer enabled 9 2 5 DMA Vector Number Registers 0 and 1 VCRDMA0 VCRDMA1 Bit 31 30 29 11 10 9 8 Bit name Initial value 0 0 0 0 0 0 0 R W R R R R R R R Bit 7 6 5 4 3 2 1 0 Bit name VC7 VC6 VC5 VC4 VC3 VC2 VC1 VC0 I...

Page 243: ... bit read write registers that set the vector address of the DMAC transfer request source It is written as an 8 bit value It is initialized to H 00 by a reset It holds the value in the module standby Bits 7 2 Reserved These bits cannot be modified They always read 0 Bits 1 0 Resource Select Bits 1 0 RS1 RS0 Specify which transfer request to input to the DMAC Changing the transfer request source mu...

Page 244: ... These bits cannot be modified They always read 0 Bit 3 Priority Mode Bit PR Selects the priority level between channels when there are transfer requests for multiple channels It is initialized to 0 by a reset and in the standby mode Values are held during a module standby Bit 3 PR Description 0 Fixed priority Ch 0 Ch 1 initial value 1 Round robin Top priority shifts to bottom after each transfer ...

Page 245: ... and then write 0 1 NMIF has occurred Bit 0 DMA Master Enable Bit DME Enables or disables DMA transfers on all channels A DMA transfer becomes enabled when the DE bit in the CHCR and the DME bit are set to 1 For this to be effective however the TE bit of the CHCR and the NMIF and AE bits must all be 0 When the DME bit is cleared all channel DMA transfers are aborted DME is initialized to 0 on rese...

Page 246: ... NMIF 0 AE 0 2 When a transfer request comes and transfer is enabled it transfers 1 transfer unit of data For an auto request the transfer begins automatically when the DE bit and DME bit are set to 1 The TCR value will be decremented by 1 The actual transfer flows vary by address mode and bus mode 3 When the specified number of transfers have been completed when TCR reaches 0 the transfer ends no...

Page 247: ...t when the NMIF AE and TE bits are all 0 and the DE and DME bits are then set to 1 2 In burst mode DREQ level detection external request or cycle steal mode 3 In burst mode DREQ edge detection external request or auto request mode in burst mode Figure 9 2 DMA Transfer Flow ...

Page 248: ...external request mode 0 1 RXI SCI receive request 1 0 TXI SCI transmit request 1 X X Auto request mode Auto Request When there is no transfer request signal from an external source as in a memory to memory transfer or a transfer between memory and an on chip peripheral module unable to request a transfer the auto request mode allows the DMAC to automatically generate a transfer request signal inte...

Page 249: ...evel using the DS and DL bits of CHCR0 and CHCR1 DS 0 is level detection DS 1 is edge detection for edge detection DL 0 is rising edge DL 1 is falling edge for level detection DL 0 is active low DL 1 is active high The source of the transfer request does not have to be the data transfer source or destination Table 9 5 Selecting the External Request Signal with the DS and DL Bits DRCR DS DL Externa...

Page 250: ...les interrupt request signals are sent not just to the DMAC but to the CPU as well When an on chip peripheral module is specified as the transfer request source set the priority level values in the interrupt priority level registers IPRC IPRE of the interrupt controller INTC at or below the levels set in the I3 I0 bits of the CPU s status register so that the CPU does not accept the interrupt requ...

Page 251: ... Robin Mode Switches the priority of channel 0 and channel 1 shifting their ability to receive transfer requests Each time one byte word longword or 16 bytes is transferred on one channel the priority shifts to the other channel The channel on which the transfer was just finished rotates to the bottom of the priority After reset channel 0 is higher priority than channel 1 Figure 9 5 shows how the ...

Page 252: ...transfer ends channel 0 is already the lowest priority so the order remains the same Figure 9 5 Channel Priority in Round Robin Mode 9 3 4 DMA Transfer Types The DMAC supports all the transfers shown in table 9 7 It can operate in single address mode or dual address mode as defined by how many bus cycles the DMAC takes to access the transfer source and transfer destination The actual transfer oper...

Page 253: ... is the source or destination excludes DMAC BSC and UBC Address Modes Single Address Mode In the single address mode both the transfer source and destination are external one selectable is accessed by a DACK signal while the other is accessed by address In this mode the DMAC performs the DMA transfer in one bus cycle by simultaneously outputting a transfer request acknowledge DACK signal to one ex...

Page 254: ...address mode 1 transfers between external devices with DACK and memory mapped external devices and 2 transfers between external devices with DACK and external memory Transfer requests for both of these must be in the external request DREQ Figure 9 7 shows the DMA transfer timing for the single address mode ...

Page 255: ...n be located externally or internally The DMAC accesses the source in the read cycle and the destination in the write cycle so the transfer is performed in two separate bus cycles The transfer data are temporarily stored in the DMAC Figure 9 8 shows an example of a transfer between two external memories in which data is read from one memory in the read cycle and written to the other memory in the ...

Page 256: ...vices and on chip peripheral modules excluding the DMAC BSC and UBC Access size that is enabled by the register of the on chip peripheral module that is the source or destination excludes DMAC BSC and UBC 6 On chip peripheral modules excluding the DMAC BSC and UBC and on chip peripheral modules excluding the DMAC BSC and UBC Transfer requests can be auto requests external requests or on chip perip...

Page 257: ...er transfer request occurs the bus rights are retrieved from the other bus master and another transfer is performed for one transfer unit When that transfer ends the bus right is passed to the other bus master This is repeated until the transfer end conditions are satisfied The cycle steal mode can be used with all categories of transfer destination transfer source and transfer request source The ...

Page 258: ...been satisfied Burst mode cannot be used when the transfer request originates from the serial communications interface SCI Figure 9 11 shows an example of DMA transfer timing in the burst mode single address mode DREQ level detection Note Single address DREQ level detection Figure 9 11 DMA Transfer Timing in Burst Mode Single Address DREQ Level Detection Refreshes cannot enter during a burst trans...

Page 259: ...ests 2 External requests auto requests and on chip peripheral module requests are all available When the SCI is the transfer request source however the transfer destination or transfer source must both be the SCI 3 If the transfer request source is the SCI cycle steal C only DREQ by edge low active 4 The access size is that permitted by the register of the on chip peripheral module that is the tra...

Page 260: ...sfer Request Acknowledge Signal Output Timing DMA transfer request acknowledge signal DACKn is output synchronous to the DMAC address output specified by the channel control register AM bit of the address bus The timing is normally to have the acknowledge signal become valid when the DMA address output begins and become invalid 0 5 cycles before the address output ends see figure 9 11 The output t...

Page 261: ...Ordinary Space Accesses AM 0 Figure 9 15 DACK Output in Ordinary Space Accesses AM 1 When doing a longword access of a 16 bit external device figure 9 16 or an 8 bit external device figure 9 17 or when doing a word access of an 8 bit external device figure 9 18 the bottom and top addresses are output 2 and 4 times in each DMAC access in order to align the data For all of these addresses the acknow...

Page 262: ...1 L LSB side 2 H MSB side Figure 9 16 DACK Output in Ordinary Space Accesses AM 0 longword access to 16 bit external device Figure 9 17 DACK Output in Ordinary Space Accesses AM 0 longword access to 8 bit external device ...

Page 263: ...nd wait and read address of the DMAC read figure 9 19 Since the synchronous DRAM read has only bursts during a single read an invalid address is output the acknowledge signal however is output on the same timing figure 9 20 At this time the acknowledge signal is extended until the write address is output after the invalid read When AM 1 the acknowledge signal is output across the row address and c...

Page 264: ...set as bank active synchronous DRAM during a burst read the acknowledge signal is output across the read command wait and read address when the row address is the same as the previous address output figure 9 22 When the row address is different from the previous address the acknowledge signal is output across the precharge row address read command wait and read address figure 9 23 ...

Page 265: ...mand wait and read address when the row address is the same as the previous address output figure 9 24 When the row address is different from the previous address the acknowledge signal is output across the precharge row address read command wait and read address figure 9 25 Since the synchronous DRAM read has only bursts during a single read an invalid address is output the acknowledge signal is ...

Page 266: ...ess AM 0 When external memory is set as bank active synchronous DRAM during a write the acknowledge signal is output across the wait and column address when the row address is the same as the previous address output figure 9 26 When the row address is different from the previous address the acknowledge signal is output across the precharge row address wait and column address figure 9 27 ...

Page 267: ... Output in Synchronous DRAM Write Bank Active Different Row Address AM 1 Acknowledge Signal Output when External Memory Is Set as DRAM When external memory is set as DRAM and a row address is output during a read or write the acknowledge signal is output across the row address and column address figures 9 28 9 30 ...

Page 268: ...Hitachi 257 Figure 9 28 DACK Output in Normal DRAM Accesses AM 1 or 0 Figure 9 29 DACK Output in DRAM Burst Accesses Same Row Address AM 1 or 0 ...

Page 269: ...r 0 Acknowledge Signal Output when External Memory Is Set as Pseudo SRAM When external memory is set as pseudo SRAM the acknowledge signal is output synchronous to the DMAC address for both reads and writes figures 9 31 9 33 Figure 9 31 DACK Output in Normal Pseudo SRAM Accesses AM 1 or 0 ...

Page 270: ... Figure 9 33 DACK Output in Pseudo SRAM Burst Accesses Different Row Address AM 1 or 0 Acknowledge Signal Output When External Memory Is Set as Burst ROM When external memory is set as burst ROM the acknowledge signal is output synchronous to the DMAC address no dual writes allowed figure 9 34 ...

Page 271: ...d the memory connected DREQ Pin Input Detection Timing in Cycle Steal Mode In cycle steal mode once a request is detected from the DREQ pin request detection for the next DMA transfer cannot be performed for a certain period of time After request detection has again become possible the detectable cycles continue until a request is detected Figure 9 35 illustrates the timing from the detection of a...

Page 272: ...on DACK output timing Read write dual DMAC cycle single Notes 1 Request detection 2 When a write dual occurs at DACK output the cycle is a DMAC read Otherwise the cycle is a CPU cycle Figure 9 35 DREQ Pin Input Detection Timing in Cycle Steal Mode with Edge Detection 1 Figures 9 36 and 9 37 show are examples of how to change the bus width of an external device ...

Page 273: ...DMAC read Otherwise the cycle is a CPU cycle Figure 9 36 Changing the Bus Size of a 16 Bit External Device Notes 1 Request detection 2 When a write dual occurs at DACK output the cycle is a DMAC read Otherwise the cycle is a CPU cycle Figure 9 37 Changing the Bus Size of an 8 Bit External Device ...

Page 274: ...d out Otherwise the cycle is a CPU cycle 3 When a write dual occurs at DACK output the cycle is a DMAC write The cycle is a DMAC read in when the read in dual occurs Figure 9 38 DREQ Pin Input Detection Timing in Cycle Steal Mode with Edge Detection 2 Requests can be detected 2 cycles after DACK output After that point the request is input to DREQ When input prior to that point requests are someti...

Page 275: ...de Level Detection Requests can be detected for the first time 3 cycles after the bus cycle prior to the DMAC read cycle and detection starts sometime between then and 2 cycles after DACK output figure 9 40 41 This varies with the fluctuations of waits and the like This means that if request output is stopped within 3 cycles from the bus cycle prior to the DMAC read cycle the next DMA transfer is ...

Page 276: ...etection 2 Request detection not established Figure 9 40 Changing the Bus Size of a 16 Bit External Device Notes 1 Request detection 2 Request detection not established Figure 9 41 Changing the Bus Size of an 8 Bit External Device ...

Page 277: ...mode Dual mode DREQ detection method Level detection DACK output timing DMAC write cycle Bus cycle Basic bus cycle Note Request detection Figure 9 42 Timing of DREQ Pin Input Detection in Cycle Steal Mode with Level Detection 2 The next request can be detected 2 cycles after DACK output figure 9 42 ...

Page 278: ...teal Mode with Level Detection 3 Requests can be detected for the first time 3 cycles after the bus cycle prior to the DMAC read cycle and starts sometime between then and 2 cycles after DACK output figure 9 43 This varies with the fluctuations of waits and the like This means that if request output is stopped within 3 cycles from the bus cycle prior to the DMAC read cycle the next DMA transfer is...

Page 279: ...e A1 A2 A3 A4 B1 B2 B3 B4 The second transfer request can be detected 2 cycles after output of acknowledge signal A1 The third transfer request is detected at A3 that is 2 cycles after output of the third acknowledge signal of the first transfer The fourth transfer request is detected 2 cycles after output of B3 Requests thereafter are detected 2 cycles after the third acknowledge signal of each t...

Page 280: ...n Timing in Burst Mode In burst mode the request detection timing differs when DREQ input is detected by edge and when detected by level When DREQ input is detected by edge once a request is detected DMA transfers continue until the conditions for ending the transfers are met regardless of the state of the REQ pin thereafter ...

Page 281: ... signals are output 3 cycles later at the earliest Even when the request signal is dropped within 2 cycles of the output of this acknowledge signal the fourth or fifth requests in figure 9 46 are accepted This means that 4 or 5 DMA transfers are executed even when the request for the 1st acknowledge signal drops out Transfer Width Byte word longword Transfer bus mode Burst mode Transfer address mo...

Page 282: ...s mode Dual mode DREQ detection method Level detection DACK output timing DMAC read Bus cycle Basic bus cycle Note Request detection The points when the 1st and 2nd acceptances occur vary with the type of wait Figure 9 47 Timing of DREQ Pin Input Detection in Burst Mode with Level Detection 2 Acknowledge signals for request signals are output 5 cycles later at the earliest Even when the request si...

Page 283: ...ollowing methods can be used when the request signal is received 1 Control the number of transfers by TCR 2 Use edge for request acceptance 3 Make acknowledge signal output at the DMAC write timing Additional Cautions when Emulators Are Used When DREQ level acceptance is by an emulator in the cycle steal mode the timing of request signal acceptance is 2 cycles after the output of the acknowledge s...

Page 284: ... Figure 9 49 16 Byte Transfer when TCR 2 Conditions for All Channels Ending Simultaneously Transfers on all channels end when either of the following conditions is met The NMIF NMI flag bit or AE address error flag bit is set to 1 in the DMAOR When an NMI interrupt or DMAC address error occurs and the NMIF or AE bit is set to 1 in the DMAOR all channels stop their transfers The DMA source address ...

Page 285: ...ers 64 TCR1 H 0040 Transfer destination address incremented CHCR1 H 4045 Transfer source address fixed Bus mode cycle steal Transfer unit byte DEI interrupt request generated at end of transfer DE 1 Channel priority Fixed 0 1 DME 1 DMAOR H 0001 Transfer request source transfer request signal SCI RXI DRCR1 H 01 Note Check the CPU interrupt level when interrupts are enabled in the SCI 9 5 Notes 1 DM...

Page 286: ...Hitachi 275 7 Do not access the cache address array data array associative purge area 8 To detect the DREQ pin in single address mode use edge detection ...

Page 287: ...276 Hitachi ...

Page 288: ...d as specified 10 1 1 Features The division unit has the following features Performs signed division of 64 bits by 32 bits and 32 bits by 32 bits Handles 32 bit quotient 32 bit remainder Completes operation execution in 39 cycles Controls enables disables of over underflow interrupts Even during the division process instructions not accessing the division unit can be parallel processed 10 1 2 Bloc...

Page 289: ...2 bits DVDNTH Dividend register H DVDNTL Dividend register L DVCR Division control register VCRDIV Vector number setting register DIV Figure 10 1 Division Unit Block Diagram 10 1 3 Register Configuration Table 10 1 lists the register configuration of the division unit ...

Page 290: ... than CONT and VCRDIV are accessed with word accesses they read write undefined values 2 The initial value of VCRDIV is H 0000 asterisks represent undefined values 10 2 Description of Registers 10 2 1 Divisor Register DVSR Bit 31 30 29 3 2 1 0 Bit name Initial value R W R W R W R W R W R W R W R W The divisor register DVSR is a 32 bit read write register in which the divisor for the operation is w...

Page 291: ...ut is also 16 bit accessible It controls enable disable of the overflow interrupt This register is initialized to H 00000000 after a power on reset or manual reset It is not initialized in the standby mode or during module standbys Bits 31 to 2 Reserved These bits cannot be modified and always read 0 Bit 1 OVF interrupt enable OVFIE Selects enable or disable for the OVF interrupt request OVFI upon...

Page 292: ...y mode Bits 31 to 7 Reserved These bits cannot be modified and always read 0 Bits 6 to 0 Interrupt vector numbers Sets the interrupt destination vector number Only bits 6 0 are valid 7 bits 10 2 5 Dividend Register H DVDNTH Bit 31 30 39 3 2 1 0 Bit name Initial value R W R W R W R W R W R W R W R W The dividend register H DVDNTH is a 32 bit read write register in which the upper 32 bits of the div...

Page 293: ...it dividend is set the dividend registers H and L DVDNTH and DVDNTL First set the value in DVDNTH When a value is written to DVDNTL the 64 bit 32 bit operation begins 3 This unit finishes a single operation in 39 cycles starting from the setting of the value in the DVDNTL When an overflow occurs however the operation ends in 6 cycles See section 10 3 3 Handling of Overflows for more information No...

Page 294: ...he division unit and the next three for division 10 4 Notes on Use 10 4 1 Access All accesses to the division unit except DVCR and VCRDIV must be 32 bit reads or writes Word accesses to registers other than DVCR and VCRDIV result in readout or writing of undefined values In the division unit a read instruction is extended for one cycle immediately after an instruction that writes to a register eve...

Page 295: ...verflow generation is detected Sets the maximum for overflows to the plus side or minimum value for overflows to the minus side DVCR Sets the OVF bit Sets the OVF bit VCRDIV Holds the value written Holds the value written DVDNTH Holds the results of operations until overflow generation is detected Holds the results of operations until overflow generation is detected DVDNTL Holds the results of ope...

Page 296: ...e following features Allows selection between four types of counter input clocks Select from external clock or three types of internal clocks φ 8 φ 32 and φ 128 External events can be counted Two independent comparators Two types of waveforms can be output Input capture Select rising edge or falling edge Counter clear can be specified The counter value can be cleared upon compare match A Four type...

Page 297: ...isters A B 16 bits FRC Free running counter 16 bits FICR Input capture register 16 bits TCR Timer control status register 8 bits TIER Timer interrupt enable register 8 bits FTCSR Free running timer control register 8 bits TOCR Timer output compare control register 8 bits Figure 11 1 FRT Block Diagram ...

Page 298: ...unning timer control status register FTCSR R W 1 H 00 HFFFFFE11 Free running counter H FRC H R W H 00 HFFFFFE12 Free running counter L FRC L R W H 00 HFFFFFE13 Output compare register A H OCRA H R W H FF HFFFFFE14 2 Output compare register A L OCRA L R W H FF HFFFFFE15 2 Output compare register B H OCRB H R W H FF HFFFFFE14 2 Output compare register B L OCRB L R W H FF HFFFFFE15 2 Timer control re...

Page 299: ...dule standby function is used 11 2 2 Output Compare Registers A and B OCRA and OCRB Bit 15 14 13 3 2 1 0 Bit name Initial value 1 1 1 1 1 1 1 R W R W R W R W R W R W R W R W The OCR is composed of two 16 bit read write registers OCRA and OCRB The contents of the OCR are always compared to the FRC value When the two values are the same the output compare flags of the FTCSR OCFA and OCFB are set to ...

Page 300: ...n is reliably performed set the pulse width of the input capture input signal to six system clocks φ or more The ICR is initialized to H 0000 by a reset in the standby mode and when the module standby function is used 11 2 4 Timer Interrupt Enable Register TIER Bit 7 6 5 4 3 2 1 0 Bit name ICIE OCIAE OCIBE OVIE Initial value 0 0 0 0 0 0 0 1 R W R W R W R W R W The TIER is an 8 bit read write regis...

Page 301: ... FTCSR is set to 1 Bit 2 OCIBE Description 0 Disables interrupt requests OCIB from the OCFB initial value 1 Enables interrupt requests OCIB from the OCFB Bit 1 Timer overflow interrupt enable OVIE Selects enable disable for interrupt requests from the OVF OVI when the overflow flag OVF of the FTCSR is set to 1 Bit 1 OVIE Description 0 Disables interrupt requests FOVI from the OVF initial value 1 E...

Page 302: ...t to the ICR by the input capture signal Bits 6 to 4 Reserved These bits always read 0 The write value should always be 0 Bit 3 Output compare flag A OCFA Status flag that indicates when the values of the FRC and OCRA match This flag is cleared by the software and set by the hardware It cannot be set by software Bit 3 OCFA Description 0 Clear conditions When OCFA 1 OCFA is read and then 1 written ...

Page 303: ...of FRC and OCRA Bit 0 CCLRA Description 0 Disables FRC clear initial value 1 Clears FRC on compare match A 11 2 6 Timer Control Register TCR Bit 7 6 5 4 3 2 1 0 Bit name IEDGA CKS1 CKS0 Initial value 0 0 0 0 0 0 0 0 R W R W R W R W TCR is an 8 bit read write register that selects the input edge for input capture and selects the input clock for FRC TCR is initialized to H 00 by a reset in the stand...

Page 304: ...VLA OLVLB Initial value 1 1 1 0 0 0 0 0 R W R W R W R W R W R W The TOCR is an 8 bit read write register that selects the output level for output compare enables output compare output and controls switching between access of output compare registers A and B TOCR is initialized to H E0 by resets in the standby mode and by module standby function is used Bits 7 to 5 Reserved These bits always read 1...

Page 305: ...ompare match A signal indicating match of FRC and OCRA Bit 1 OLVLA Description 0 Outputs 0 on compare match A initial value 1 Outputs 1 on compare match A Bit 0 Output level B OLVLB Selects the output level that is output to the output compare B output pin upon compare match B signal indicating match of FRC and OCRB Bit 0 OLVLB Description 0 Outputs 0 on compare match B initial value 1 Outputs 1 o...

Page 306: ...ng from 16 bit Registers The upper byte of data is read which results in the upper byte values being transferred to the CPU The lower byte values are transferred to TEMP The lower byte is then read which results in the lower byte values in TEMP being sent to the CPU When registers of these three types are accessed byte accesses should always be performed twice in upper byte lower byte order The sa...

Page 307: ...296 Hitachi Note For a CPU writing H AA55 to FRC Figure 11 2 FRC Access Operation Write ...

Page 308: ...Hitachi 297 Note For an FRC reading from a CPU H AA55 Figure 11 3 FRC Access Operation Read ...

Page 309: ...φ 32 φ 128 is used Figures 11 4 shows the timing Figure 11 4 Count Timing Internal Clock Operating External Clock Operation Set the CKS1 and CKS0 bits of the TCR to select the external clock The external clock begins counting on the rising edge The pulse width of the external clock must be at least 6 system clocks φ A smaller pulse width results in operation that is not always accurate Figures 11 ...

Page 310: ...t from the output compare output pins FTOA FTOB Figure 11 6 shows the timing for output of output compare A Note Indicates instruction execution by software Figure 11 6 Output Timing for Output Compare A 11 4 3 FRC Clear Timing The FRC can be cleared on compare match A Figure 11 7 shows the timing Figure 11 7 Compare Match A Clear Timing ...

Page 311: ...ows the timing when the rising edge is selected IEDG 1 Figure 11 8 Input Capture Signal Timing Normal When the FICR is read upper byte read and the input capture signal is input the input capture signal is delayed one cycle of the clock that drives the timer Figure 11 9 shows the timing Note When FICR is read and input capture input is input Figure 11 9 Input Capture Signal Timing ...

Page 312: ...Compare Flag OCFA OCFB Set Timing The compare match signal output when OCRA or OCRB matches the FRC value sets OCFA or OCFB to 1 The compare match signal is generated in the last state in which the values matched at the timing for updating the count value that matched the FRC After OCRA or OCRB matches the FRC no compare match signal is generated until the increment lock is generated Figure 11 11 ...

Page 313: ...FFF goes to H 0000 sets the OVF to 1 Figure 11 12 shows the timing Figure 11 12 OVF Setting Timing 11 5 Interrupt Sources There are four FRT interrupt sources of three types ICI OCIA OCIB and OVI Table 11 3 lists priorities for interrupt sources and clearing resets The interrupt enable bits of the TIER are used to ...

Page 314: ...n Priority ICI Interrupt by ICF Highest OCIA OCIB Interrupt by OCFA or OCFB Middle OVI Interrupt by OVF Lowest 11 6 Example of Using the FRT Figure 11 13 illustrates an example of outputting a pulse with 50 duty at any phase differential It is set as follows 1 Set the CCLRA bit of the FTCSR to 1 2 OLVLA and OLVLB bits are inverted by software whenever a compare match occurs Figure 11 13 Example of...

Page 315: ... 2 Contention between FRC Writes and Clears When a counter clear signal is generated with the timing shown in figure 11 14 during the write cycle for the lower byte of the FRC writing does not occur to the FRC and the FRC clear takes priority Figure 11 14 Contention between FRC Write and Clear 3 Contention between FRC Writes and Increments When an increment occurs with the timing shown in figure 1...

Page 316: ...Increment 4 Contention between OCR Writes and Compare Matches When a compare match occurs with the timing shown in figure 11 16 during the write cycle for the lower byte of the OCRA and OCRB the OCR write takes priority and the compare match signal is disabled ...

Page 317: ...writes and FRC operation When an internal clock is used the FRC clock is generated when the falling edge of an internal clock created by dividing the system clock φ is detected When a clock is switched to high before the switching and to low after switching as shown in number 3 of table 11 4 the time of the switch is considered a falling edge and an FRC clock is generated causing the FRC to begin ...

Page 318: ...Hitachi 307 Table 11 4 Internal Clock Switching and FRC Operation No Timing of Rewrite of CKS1 and CKS0 Bits FRC Operation 1 Low to low switch 2 Low to high switch ...

Page 319: ...igh to high switch Note Because the time of switching is considered a falling edge the FRC starts counting up 6 Timer Output FTOA FTOB During a reset that occurs while the power supply is coming up the timer outputs FTOA FTOB will be unreliable until the oscillation stabilizes The initial value is output after the oscillation settling time has elapsed ...

Page 320: ...generated at each counter overflow The WDT is also used when recovering from the standby mode in modifying a clock frequency and in clock pause mode 12 1 1 Features Works in watchdog timer mode or interval timer mode Outputs WDTOVF in the watchdog timer mode When the counter overflows in the watchdog timer mode overflow signal WDTOVF is output externally You can select whether to reset the chip in...

Page 321: ...gister Note The internal reset signal can be generated by setting the register The type of reset can be selected power on or manual resets Figure 12 1 WDT Block Diagram 12 1 3 Pin Configuration Table 12 1 lists the pin configuration Table 12 1 Pin Configuration Pin Abbreviation I O Function Watchdog timer overflow WDTOVF O Outputs the counter overflow signal in the watchdog mode ...

Page 322: ...ptions 12 2 1 Watchdog Timer Counter WTCNT The WTCNT is an eight bit R W upcounter The WTCNT differs from other registers in that it is more difficult to write See section 12 2 4 Register Access for details When the timer enable bit TME in the watchdog timer control status register WTCSR is set to 1 the watchdog timer counter starts counting pulses of an internal clock source selected by clock sel...

Page 323: ... that the WTCNT has overflowed from H FF to H 00 It is not set in the watchdog timer mode Bit 7 OVF Description 0 No overflow of WTCNT in interval timer mode initial value Cleared by reading OVF then writing 0 in OVF 1 WTCNT overflow in the interval timer mode Bit 6 Timer mode select WT IT Selects whether to use the WDT as a watchdog timer or interval timer When the WTCNT overflows the WDT either ...

Page 324: ...0 0 φ 2 initial value 17 8 µs 0 0 1 φ 64 570 8 µs 0 1 0 φ 128 1 1 ms 0 1 1 φ 256 2 2 ms 1 0 0 φ 512 4 5 ms 1 0 1 φ 1024 9 1 ms 1 1 0 φ 4096 36 5 ms 1 1 1 φ 8192 73 0 ms Note The overflow interval listed is the time from when the WTCNT begins counting at H 00 until an overflow occurs 12 2 3 Reset Control Status Register RSTCSR The RSTCSR is an eight bit R W register that controls output of the rese...

Page 325: ...s whether to reset the chip internally if the WTCNT overflows in the watchdog timer mode Bit 6 RSTE Description 0 Not reset when WTCNT overflows initial value LSI not reset internally but WTCNT and WTCSR reset within WDT 1 Reset when WTCNT overflows Bit 5 Reset select RSTS Selects the type of internal reset generated if the WTCNT overflows in the watchdog timer mode Bit 5 RSTS Description 0 Power ...

Page 326: ...TCSR The RSTCSR must be written by a word access to address H FFFFFE82 It cannot be written by byte or longword transfer instructions Procedures for writing 0 in WOVF bit 7 and for writing to RSTE bit 6 and RSTS bit 5 are different as shown in figure 12 3 To write 0 in the WOVF bit the write data must be H A5 in the upper byte and H 00 in the lower byte This clears the WOVF bit to 0 The RSTE and R...

Page 327: ...itten and overflows occur due to a system crash or the like a WDTOVF signal is output figure 12 4 The WDTOVF signal can be used to reset the system The WDTOVF signal is output for 128 φ clock cycles If the RSTE bit in the RSTCSR is set to 1 a signal to reset the chip will be generated internally simultaneous to the WDTOVF signal when WTCNT overflows Either a power on reset or a manual reset can be...

Page 328: ...Hitachi 317 WT IT Timer mode select bit TME Timer enable bit Note Internal reset signal occurs only when the RSTE bit is set Figure 12 4 Operation in the Watchdog Timer Mode ...

Page 329: ...WTCSR must be cleared to 0 to stop the watchdog timer counter before it enters the standby mode The chip cannot enter the standby mode while the TME bit is set to 1 Set bits CKS2 to CKS0 so that the counter overflow interval is equal to or longer than the oscillation settling time See section15 Electrical Characteristics for the oscillation settling time Recovery from the Standby Mode When an NMI ...

Page 330: ... 12 6 Figure 12 6 Timing of Setting the OVF 12 3 5 Timing of Setting the Watchdog Timer Overflow Flag WOVF When the WTCNT overflows the WOVF bit of the RSTCSR is set to 1 and a WDTOVF signal is output When the RSTE bit is set to 1 WTCNT overflow enables an internal reset signal to be generated for the entire chip figure 12 7 Figure 12 7 Timing of Setting the WOVF Bit and Internal Reset ...

Page 331: ...rite and Increment 12 4 2 Changing CKS2 to CKS0 Bit Values If the values of bits CKS2 to CKS0 are altered while the WDT is running the count may increment incorrectly Always stop the watchdog timer by clearing the TME bit to 0 before changing the values of bits CKS2 to CKS0 12 4 3 Changing Watchdog Timer Interval Timer Modes To prevent incorrect operation always stop the watchdog timer by clearing...

Page 332: ... RES input pin To reset the entire system with the WDTOVF signal use the circuit shown in figure 12 9 Figure 12 9 Example of a System Reset Circuit with a WDTOVF Signal 12 4 5 Internal Reset With the Watchdog Timer If the RSTE bit is cleared to 0 in the watchdog timer mode the LSI will not reset internally when a WTCNT overflow occurs but the WTCNT and WTCSR in the WDT will reset ...

Page 333: ...322 Hitachi ...

Page 334: ...y even odd or none Multiprocessor bit one or none Receive error detection parity overrun and framing errors Break detection by reading the RxD level directly when a framing error occurs Clocked synchronous mode Serial data communication is synchronized with a clock signal The SCI can communicate with other chips having a clocked synchronous communication function There is one serial data communica...

Page 335: ...ft register SSR Serial status register TDR Transmit data register BRR Bit rate register Figure 13 1 SCI Block Diagram 13 1 3 Pin Configuration Table 13 1 summarizes the SCI pins by channel Table 13 1 SCI Pins Pin Name Abbreviation Input Output Function Serial clock pin SCK Input output Clock input output Receive data pin RxD Input Receive data input Transmit data pin TxD Output Transmit data outpu...

Page 336: ...o clear the flags 13 2 Register Descriptions 13 2 1 Receive Shift Register The receive shift register RSR receives serial data Data input at the RxD pin is loaded into the RSR in the order received LSB bit 0 first converting the data to parallel form When one byte has been received it is automatically transferred to the RDR The CPU cannot read or write the RSR directly Bit 7 6 5 4 3 2 1 0 Bit name...

Page 337: ...ame R W 13 2 4 Transmit Data Register The transmit data register TDR is an eight bit register that stores data for serial transmission When the SCI detects that the transmit shift register TSR is empty it moves transmit data written in the TDR into the TSR and starts serial transmission Continuous serial transmission is possible by writing the next transmit data in the TDR during serial transmissi...

Page 338: ...he MSB bit 7 of the transmit data register is not transmitted Bit 5 Parity enable PE Selects whether to add a parity bit to transmit data and to check the parity of receive data in the asynchronous mode In the clocked synchronous mode a parity bit is neither added nor checked regardless of the PE setting Bit 5 PE Description 0 Parity bit not added or checked initial value 1 Parity bit added and ch...

Page 339: ...s 1 it is treated as a stop bit but if the second stop bit is 0 it is treated as the start bit of the next incoming character Bit 3 STOP Description 0 One stop bit initial value In transmitting a single bit of 1 is added at the end of each transmitted character 1 Two stop bits In transmitting two bits of 1 are added at the end of each transmitted character Bit 2 Multiprocessor mode MP Selects mult...

Page 340: ...4 3 2 1 0 Bit name TIE RIE TE RE MPIE TEIE CKE1 CKE0 Initial value 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W Bit 7 Transmit interrupt enable TIE Enables or disables the transmit data empty interrupt TXI requested when the transmit data register empty bit TDRE in the serial status register SSR is set to 1 due to transfer of serial transmit data from the TDR to the TSR Bit 7 TIE Descriptio...

Page 341: ...5 Transmit enable TE Enables or disables the SCI serial transmitter Bit 5 TE Description 0 Transmitter disabled initial value The transmit data register empty bit TDRE in the serial status register SSR is locked at 1 1 Transmitter enabled Serial transmission starts when the transmit data register empty TDRE bit in the serial status register SSR is cleared to 0 after writing of transmit data into t...

Page 342: ...rrupts if the TIE and RIE bits in the SCR are set to 1 and allows the FER and ORER bits to be set Bit 2 Transmit end interrupt enable TEIE Enables or disables the transmit end interrupt TEI requested if TDR does not contain new transmit data when the MSB is transmitted Bit 2 TEIE Description 0 Transmit end interrupt TEI requests are disabled initial value 1 Transmit end interrupt TEI requests are ...

Page 343: ...ncy is the same as the bit rate 3 The input clock frequency is 16 times the bit rate 13 2 7 Serial Status Register The serial status register SSR is an 8 bit register containing multiprocessor bit values and status flags that indicate SCI operating status The CPU can always read and write the SSR but cannot write 1 in the status flags TDRE RDRF ORER PER and FER These flags can be cleared to 0 only...

Page 344: ...n of receive errors or by clearing of the RE bit to 0 in the serial control register They retain their previous contents If RDRF is still set to 1 when reception of the next data ends an overrun error ORER occurs and the received data is lost Bit 5 Overrun error ORER Indicates that data reception ended abnormally due to an overrun error Bit 5 ORER Description 0 Receiving is in progress or has ende...

Page 345: ...with parity ended abnormally due to a parity error in the asynchronous mode Bit 3 PER Description 0 Receiving is in progress or has ended normally initial value Clearing the RE bit to 0 in the serial control register does not affect the PER bit which retains its previous value PER is cleared to 0 when the chip is reset or enters standby mode or software reads PER after it has been set to 1 then wr...

Page 346: ...in the asynchronous mode The MPB is a read only bit and cannot be written Bit 1 MPB Description 0 Multiprocessor bit value in receive data is 0 initial value If RE is cleared to 0 when a multiprocessor format is selected the MPB retains its previous value 1 Multiprocessor bit value in receive data is 1 Bit 0 Multiprocessor bit transfer MPBT Stores the value of the multiprocessor bit added to trans...

Page 347: ...e register SMR determines the serial transmit receive bit rate The CPU can always read and write the BRR The BRR is initialized to H FF by a reset or in standby mode Bit 7 6 5 4 3 2 1 0 Bit name Initial value 1 1 1 1 1 1 1 1 R W R W R W R W R W R W R W R W R W Table 13 3 shows examples of BRR settings in the asynchronous mode table 13 4 shows examples of BBR settings in the clocked synchronous mod...

Page 348: ... 16 0 15 0 00 9600 0 3 0 00 0 7 0 00 19200 0 1 0 00 0 3 0 00 31250 0 0 0 00 0 1 0 00 38400 0 0 0 00 0 1 0 00 MHz 12 14 7456 16 19 6608 Bit Rate bits s n N Error n N Error n N Error n N Error 110 1 212 0 03 2 64 0 70 2 70 0 03 2 86 0 31 150 1 155 0 16 1 191 0 00 1 207 0 16 1 255 0 00 300 1 77 0 16 1 95 0 00 1 103 0 16 1 127 0 00 600 0 155 0 16 0 191 0 00 0 207 0 16 0 255 0 00 1200 0 77 0 16 0 95 0 ...

Page 349: ...6 2 79 0 00 2 92 0 46 300 1 129 0 16 1 155 0 16 1 159 0 00 1 186 0 08 600 1 64 0 16 1 77 0 16 1 79 0 00 1 92 0 46 1200 0 129 0 16 0 155 0 16 0 159 0 00 0 186 0 08 2400 0 64 0 16 0 77 0 16 0 79 0 00 0 92 0 46 4800 0 32 1 36 0 38 0 16 0 39 0 00 0 46 0 61 9600 0 15 1 73 0 19 2 34 0 19 0 00 0 22 1 55 19200 0 7 1 73 0 9 2 34 0 9 0 00 0 11 2 68 31250 0 4 0 00 0 5 0 00 0 5 2 40 0 6 2 50 38400 0 3 1 73 0 ...

Page 350: ... 35 100k 0 4 0 9 0 17 250k 0 0 0 1 0 3 500k 0 0 0 1 1M 0 0 2 5M 5M Note Settings with an error of 1 or less are recommended Explanation of symbols Blank No setting possible Setting possible but error occurs Continuous transmit receive not possible The BRR setting is calculated as follows Asynchronous mode N φ 256 2 2n 1 B 106 1 Clocked synchronous mode N φ 32 2 2n 1 B 106 1 B bit rate bit s N BRR ...

Page 351: ... rates in the asynchronous mode when the baud rate generator is being used Tables 13 7 and 13 8 show the maximum rates for external clock input Table 13 6 Maximum Bit Rates for Various Frequencies with Baud Rate Generator Asynchronous Mode Settings MHz Maximum Bit Rate bits s n N 4 31250 0 0 4 9152 38400 0 0 8 62500 0 0 9 8304 76800 0 0 12 93750 0 0 14 7456 115200 0 0 16 125000 0 0 19 6608 153600 ...

Page 352: ...al Input Clock MHz Maximum Bit Rate bits s 8 0 3333 333333 3 16 0 6667 666666 7 24 1 0000 1000000 0 28 7 1 1958 1195833 3 13 3 Operation 13 3 1 Overview For serial communication the SCI has an asynchronous mode in which characters are synchronized individually and a clocked synchronous mode in which communication is synchronized with clock pulses Asynchronous clocked synchronous mode and the commu...

Page 353: ...rator and can output a serial clock signal with a frequency matching the bit rate When an external clock is selected the external clock input must have a frequency 16 times the bit rate The on chip baud rate generator is not used Clocked Synchronous Mode The communication format has a fixed eight bit data length In receiving it is possible to detect overrun errors ORER An internal or external cloc...

Page 354: ...it 1 2 bits Clocked synchronous 1 8 bit Not set Not set None Note Asterisks in the table indicate don t care bits Table 13 10 SMR and SCR Settings and SCI Clock Source Selection SMR SCR Settings SCI Transmit Receive Clock Mode Bit 7 C A Bit 1 CKE1 Bit 0 CKE0 Clock Source SCK Pin Function Asynchronous 0 0 0 Internal SCI does not use the SCK pin mode 1 Outputs a clock with frequency matching the bit...

Page 355: ...eral format of asynchronous serial communication In asynchronous serial communication the communication line is normally held in the mark high state The SCI monitors the line and starts serial communication when the line goes to the space low state indicating a start bit One serial character consists of a start bit low data LSB first parity bit high or low and stop bit high in that order When rece...

Page 356: ... 7 Bit data STOP STOP 1 1 0 0 START 7 Bit data P STOP 1 1 0 1 START 7 Bit data P STOP STOP 0 1 0 START 8 Bit data MPB STOP 0 1 1 START 8 Bit data MPB STOP STOP 1 1 0 START 7 Bit data MPB STOP 1 1 1 START 7 Bit data MPB STOP STOP Don t care bits Note START Start bit STOP Stop bit P Parity bit MPB Multiprocessor bit Clock An internal clock generated by the on chip baud rate generator or an external ...

Page 357: ...ta register RDR which retain their previous contents When an external clock is used the clock should not be stopped during initialization or subsequent operation SCI operation becomes unreliable if the clock is stopped Figure 13 4 is a sample flowchart for initializing the SCI The procedure for initializing the SCI is as follows 1 Select the communication format in the serial mode register SMR 2 W...

Page 358: ...te read the serial status register SSR check that the TDRE bit is 1 then write transmit data in the transmit data register TDR and clear TDRE to 0 2 To continue transmitting serial data read the TDRE bit to check whether it is safe to write if it reads 1 if so write data in TDR then clear TDRE to 0 When the DMAC is started by a transmit data empty interrupt request TXI in order to write data in TD...

Page 359: ...348 Hitachi Note Circled numbers refer to the preceding procedure Figure 13 5 Sample Flowchart for Transmitting Serial Data ...

Page 360: ...t bits of data are output LSB first c Parity bit or multiprocessor bit one parity bit even or odd parity or one multiprocessor bit is output Formats in which neither a parity bit nor a multiprocessor bit is output can also be selected d Stop bit one or two 1 bits stop bits are output e Marking output of 1 bits continues until the start bit of the next transmit data 3 The SCI checks the TDRE bit wh...

Page 361: ...o 0 Receiving cannot resume if ORER PER or FER remain set to 1 When a framing error occurs the RxD pin can be read to detect the break state 2 SCI status check and receive data read read the serial status register SSR check that RDRF is set to 1 then read receive data from the receive data register RDR and clear RDRF to 0 The RXI interrupt can also be used to determine if the RDRF bit has changed ...

Page 362: ...Hitachi 351 Note Circled numbers refer to the preceding procedure Figure 13 7 Sample Flowchart for Receiving Serial Data ...

Page 363: ...e preceding procedure Figure 13 7 Sample Flowchart for Receiving Serial Data cont In receiving the SCI operates as follows 1 The SCI monitors the receive data line When it detects a start bit 0 the SCI synchronizes internally and starts receiving ...

Page 364: ...urther receiving is disabled The RDRF bit is not set to 1 Be sure to clear the error flags 4 After setting RDRF to 1 if the receive data full interrupt enable bit RIE is set to 1 in the SCR the SCI requests a receive data full interrupt RXI If one of the error flags ORER PER or FER is set to 1 and the receive data full interrupt enable bit RIE in the SCR is also set to 1 the SCI requests a receive...

Page 365: ...ycles The transmitting processor starts by sending the ID of the receiving processor with which it wants to communicate as data with the multiprocessor bit set to 1 Next the transmitting processor sends transmit data with the multiprocessor bit cleared to 0 Receiving processors skip incoming data until they receive data with the multiprocessor bit set to 1 When they receive data with the multiproc...

Page 366: ...ata is listed below 1 SCI status check and transmit data write read the serial status register SSR check that the TDRE bit is 1 then write transmit data in the transmit data register TDR Also set MPBT multiprocessor bit transfer to 0 or 1 in SSR Finally clear TDRE to 0 2 To continue transmitting serial data read the TDRE bit to check whether it is safe to write if it reads 1 if so write data in TD...

Page 367: ...356 Hitachi Note Circled numbers refer to the preceding procedure Figure 13 10 Sample Flowchart for Transmitting Multiprocessor Serial Data ...

Page 368: ...n the following order from the TxD pin a Start bit one 0 bit is output b Transmit data seven or eight bits are output LSB first c Multiprocessor bit one multiprocessor bit MPBT value is output d Stop bit one or two 1 bits stop bits are output e Marking output of 1 bits continues until the start bit of the next transmit data 3 The SCI checks the TDRE bit when it outputs the stop bit If TDRE is 0 th...

Page 369: ... read data from the receive data register RDR and compare with the processor s own ID If the ID does not match the receive data set MPIE to 1 again and clear RDRF to 0 If the ID matches the receive data clear RDRF to 0 3 Receive error handling and break detection if a receive error occurs figure 13 12 continued read the ORER and FER bits in SSR to identify the error After executing the necessary e...

Page 370: ...Hitachi 359 Figure 13 12 Sample Flowchart for Receiving Multiprocessor Serial Data ...

Page 371: ...360 Hitachi Figure 13 12 Sample Flowchart for Receiving Multiprocessor Serial Data cont ...

Page 372: ...361 Figure 13 13 shows an example of SCI receive operation using a multiprocessor format Example Own ID does not match data 8 bit data with multiprocessor bit and one stop bit Figure 13 13 SCI Receive Operation ...

Page 373: ...ation with clock pulses This mode is suitable for high speed serial communication The SCI transmitter and receiver are independent so full duplex communication is possible while sharing the same clock The transmitter and receiver are also double buffered so continuous transmitting or receiving is possible by reading or writing data while transmitting or receiving is in progress Figure 13 14 shows ...

Page 374: ... clock input from the SCK pin can be selected as the SCI transmit receive clock The clock source is selected by the C A bit in the serial mode register SMR and bits CKE1 and CKE0 in the serial control register SCR See table 13 9 When the SCI operates on an internal clock it outputs the clock signal at the SCK pin Eight clock pulses are output per transmitted or received character When the SCI is n...

Page 375: ...smit end interrupt TEI is requested at this time 4 After the end of serial transmission the SCK pin is held in the high state Figure 13 15 Example of SCI Transmit Operation Transmitting and Receiving Data SCI Initialization clocked synchronous mode Before transmitting or receiving software must clear the TE and RE bits to 0 in the serial control register SCR then initialize the SCI as follows When...

Page 376: ... bit then set TE or RE in the serial control register SCR to 1 Also set RIE TIE TEIE and MPIE Note High except in continuous transmitting or receiving Figure 13 16 Sample Flowchart for SCI Initialization Transmitting Serial Data Clocked Synchronous Mode Figure 13 17 shows a sample flowchart for transmitting serial data The procedure for transmitting serial data is listed below 1 SCI status check a...

Page 377: ...Figure 13 17 Sample Flowchart for Serial Transmitting Receiving Serial Data Clocked Synchronous Mode Figure 13 18 shows a sample flowchart for receiving serial data When switching from the asynchronous mode to the clocked synchronous mode make sure that ORER PER and FER are cleared to 0 If PER or FER is set to 1 the RDRF bit will not be set and both transmitting and receiving will be disabled Figu...

Page 378: ...egister SSR check that RDRF is set to 1 then read receive data from the receive data register RDR and clear RDRF to 0 The RXI interrupt can also be used to determine if the RDRF bit has changed from 0 to 1 3 To continue receiving serial data read RDR and clear RDRF to 0 before the frame MSB bit 7 of the current frame is received If the DMAC is started by a receive data full interrupt RXI to read R...

Page 379: ...ion In receiving the SCI operates as follows 1 The SCI synchronizes with serial clock input or output and initializes internally 2 Receive data is shifted into the RSR in order from the LSB to the MSB After receiving the data the SCI checks that RDRF is 0 so that receive data can be loaded from the RSR into the ...

Page 380: ...lear TDRE to 0 The TXI interrupt can also be used to determine if the TDRE bit has changed from 0 to 1 2 Receive error handling if a receive error occurs read the ORER bit in SSR to identify the error After executing the necessary error processing clear ORER to 0 Transmitting receiving cannot resume if ORER remains set to 1 3 SCI status check and receive data read read the serial status register S...

Page 381: ...itachi Note In switching from transmitting or receiving to simultaneous transmitting and receiving clear both TE and RE to 0 then set both TE and RE to 1 Figure 13 20 Sample Flowchart for Serial Transmitting ...

Page 382: ... is requested when the TEND bit in the SSR is set to 1 TEI cannot start the DMAC Where the TXI interrupt indicates that transmit data writing is enabled the TEI interrupt indicates that the transmit operation is complete Table 13 13 SCI Interrupt Sources Interrupt Source Description DMAC Availability Priority ERI Receive error ORER PER or FER No High RXI Receive data full RDRF Yes TXI Transmit dat...

Page 383: ...FER is detected In the break state the input from the RxD pin consists of all 0s so FER is set and the parity error flag PER may also be set In the break state the SCI receiver continues to operate so if the FER bit is cleared to 0 it will be set to 1 again Sending a Break Signal When TE is cleared to 0 a 1 is output from the TxD pin Receive Error Flags and Transmitter Operation clocked synchronou...

Page 384: ... L 0 5 F D 0 5 N 1 F 100 M Receive margin N Ratio of clock frequency to bit rate N 16 D Clock duty cycle D 0 1 0 L Frame length L 9 12 F Absolute deviation of clock frequency From equation 1 if F 0 and D 0 5 the receive margin is 46 875 as given by equation 2 Equation 2 D 0 5 F 0 M 0 5 1 2 16 100 46 875 This is a theoretical value A reasonable margin to allow in system designs is 20 30 ...

Page 385: ...control register CHCR Note During external clock operation an error may occur if t is 4φ or less Figure 13 22 Clocked Synchronous Transmitting Example with DMAC Cautions for Clocked Synchronous External Clock Mode Set TE RE 1 only when the external clock SCK is 1 Do not set TE RE 1 until at least four clocks after the external clock SCK has changed from 0 to 1 When receiving RDRF is 1 when RE is s...

Page 386: ...1 Power Down Modes In addition to the sleep mode and standby mode the SH7095 also has a third power down mode the module standby function which halts the DMAC multiplication unit division unit free running timer and SCI on chip peripheral modules Table 14 1 describes the transition conditions for entering the modes from the program execution state as well as the CPU and peripheral module states in...

Page 387: ...nstruction with SBY bit set to 1 in SBYCR Halt Halt Held Halt Held or high impedance 1 NMI interrupt 2 Power on reset 3 Manual reset Module standby function MSTP bit becomes 1 Run Run MULT is held Run When MSTP bit is 1 the supply of the clock to the affected module is halted Pins in FRT and SCI are initialized and others operate Make MSTP bit 0 14 1 2 Register Table 14 2 lists the register config...

Page 388: ...dby mode Bit 6 Port high impedance HIZ In the standby mode this bit selects whether to keep the output pin at high impedance or hold the output When HIZ 0 initial state the specified pin holds output When HIZ 1 the pin is in high impedance state See Appendix A 1 Pin States during Resets Power Down States and Bus Release State for which pin is controled Bit 6 HIZ Description 0 Holds pin state in st...

Page 389: ...ription 0 DIVU running Initial value 1 Clock supply to DIVU halted Bit 1 Module stop 1 MSTP1 Specifies halting the clock supply to the 16 bit free running timer FRT an on chip peripheral module When MSTP1 bit is set to 1 the supply of the clock to the FRT is halted When the clock halts all FRT registers except the interrupt vector which holds the previous value are initialized When MSTP1 is cleare...

Page 390: ...ority level is equal to or less than the mask level set in the CPU s status register SR or if an interrupt by an on chip peripheral module is disabled at the peripheral module Cancellation by a DMA Address Error If a DMA address error occurs the sleep mode is canceled and DMA address error exception processing is executed Cancellation by a Power On Reset A power on reset cancels the sleep mode Can...

Page 391: ...trol status register Reset control status register Timer counter 16 bit free running timer FRT All registers Serial communication interface SCI All registers Others Standby control register Frequency setting register 14 4 2 Canceling the Standby Mode The standby mode is canceled by an NMI interrupt a power on reset or a manual reset Cancellation by an NMI Can be hot started by the on chip WDT When...

Page 392: ...e routine the standby bit SBY of the standby control register SBYCR is set to 1 and a SLEEP instruction is executed the standby mode is entered The standby mode is cleared the next time the NMI pin level changes from low level to high level Figure 14 1 NMI Timing in the Standby Mode Application Example 14 4 4 Clock Pause Function When the clock is input from the CKIO pin the clock frequency can be...

Page 393: ...celed the WDT starts to count up at the falling edge or rising edge of the NMI pin when the NMIE bit of the INTC is set 7 When a frequency is modified the CKPACK pin becomes high after the time set by the WDT and the clock pause function informs the outside that the LSI can again be operated the standby mode is canceled 8 When a clock is halted the clock is applied again to the CKIO pin and NMI in...

Page 394: ... is input The clock is output as well as by cancellation by power on reset and manual reset Input power on reset and manual reset for the equal to or more time than the oscillation setting time 14 5 Module Standby Function 14 5 1 Transition to Module Standby Function By setting the standby control register MSTP4 MSTP0 bits to 1 the supply of clock to the corresponding registers can be halted table...

Page 395: ...384 Hitachi ...

Page 396: ...m ratings Table 15 1 Absolute Maximum Ratings Item Symbol Rating Unit Power supply voltage VCC 0 3 to 7 0 V Input voltage Vin 0 3 to VCC 0 3 V Operating temperature Topr 200 to 75 C Storage temperature Tstg 55 to 125 C Caution Operating the chip in excess of the absolute maximum rating may result in permanent damage ...

Page 397: ... 0 3 0 5 During standby level MD0 0 3 0 8 V Normal operation voltage Other input pins 0 3 0 8 V Input leak RES Iin 1 0 µA Vin 0 5 to VCC 0 5 V current NMI MD5 MD0 1 0 µA Vin 0 5 to VCC 0 5 V Other input pins 1 0 µA Vin 0 5 to VCC 0 5 V 3 state leak current while off A26 A0 D31 D0 BS CS3 CS0 RD WR RAS CAS WE3 WE0 RD IVECF ISTI 1 0 µA Vin 0 5 to VCC 0 5 V Output All output pins VOH VCC 0 5 V IOH 200...

Page 398: ... Connect PLLVCC to VCC and PLLVSS to VSS 2 Current consumption values shown are the values at which all output pins are without load under conditions of VIH min VCC 0 5 V VIL max 0 5 V Table 15 3 Permitted Output Current Values Conditions VCC 5 0 10 Ta 20 to 75 C Item Symbol Min Typ Max Unit Output low level permissible current per pin IOL 2 0 mA Output low level permissible current total IOL 80 m...

Page 399: ...ut frequency fEX 4 8 MHz 15 2 EXTAL clock input cycle time tEXcyc 125 250 ns EXTAL clock input low level pulse width tEXL 50 ns EXTAL clock input high level pulse width tEXH 50 ns EXTAL clock input rise time tEXR 5 ns EXTAL clock input clock fall time tEXF 5 ns Power on oscillation settling time tOSC1 10 ms 15 3 Software standby oscillation settling time 1 tOSC2 10 ms 15 4 Software standby oscilla...

Page 400: ...i 389 Note External clock input from EXTAL pin Figure 15 2 EXTAL Clock Input Timing Note Oscillation settling time when on chip clock pulse generator is used Figure 15 3 Oscillation Settling Time at Power On ...

Page 401: ...n on chip clock pulse generator is used Figure 15 4 Oscillation Settling Timing at Standby Return via RESET Note Oscillation settling time when on chip clock pulse generator is used Figure 15 5 Oscillation Settling Timing at Standby Return via NMI ...

Page 402: ...Hitachi 391 Figure 15 6 PLL Synchronization Settling Timing ...

Page 403: ... time tIRLH 10 ns BRLS setup time 1 PLL on tBLSS1 1 2 tcyc 9 ns 15 10 BRLS hold time 1 PLL on tBLSH1 9 1 2 tcyc ns BGR delay time 1 PLL on tBGRD1 1 2 tcyc 18 ns BRLS setup time 1 PLL on 1 4 cycle delay tBLSS1 1 4 tcyc 9 ns 15 10 BRLS hold time 1 PLL on 1 4 cycle delay tBLSH1 9 1 4 tcyc ns BGR delay time 1 PLL on 1 4 cycle delay tBGRD1 3 4 tcyc 18 ns BRLS setup time 2 PLL off tBLSS2 9 ns 15 11 BRLS...

Page 404: ...Bus tri state delay time 1 PLL on tBOFF1 0 25 ns 15 10 Bus buffer on time 1 PLL on tBON1 0 18 ns 15 12 Bus tri state delay time 1 PLL on 1 4 cycle delay tBOFF1 1 4 tcyc 1 4 tcyc 25 ns 15 10 Bus buffer on time 1 PLL on 1 4 cycle delay tBON1 1 4 tcyc 1 4 tcyc 18 ns 15 12 Bus tri state delay time 1 PLL off tBOFF1 0 30 ns 15 11 Bus buffer on time 1 PLL off tBON1 0 25 ns 15 13 Bus tri state delay time ...

Page 405: ...394 Hitachi Figure 15 7 Reset Input Timing Figure 15 8 Interrupt Signal Input Timing With PLL1 Off ...

Page 406: ...Hitachi 395 Figure 15 9 Interrupt Signal Input Timing With PLL1 On Figure 15 10 Bus Release Timing Master Mode With PLL1 On ...

Page 407: ...396 Hitachi Figure 15 11 Bus Release Timing Master Mode With PLL1 Off Figure 15 12 Bus Release Timing Slave Mode With PLL1 On ...

Page 408: ...Hitachi 397 Figure 15 13 Bus Release Timing Slave Mode With PLL1 Off ...

Page 409: ...5 52 15 66 15 68 Read data setup time 1 tRDS1 1 2 tcyc 10 ns 15 14 15 40 15 52 15 66 15 68 Read data setup time 3 SDRAM tRDS3 1 2 tcyc 8 ns 15 20 Read data hold time 2 tRDH2 0 ns 15 14 15 66 Read data hold time 4 SDRAM tRDH4 0 ns 15 20 Read data hold time 5 DRAM tRDH5 0 ns 15 40 Read data hold time 6 PSRAM tRDH6 0 ns 15 52 Read data hold time 7 interrupt vector tRDH7 0 ns 15 68 Write enable delay ...

Page 410: ...tRASD2 1 2 tcyc 3 1 2 tcyc 18 ns 15 40 CAS delay time 1 SDRAM tCASD1 18 ns 15 20 CAS delay time 2 DRAM tCASD2 1 2 tcyc 3 1 2 tcyc 18 ns 15 40 DQM delay time tDQMD 18 ns 15 20 CKE delay time tCKED 21 ns 15 37 CE delay time 1 tCED1 1 2 tcyc 3 1 2 tcyc 18 ns 15 52 OE delay time 1 tOED1 1 2 tcyc 18 ns 15 52 IVECF delay time tIVD 18 ns 15 68 Address input setup time tASIN 14 ns 15 71 Address input hold...

Page 411: ... 40 15 52 15 66 15 68 Read data setup time 1 tRDS1 1 4 tcyc 10 ns 15 14 15 40 15 52 15 66 15 68 Read data setup time 3 SDRAM tRDS3 1 4 tcyc 8 ns 15 20 Read data hold time 2 tRDH2 0 ns 15 14 15 66 Read data hold time 4 SDRAM tRDH4 0 ns 15 20 Read data hold time 5 DRAM tRDH5 0 ns 15 40 Read data hold time 6 PSRAM tRDH6 0 ns 15 52 Read data hold time 7 interrupt vector tRDH7 0 ns 15 68 Write enable d...

Page 412: ...tcyc 3 3 4 tcyc 18 ns 15 40 CAS delay time 1 SDRAM tCASD1 1 4 tcyc 18 ns 15 20 CAS delay time 2 DRAM tCASD2 3 4 tcyc 3 3 4 tcyc 18 ns 15 40 DQM delay time tDQMD 1 4 tcyc 18 ns 15 20 CKE delay time tCKED 1 4 tcyc 21 ns 15 37 CE delay time 1 tCED1 3 4 tcyc 3 3 4 tcyc 18 ns 15 52 OE delay time 1 tOED1 3 4 tcyc 18 ns 15 52 IVECF delay time tIVD 1 4 tcyc 18 ns 15 68 Address input setup time tASIN 14 1 ...

Page 413: ...ata setup time 2 tRDS2 10 ns 15 16 15 38 15 47 15 60 15 67 15 69 Read data hold time 2 tRDH2 0 ns 15 16 15 67 Read data hold time 3 tRDH3 15 ns 15 16 15 38 15 47 15 60 15 67 Read data hold time 5 DRAM tRDH5 0 ns 15 47 Read data hold time 6 PSRAM tRDH6 0 ns 15 60 Read data hold time 7 interrupt vector tRDH7 0 ns 15 69 Write enable delay time 2 tWED2 10 25 ns 15 17 15 61 Write data delay time tWDD 1...

Page 414: ...ES1 0 ns 15 16 Address setup time 1 tAS1 0 ns 15 17 Address setup time 2 tAS2 3 ns 15 60 Address hold time 2 tAH2 0 ns 15 17 Row address setup time tASR 3 ns 15 47 Column address setup time tASC 3 ns 15 47 Write command setup time tWCS 3 ns 15 48 Write data setup time tWDS 3 ns 15 48 Address input setup time tASIN 15 ns 15 71 Address input hold time tAHIN 10 ns 15 71 BS input setup time tBSS 15 ns...

Page 415: ...Read data setup time 2 tRDS2 12 ns 15 16 15 38 15 47 15 60 15 67 15 69 Read data hold time 2 tRDH2 0 ns 15 16 15 67 Read data hold time 3 SDRAM tRDH3 1 2 tcyc ns 15 38 Read data hold time 5 DRAM tRDH5 0 ns 15 47 Read data hold time 6 PSRAM tRDH6 0 ns 15 60 Read data hold time 7 interrupt vector tRDH7 0 ns 15 69 Write enable delay time 2 tWED2 3 18 ns 15 17 15 61 Write data delay time tWDD 3 18 ns ...

Page 416: ...E delay time tCKED 21 ns 15 37 CE delay time 2 tCED2 3 18 ns 15 60 OE delay time 2 tOED2 18 ns 15 60 IVECF delay time tIVD 18 ns 15 69 Address input setup time tASIN 14 ns 15 71 Address input hold time tAHIN 3 ns 15 71 BS input setup time tBSS 15 ns 15 71 BS input hold time tBSH 3 ns 15 71 Read write input setup time tRWS 15 ns 15 71 Read write input hold time tRWH 3 ns 15 71 Data buffer on time t...

Page 417: ...tted lines indicate a synchronous DRAM is connected 2 tRDH2 is defined by the faster of CSn and RD 3 The DACKn waveform shown is for the case where active high has been specified Figure 15 14 Basic Read Cycle No Waits PLL On ...

Page 418: ...Hitachi 407 Notes 1 Dotted lines indicate a synchronous DRAM is connected 2 The DACKn waveform shown is for the case where active high has been specified Figure 15 15 Basic Write Cycle No Waits PLL On ...

Page 419: ...ted lines indicate a synchronous DRAM is connected 2 tRDH2 is defined by the faster of CSn and RD 3 The DACKn waveform shown is for the case where active high has been specified Figure 15 16 Basic Read Cycle No Waits PLL Off ...

Page 420: ...Hitachi 409 Notes 1 Dotted lines indicate a synchronous DRAM is connected 2 The DACKn waveform shown is for the case where active high has been specified Figure 15 17 Basic Write Cycle No Waits PLL Off ...

Page 421: ...410 Hitachi Notes 1 Dotted lines indicate a synchronous DRAM is connected 2 The DACKn waveform shown is for the case where active high has been specified Figure 15 18 Basic Bus Cycle 1 Wait Cycle ...

Page 422: ...Hitachi 411 Notes 1 Dotted lines indicate a synchronous DRAM is connected 2 The DACKn waveform shown is for the case where active high has been specified Figure 15 19 Basic Bus Cycle External Wait Input ...

Page 423: ...nes indicate a synchronous DRAM in another CS space is connected 2 The DACKn waveform shown is for the case where active high has been specified Figure 15 20 Synchronous DRAM Read Bus Cycle PLL On 4 Bursts CAS Latency 1 RCD 1 Cycle ...

Page 424: ...Hitachi 413 Note Dotted lines indicate a synchronous DRAM in another CS space is connected Figure 15 21 Synchronous DRAM Single Read Bus Cycle RCD 1 Cycle CAS Latency 1 Cycle Bursts 4 PLL On ...

Page 425: ...nes indicate a synchronous DRAM in another CS space is connected 2 The DACKn waveform shown is for the case where active high has been specified Figure 15 22 Synchronous DRAM Read Bus Cycle RCD 2 Cycle CAS Latency 2 Cycle Bursts 4 ...

Page 426: ...Hitachi 415 Note 1 The DACKn waveform shown is for the case where active high has been specified Figure 15 23 Synchronous DRAM Read Bus Cycle Bank Active Same Row Access CAS Latency 1 Cycle ...

Page 427: ...416 Hitachi Note 1 The DACKn waveform shown is for the case where active high has been specified Figure 15 24 Synchronous DRAM Read Bus Cycle Bank Active Same Row Access CAS Latency 1 Cycle ...

Page 428: ...417 Note 1 The DACKn waveform shown is for the case where active high has been specified Figure 15 25 Synchronous DRAM Read Bus Cycle Bank Active Different Row Access TRP 1 Cycle RCD 1 Cycle CAS Latency 1 Cycle ...

Page 429: ...hi Note 1 The DACKn waveform shown is for the case where active high has been specified Figure 15 26 Synchronous DRAM Read Bus Cycle Bank Active Different Row Access TRP 2 Cycles RCD 1 Cycle CAS Latency 1 Cycle ...

Page 430: ...ed lines indicate a synchronous DRAM in another CS space is accessed 2 The DACKn waveform shown is for the case where active high has been specified Figure 15 27 Synchronous DRAM Read Bus Cycle RCD 1 Cycle TRWL 1 Cycle PLL On ...

Page 431: ...otted lines indicate a synchronous DRAM in another CS space is accessed 2 The DACKn waveform shown is for the case where active high has been specified Figure 15 28 Synchronous DRAM Read Bus Cycle RCD 2 Cycles TRWL 2 Cycles ...

Page 432: ...Hitachi 421 Note 1 The DACKn waveform shown is for the case where active high has been specified Figure 15 29 Synchronous DRAM Write Bus Cycle Bank Active Same Row Access ...

Page 433: ...422 Hitachi Note 1 The DACKn waveform shown is for the case where active high has been specified Figure 15 30 Synchronous DRAM Consecutive Write Cycle Bank Active Same Row Access ...

Page 434: ...Hitachi 423 Note 1 The DACKn waveform shown is for the case where active high has been specified Figure 15 31 Synchronous DRAM Write Bus Cycle Bank Active Different Row Access TRP 1 Cycle RCD 1 Cycle ...

Page 435: ...424 Hitachi Note 1 The DACKn waveform shown is for the case where active high has been specified Figure 15 32 Synchronous DRAM Write Bus Cycle Bank Active Different Row Access TRP 2 Cycles RCD 2 Cycles ...

Page 436: ...Hitachi 425 Figure 15 33 Synchronous DRAM Mode Register Write Cycle TRP 1 Cycle ...

Page 437: ...426 Hitachi Figure 15 34 Synchronous DRAM Mode Register Write Cycle TRP 2 Cycles ...

Page 438: ...Hitachi 427 Note Always put in a precharge cycle before the auto refresh cycle The TRP determines how many cycles prior it should be placed Figure 15 35 Synchronous DRAM Auto Refresh Cycle TRAS 2 Cycles ...

Page 439: ...428 Hitachi Figure 15 36 Synchronous DRAM Auto Refresh Cycle Shown From Precharge Cycle TRP 1 Cycle TRAS 2 Cycles ...

Page 440: ...Hitachi 429 Note Always put in a precharge cycle before the auto refresh cycle The TRP determines how many cycles prior it should be placed Figure 15 37 Synchronous DRAM Self Refresh Cycle TRAS 2 ...

Page 441: ...te a synchronous DRAM in another CS space is connected 2 The DACKn waveform shown is for the case where active high has been specified Figure 15 38 Synchronous DRAM Read Bus Cycle RCD 1 Cycle CAS Latency 1 Cycle TRP 1 Cycle Bursts 4 PLL Off ...

Page 442: ...d lines indicate a synchronous DRAM in another CS space is connected 2 The DACKn waveform shown is for the case where active high has been specified Figure 15 39 Synchronous DRAM Write Bus Cycle RCD 1 Cycle TRP 1 Cycle PLL Off ...

Page 443: ...hi Notes 1 tRDH5 is defined by the faster of RD and CASxx rise 2 The DACKn waveform shown is for the case where active high has been specified Figure 15 40 DRAM Read Cycle TRP 1 Cycle RCD 1 Cycle No Waits PLL On ...

Page 444: ...Hitachi 433 Note 1 The DACKn waveform shown is for the case where active high has been specified Figure 15 41 DRAM Write Cycle TRP 1 Cycle RCD 1 Cycle No Waits PLL On ...

Page 445: ...434 Hitachi Note 1 The DACKn waveform shown is for the case where active high has been specified Figure 15 42 DRAM Bus Cycle TRP 2 Cycles RCD 2 Cycles 1 Wait ...

Page 446: ...Hitachi 435 Note 1 The DACKn waveform shown is for the case where active high has been specified Figure 15 43 DRAM Bus Cycle TRP 1 Cycle RCD 1 Cycle External Wait Input ...

Page 447: ...Notes 1 tRDH5 is defined by the faster of RD and CASxx rise 2 The DACKn waveform shown is for the case where active high has been specified Figure 15 44 DRAM Burst Read Cycle TRP 1 Cycle RCD 1 Cycle No Waits PLL On ...

Page 448: ...Hitachi 437 Note 1 The DACKn waveform shown is for the case where active high has been specified Figure 15 45 DRAM Burst Write Cycle TRP 1 Cycle RCD 1 Cycle No Waits PLL On ...

Page 449: ...438 Hitachi Figure 15 46 DRAM CAS Before RAS Refresh Cycle TRP 1 Cycle TRAS 2 Cycles PLL On ...

Page 450: ...39 Notes 1 tRDH5 is defined by the faster of RD and CASxx rise 2 The DACKn waveform shown is for the case where active high has been specified Figure 15 47 DRAM Bus Cycle TRP 1 Cycle RCD 1 Cycle No Waits PLL On ...

Page 451: ...440 Hitachi Note 1 The DACKn waveform shown is for the case where active high has been specified Figure 15 48 DRAM Write Cycle TRP 1 Cycle RCD 1 Cycle No Waits PLL Off ...

Page 452: ...otes 1 tRDH5 is defined by the faster of RD and CASxx rise 2 The DACKn waveform shown is for the case where active high has been specified Figure 15 49 DRAM Burst Read Cycle TRP 1 Cycle RCD 1 Cycle No Waits PLL Off ...

Page 453: ...442 Hitachi Note 1 The DACKn waveform shown is for the case where active high has been specified Figure 15 50 DRAM Burst Write Cycle TRP 1 Cycle RCD 1 Cycle No Waits PLL Off ...

Page 454: ...Hitachi 443 Figure 15 51 DRAM CAS Before RAS Refresh Cycle TRP 1 Cycle TRAS 2 Cycles PLL Off ...

Page 455: ...444 Hitachi Note 1 The DACKn waveform shown is for the case where active high has been specified Figure 15 52 Pseudo SRAM Read Cycle PLL On TRP 1 Cycles TRCD 1 Cycle No Waits ...

Page 456: ...Hitachi 445 Note 1 The DACKn waveform shown is for the case where active high has been specified Figure 15 53 Pseudo SRAM Write Cycle PLL On TRP 1 Cycle TRCD 1 Cycle No Waits ...

Page 457: ...446 Hitachi Note 1 The DACKn waveform shown is for the case where active high has been specified Figure 15 54 Pseudo SRAM Bus Cycle TRP 2 Cycles TRCD 2 Cycles 1 Wait ...

Page 458: ...Hitachi 447 Note 1 The DACKn waveform shown is for the case where active high has been specified Figure 15 55 Pseudo SRAM Bus Cycle TRP 1 Cycle TRCD 1 Cycle External Wait Input ...

Page 459: ...448 Hitachi Note 1 The DACKn waveform shown is for the case where active high has been specified Figure 15 56 Pseudo SRAM Read Cycle Nibble Access PLL On TRP 1 Cycle No Waits ...

Page 460: ...Hitachi 449 Note 1 The DACKn waveform shown is for the case where active high has been specified Figure 15 57 Pseudo SRAM Write Cycle Nibble Access PLL On TRP 1 Cycle TRCD 1 Cycle No Waits ...

Page 461: ...450 Hitachi Figure 15 58 Pseudo SRAM Auto Refresh Cycle PLL On TRP 1 Cycle TRAS 2 Cycles ...

Page 462: ...Hitachi 451 Figure 15 59 Pseudo SRAM Self Refresh Cycle PLL On TRP 1 Cycle TRAS 2 Cycles ...

Page 463: ...452 Hitachi Note 1 The DACKn waveform shown is for the case where active high has been specified Figure 15 60 Pseudo SRAM Read Cycle PLL Off TRP 1 Cycle TRCD 1 Cycle No Waits ...

Page 464: ...Hitachi 453 Note 1 The DACKn waveform shown is for the case where active high has been specified Figure 15 61 Pseudo SRAM Write Cycle PLL Off TRP 1 Cycle TRCD 1 Cycle No Waits ...

Page 465: ...454 Hitachi Note 1 The DACKn waveform shown is for the case where active high has been specified Figure 15 62 Pseudo SRAM Read Cycle Nibble Access PLL Off TRP 1 Cycle TRCD 1 Cycle No Waits ...

Page 466: ...Hitachi 455 Note 1 The DACKn waveform shown is for the case where active high has been specified Figure 15 63 Pseudo SRAM Write Cycle Nibble Access PLL Off TRP 1 Cycle TRCD 1 Cycle No Waits ...

Page 467: ...456 Hitachi Figure 15 64 Pseudo SRAM Auto Refresh Cycle PLL Off TRP 1 Cycle TRAS 2 Cycles ...

Page 468: ...Hitachi 457 Figure 15 65 Pseudo SRAM Self Refresh Cycle PLL Off TRP 1 Cycle TRAS 2 Cycles ...

Page 469: ...458 Hitachi Note 1 The DACKn waveform shown is for the case where active high has been specified Figure 15 66 Burst ROM Read Cycle PLL On 1 Wait ...

Page 470: ...Hitachi 459 Note 1 The DACKn waveform shown is for the case where active high has been specified Figure 15 67 Burst ROM Read Cycle PLL Off 1 Wait ...

Page 471: ...460 Hitachi Figure 15 68 Interrupt Vector Fetch Cycle PLL On No Waits ...

Page 472: ...Hitachi 461 Figure 15 69 Interrupt Vector Fetch Cycle PLL Off No Waits ...

Page 473: ...462 Hitachi Figure 15 70 Interrupt Vector Fetch Cycle 1 External Wait Cycle ...

Page 474: ...Hitachi 463 Figure 15 71 Address Monitor Cycle ...

Page 475: ...e DREQ0 DREQ1 setup time PLL Off On tDRQS 30 ns 15 72 DREQ0 DREQ1 setup time PLL On 1 4 cycle delay tDRQS 30 1 4 tcyc ns DREQ0 DREQ1 hold time PLL Off On tDRQH 15 ns DREQ0 DREQ1 hold time PLL On 1 4 cycle delay tDRQH 1 4 tcyc 15 ns DREQ0 DREQ1 low level width tDRQW 1 5 tcyc Figure 15 72 DREQ0 DREQ1 Input Timing ...

Page 476: ...y tTOCD 1 4 tcyc 160 ns Input capture setup time PLL Off On tTICS 80 ns Input capture setup time PLL On 1 4 cycle delay tTICS 80 1 4 tcyc ns Timer clock input setup time PLL Off On tTCKS 80 ns 15 74 Timer clock input setup time PLL On 1 4 cycle delay tTCKS 80 1 4 tcyc ns Timer clock pulse width single edge tTCKWH 4 5 tcyc Timer clock pulse width both edges tTCKWL 8 5 tcyc Figure 15 73 FRT Input Ou...

Page 477: ... Table 15 11 Watchdog Timer Timing VCC 5 0 V 10 Ta 20 to 75 C Item Symbol Min Max Unit Figure WDTOVF delay time PLL Off On tWOVD 70 ns 15 75 WDTOVF delay time PLL On 1 4 cycle delay tWOVD 1 4 tcyc 70 Figure 15 75 Watchdog Timer Output Timing ...

Page 478: ...16 tcyc 15 76 Input clock cycle clocked synchronization tscyc 24 tcyc Input clock pulse width tsckw 0 4 0 6 tscyc Transmission data delay time clocked synchronization tTXD 70 ns 15 77 Receive data setup time clocked synchronization tRXS 70 ns Receive data hold time clocked synchronization tRXH 70 ns Figure 15 76 Input Clock I O Timing Figure 15 77 SCI I O Timing Clocked Synchronization Mode ...

Page 479: ...times 1 ns Notes 1 CL is a total value that includes capacitance of measurement instruments and the like and is set as follows for each pin 2 30 pF CKIO RAS CAS CKE CS0 CS3 BREQ BACK DACK0 DACK1 IVECF 3 50 pF All output pins other than the above 4 IOL and IOH values are as shown in section 15 2 DC Characteristics and table 15 3 Permitted Output Current Values Figure 15 78 Output Load Circuit ...

Page 480: ... H H H H H 2 H H System control RESET I I I I I I I WDTOVF H H H H O O O BACK BRLS Z Z I I Z I I BREQ BGR H H O O H O O MD5 MD0 I I I I I I I Interrupt NMI I I I I I I I IRL3 IRL0 Z Z Z Z I I I IVECF H H H H H 3 H H Address bus A26 A0 O Z O Z Z O Z Data bus D31 D0 Z Z IO Z Z Z Z Bus control CS3 CS0 H Z O Z H H Z BS H Z O Z H H Z RD WR H Z O Z H H Z RAS CE H Z O Z H H Z CAS OE H Z O Z H H Z CASHH D...

Page 481: ...Z Z K 3 I I communication TXD L L L L K 3 O O interface SCI SCK Z Z Z Z K 3 IO I PLL CAP2 CAP1 IO IO IO IO IO IO IO I Input O Output H High level output L Low level output Z High impedance K Input pin is high impedance output pin holds the state Notes 1 Depends on the clock mode MD2 MD0 setting 2 Outputs low in the standby mode when the clock is paused 3 When the high impedance bit HIZ of the stan...

Page 482: ...FFFFE09 H FFFFFE10 TIER ICIE OCIAE OCIBE OVIE H FFFFFE11 FTCSR ICF OCFA OCFB OVF CCLRA H FFFFFE12 FRC H FFFFFE13 OCRA B H FFFFFE14 FRT H FFFFFE15 TCR H FFFFFE16 IEDGA CKS1 CKS0 H FFFFFE17 TOCR OCRS OLVLA OLVLB H FFFFFE18 FICR H FFFFFE19 H FFFFFE20 to H FFFFFE59 H FFFFFE60 IPRB SCIIP3 SCIIP2 SCIIP1 SCIIP0 FRTIP3 FRTIP2 FRTIP1 FRTIP0 H FFFFFE61 H FFFFFE62 VCRA SERV6 SERV5 SERV4 SERV3 SERV2 SERV1 SER...

Page 483: ...R0 RS1 RS0 DMAC channel0 H FFFFFE72 DRCR1 RS1 RS0 DMAC channel1 H FFFFFE73 to H FFFFFE7F H FFFFFE80 WTCSR OVF WT IT TME CKS2 CKS1 CKS0 H FFFFFE81 WTCNT WDT H FFFFFE82 H FFFFFE83 WSTCSR WOVF RSTE RSTS H FFFFFE84 to H FFFFFE90 H FFFFFE91 SBYCR SBY HIZ MSTP4 MSTP3 MSTP2 MSTP1 MSTP0 Low consump tion power H FFFFFE92 CCR W1 W0 CP TW OC ID CE cache H FFFFFE93 to H FFFFFE9F Note Address at read When writ...

Page 484: ... DMACIP 0 INTC H FFFFFEE3 WDTIP3 WDTIP2WDTIP1 WDTIP0 H FFFFFEE4 VCRWDT WITV6 WITV5 WITV4 WITV3 WITV2 WITV1 WITV0 H FFFFFEE5 BCMV6 BCMV5 BCMV4 BCMV3 BCMV2 BCMV1 BCMV0 H FFFFFEE6 to H FFFFFEFF H FFFFFF00 H FFFFFF01 DVSR H FFFFFF02 H FFFFFF03 H FFFFFF04 H FFFFFF05 DVDNT H FFFFFF06 H FFFFFF07 H FFFFFF08 H FFFFFF09 DVCR DIVU H FFFFFF0A H FFFFFF0B OVFIE OVF H FFFFFF0C H FFFFFF0D VCRDIV H FFFFFF0E H FFFF...

Page 485: ... BAMA2 4 H FFFFFF45 BAMA2 3 BAMA2 2 BAMA2 1 BAMA2 0 BAMA1 9 BAMA1 8 BAMA1 7 BAMA1 6 UBC channelA H FFFFFF46 BAMRAL BAMA1 5 BAMA1 4 BAMA1 3 BAMA1 2 BAMA1 1 BAMA1 0 BAMA9BAMA8 H FFFFFF47 BAMA7BAMA6BAMA5BAMA4BAMA3BAMA2BAMA1BAMA0 H FFFFFF48 BBRA H FFFFFF49 CPA1 CPA0 IDA1 IDA0 RWA1 RWA0 SZA1 SZA0 H FFFFFF4A to H FFFFFF5F H FFFFFF60 BARBH BAB31 BAB30 BAB29 BAB28 BAB27 BAB26 BAB25 BAB24 H FFFFFF61 BAB23 ...

Page 486: ...DB25 BDB24 H FFFFFF71 BDB23 BDB22 BDB21 BDB20 BDB19 BDB18 BDB17 BDB16 H FFFFFF72 BDRBL BDB15 BDB14 BDB13 BDB12 BDB11 BDB10 BDB9 BDB8 H FFFFFF73 BDB7 BDB6 BDB5 BDB4 BDB3 BDB2 BDB1 BDB0 H FFFFFF74 BDMRBH BDMB 31 BDMB 30 BDMB 29 BDMB 28 BDMB 27 BDMB 26 BDMB 25 BDMB 24 H FFFFFF75 BDMB 23 BDMB 22 BDMB 21 BDMB 20 BDMB 19 BDMB 18 BDMB 17 BDMB 16 UBC H FFFFFF76 BDMRBL BDMB 15 BDMB 14 BDMB 13 BDMB 12 BDMB ...

Page 487: ...83 H FFFFFF84 H FFFFFF85 DAR0 H FFFFFF86 H FFFFFF87 DMAC H FFFFFF88 channel0 H FFFFFF89 TCR0 H FFFFFF8A H FFFFFF8B H FFFFFF8C H FFFFFF8D CHCR0 H FFFFFF8E DM1 DM0 SM1 SM0 TS1 TS0 AR AM H FFFFFF8F AL DS DL TB TA IE TE DE H FFFFFF90 H FFFFFF91 SAR1 H FFFFFF92 H FFFFFF93 H FFFFFF94 H FFFFFF95 DAR1 DMAC H FFFFFF96 channel1 H FFFFFF97 H FFFFFF98 H FFFFFF99 TCR1 H FFFFFF9A H FFFFFF9B ...

Page 488: ...AM channel1 H FFFFFF9F AL DS DL TB TA IE TE DE H FFFFFFA0 H FFFFFFA1 VCRMA0 DMAC H FFFFFFA2 channel0 H FFFFFFA3 VC7 VC6 VC5 VC4 VC3 VC2 VC1 VC0 H FFFFFFA4 to H FFFFFFA7 H FFFFFFA8 H FFFFFFA9 VCRDMA1 DMAC H FFFFFFAA channel1 H FFFFFFAB VC7 VC6 VC5 VC4 VC3 VC2 VC1 VC0 H FFFFFFAC to H FFFFFFAF H FFFFFFB0 H FFFFFFB1 DMAOR H FFFFFFB2 DMAC H FFFFFFB3 PR SR NMIF DME channels H FFFFFFB4 to H FFFFFFDF 0 an...

Page 489: ...R2 H FFFFFFE6 H FFFFFFE7 A3SZ1 A3SZ0 A2SZ1 A2SZ0 A1SZ1 A1SZ0 H FFFFFFE8 H FFFFFFE9 WCR H FFFFFFEA IW31 IW30 IW20 IW21 IW10 IW11 IW01 IW00 H FFFFFFEB W31 W30 W20 W21 W10 W11 W01 W00 H FFFFFFEC H FFFFFFED MCR BSC H FFFFFFEE TRP RCD TRWL TRAS1 TRS0 BE RASD H FFFFFFEF AMX2 SZ AMX1 AMX0 RFSH RMD H FFFFFFF0 H FFFFFFF1 RTCSR H FFFFFFF2 H FFFFFFF3 CMF CMIE CKS2 CKS1 CKS0 H FFFFFFF4 H FFFFFFF5 RTCNT H FFFF...

Page 490: ...Hitachi 479 B 2 Register Chart ...

Page 491: ...ot added or checked Initial value PE 1 Parity bit added and checked 4 Parity mode 0 Even parity Initial value OE 1 Odd parity 3 Stop bit length 0 One stop bit Initial value STOP 1 Two stop bits 2 Multiprocessor mode 0 Multiprocessor function disabled Initial value MP 1 Multiprocessor format selected 1 0 0 φ 4 Initial value Clock select 1 and 0 0 1 φ 16 0 CKS1 CKS0 1 0 φ 64 1 1 φ 256 Bit rate regis...

Page 492: ...r bit MPB is set to 1 in receive data 1 Multiprocessor interrupts are enabled Receive data full interrupt requests RXI receive error interrupt requests ERI and setting of the RDRF FER and ORER status flags in the serial status register SSR are disabled until the multiprocessor bit is set to 1 2 Transmit end interrupt enable TEIE 0 Transmit end interrupt TEI requests are disabled initial value 1 Tr...

Page 493: ... TDRE is cleared to 0 when software reads TDRE after it has been set to 1 then writes 0 in TDRE or the DMAC writes data in TDR 1 TDR does not contain valid transmit data initial value TDRE is set to 1 when the chip is reset or enters standby mode the TE bit in the serial control register SCR is cleared to 0 or TDR contents are loaded into TSR so new data can be written in TDR 6 Receive data regist...

Page 494: ...to 0 when the chip is reset or enters standby mode or software reads PER after it has been set to 1 then writes 0 in PER 1 A receive parity error occurred PER is set to 1 if the number of ls in receive data including the parity bit does not match the even or odd parity setting of the parity mode bit O E in the serial mode register SMR 2 Tranamit end TEND 0 Transmission is in progress TEND is clear...

Page 495: ...I Receive data register RDR H FFFFFE05 8 Bit Item 7 6 5 4 3 2 1 0 Bit Name Initial Value 0 0 0 0 0 0 0 0 R W R R R R R R R R Bit Bit Name Description 7 to 0 Stores serial receive data Stores the received serial data ...

Page 496: ...errupt requests OCIB from the OCFB 1 Timer overflow interrupt enable DVIE 0 Disables interrupt requests OVI from the OVF initial value 1 Enables interrupt requests OVI from the OVF Free running timer control status register FTCSR H FFFFFE11 8 Bit Item 7 6 5 4 3 2 1 0 Bit Name ICF OCFA OCFB OVF CCLRA Initial Value 0 0 0 0 0 0 0 0 R W R W R W R W R W R W Note For bits 7 and 3 to 1 the only value tha...

Page 497: ... FRCH first and then FRCL in eight bits twice Bit Item 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit name nitial Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W Bit Bit name Description 15 to 0 count value Counts input clock Output compare register A B 1 OCRA B H FFFFFE14 OCRA BH H FFFFFE15 OCRA BL 16 2 Notes 1 Switch registers by the OCRS in t...

Page 498: ...ernal clock count at φ 32 1 0 Internal clock count at φ 128 1 1 External clock count at rising edge Timer output compare control register TOCR H FFFFFE17 8 Bit Item 7 6 5 4 3 2 1 0 Bit name OCRS OLVLA OLVLB Initial Value 1 1 1 0 0 0 0 0 R W R W R W R W R W R W Bit Bit Name Value Description 4 Output compare register 0 Selects OCRA register initial value select OCRS 1 Selects OCRB register 1 Output...

Page 499: ...ess FICRH first and then FICRL in eight bits twice Bit Item 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit name Initial Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R W R R R R R R R R R R R R R R R R Bit Bit nam Description 15 to 0 Stores FRC value Stores FRC value when an input capture signal occurs ...

Page 500: ... the DMA controller DMAC interrupt priority level 7 to 4 Watchdog timer WDT interrupt priority level WDTIP3 WDTIP0 These bits set the watchdog timer WDT interrupt priority level and bus state controller BSC interrupt priority level Interrupt priority level setting register B IPRB H FFFFFE60 8 16 Bit Item 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit name SCI SCI SCI SCI FRT FRT FRT FRT IP3 IP2 IP1 IP0...

Page 501: ... These bits set the vector number for the serial communication interface SCI receive data full interrupt RXI Vector number setting register B VCRB H FFFFFE64 8 16 Bit Item 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit name STX STX STX STX STX STX STX STE STE STE STE STE STE STE V6 V5 V4 V3 V2 V1 V0 V6 V5 V4 V3 V2 V1 V0 Initial Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R W R R W R W R W R W R W R W R W R R...

Page 502: ... for the free running timer FRT input capture interrupt ICI 6 to 0 Free running timer FRT output compare interrupt vector number FOCV6 FOCV0 These bits set the vector number for the free running timer FRT output compare interrupt OCI Vector number setting register D VCRD H FFFFFE68 8 16 Bit Item 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit name FOV FOV FOV FOV FOV FOV FOV V6 V5 V4 V3 V2 V1 V0 Initial...

Page 503: ... timer WDT 6 to 0 Bus state controller BSC compare match interrupt vector number BCMV6 BCMV0 These bits set the vector number for the compare match interrupt CMI of the bus state controller BSC Vector number setting register DIV VCRDIV H FFFFFF0C 32 Bit Item 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Bit name Initial Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R W R R R R R R R R R R R R R R R R It...

Page 504: ...ese bits set the vector number at the end of the DMAC transfer VInterrupt control register ICR H FFFFFEE0 8 16 Bit Item 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit name VEC NMIL NMIE MC Initial Value 0 1 0 0 0 0 0 0 0 R W R R R R R R R R W R R R R R R R R W Note When NMI input is high 1 when NMI input is low 0 Bit Bit Name Value Description 15 NMI input level NMIL 0 NMI input level is low 1 NMI inpu...

Page 505: ...Interval timer mode Interval timer interrupt ITI request to the CPU when WTCNT overflows initial value 1 Watchdog timer mode WDTOVF signal is output externally when WTCNT overflows 5 Timer enable TME 0 Timer disabled WTCNT is initialized to H 00 and count up stops initial value 1 Timer enabled WTCNT starts counting A WDTOVF signal or interrupt is generated when WTCNT overflows 2 to 0 Clock select ...

Page 506: ... read Bit BItem 7 6 5 4 3 2 1 0 Bit name WOVF RSTE RSTS Initial Value 0 0 0 1 1 1 1 1 R W R W R W R W Note Only 0 can be written in bit 7 to clear the flag Bit Bit Name Value Description 7 Watchdog timer overflow flag WOVF 0 No WTCNT overflow in watchdog timer mode initial value Cleared when software reads WOVF then writes 0 in WOVF 1 Set by WTCNT overflow in watchdog timer mode 6 Reset enable RST...

Page 507: ...it nam Description 31 to 0 Writes the divisor Writes the divisor for the operation Dividend register L for 32 bit division DVDNT H FFFFFE04 32 Bit Item 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Bit name Initial Value R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W Item 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit name Initial Value R W R W R W R W R W R W R W R W R W R W R W...

Page 508: ...terrupt requests OVFI caused by OVF initial value 1 Enables interrupt requests OVFI caused by OVF 0 Overflow flag OVF 0 No overflow has occurred initial value 1 Overflow has occurred Dividend register H DVDNTH H FFFFFF10 32 Bit Item 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Bit name Initial Value R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W Item 15 14 13 12 11 10 9 8 7...

Page 509: ...ue R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W Item 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit name Initial Value R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W Bit Bit nam Description 31 to 1 Sets the dividend Sets the lower 32 bits of the dividend used for 64 bit 32 bit division operations ...

Page 510: ...dress BAA31 BAA16 These bits specify the upper bits bit 31 to bit 16 of the address of the channel A break condition Break address register AL BARAL H FFFFFF42 16 Bit Item 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit name BAA 15 BAA 14 BAA 13 BAA 12 BAA 11 BAA 10 BAA 9 BAA 8 BAA 7 BAA 6 BAA 5 BAA 4 BAA 3 BAA 2 BAA 1 BAA 0 Initial Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R...

Page 511: ...the break conditions initial value 1 Channel A break address BAAn is not included in the break conditions n 31 to 16 Break address mask register AL BAMRAL H FFFFFF46 16 Bit Item 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit name BAM A15 BAM A14 BAM A13 BAM A12 BAM A11 BAM A10 BAM A9 BAM A8 BAM A7 BAM A6 BAM A5 BAM A4 BAM A3 BAM A2 BAM A1 BAM A0 Initial Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R W R W R W...

Page 512: ...1 Break on both instruction fetch and data access cycles 3 2 Read write select A 0 0 No channel A user break interrupt occurs initial value RWA1 RWA0 0 1 Break only on read cycles 1 0 Break only on write cycles 1 1 Break on both read and write cycles 1 0 0 0 Operand size is not a break condition initial value Operand size select A 0 1 Break on byte access SZA1 SZA0 1 0 Break on word access 1 1 Bre...

Page 513: ...t 0 of the address of the channel B break condition Break address mask register BH BAMRBH H FFFFFF64 16 32 Bit Item 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit name BAM B31 BAM B30 BAM B29 BAM B28 BAM B27 BAM B26 BAM B25 BAM B24 BAM B23 BAM B22 BAM B21 BAM B20 BAM B19 BAM B18 BAM B17 BAM B16 Initial Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W...

Page 514: ... B break address BABn is included in the break conditions initial value 1 Channel B break address BABn is not included in the break conditions n 15 to 0 Break data register BH BDRBH H FFFFFF70 16 32 Bit Item 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit name BDB 31 BDB 30 BDB 29 BDB 28 BDB 27 BDB 26 BDB 25 BDB 24 BDB 23 BDB 22 BDB 21 BDB 20 BDB 19 BDB 18 BDB 17 BDB 16 Initial Value 0 0 0 0 0 0 0 0 0 0...

Page 515: ...he address of the channel B break condition Break data mask register BH BDMRBH H FFFFFF74 16 32 Bit Item 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit name BDM B31 BDM B30 BDM B29 BDM B28 BDM B27 BDM B26 BDM B25 BDM B24 BDM B23 BDM B22 BDM B21 BDM B20 BDM B19 BDM B18 BDM B17 BDM B16 Initial Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W Bit Bi...

Page 516: ... B5 BDM B4 BDM B3 BDM B2 BDM B1 BDM B0 Initial Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W Bit Bit Name Value Description 15 to 0 Break data mask BDMB15 BDMB0 0 Channel B break address BDBn is included in the break conditions initial value 1 Channel B break address BDBn is masked and therefore not inclnded in the break conditions n 15 t...

Page 517: ...cycles 1 1 Break on both CPU and peripheral cycles 5 4 Instruction fetch data 0 0 No channel B user break interrupt occurs initial value access select B 0 1 Break only on instruction fetch cyclcs IDB1 IDB0 1 0 Break only on data access cycles 1 1 Break on both instruction fetch and data access cycles 3 2 Read write select B 0 0 No channel B user break interrupt occurs initial value RWB1 RWB0 0 1 B...

Page 518: ...de 10 PC break select A PCBA 0 Places the channel A instruction fetch cycle break before instruction execution initial value 1 Places the channel A instruction fetch cycle break after instruction execution 7 CPU condition match flag B CMFCB 1 Channel B CPU cycle conditions do not match no user break interrupt generated initial value 0 Channel B CPU cycle conditions have matched user break interrup...

Page 519: ...m Description 31 to 0 Specifies the transfer source address Specifies the DMA transfer source address DMA destination address registers 0 and 1 DAR0 and DAR1 H FFFFFF84 channel 0 H FFFFFF94 channel 1 32 Bit Item 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Bit name Initial Value R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W Item 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit na...

Page 520: ...28 27 26 25 24 23 22 21 20 19 18 17 16 Bit name Initial Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R W R R R R R R R R R R R R R R R R Item 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit name DM1 DM0 SM1 SM0 TS1 TS0 AR AM AL DS DL TB TA IE TE DE Initial Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W Note The only writing permitted is 0 to clear the ...

Page 521: ...ut in read cycle transfer from memory to device initial value 1 DACK output in write cycle transfer from device to memory 7 Acknowledge level bit 0 DACK is an active low signal initial value AL 1 DACK is an active high signal 6 DREQ select bit DS 0 Detected by level initial value 1 Detected by edge 5 DREQ level bit DL 0 When DS is 0 DREQ is detected by low level when DS is 1 DREQ is detected by fa...

Page 522: ...S0 Initial Value 0 0 0 0 0 0 0 0 R W R R R R R R R W R W Bit Bit Name Value Description 1 0 Resource select bits 0 0 DREQ external request initial value 1 0 RS1 RS0 0 1 RXI receive data full interrupt transfer request of the on chip serial communication interface SCI 1 0 TXI transmit data full interrupt transfer request of the on chip SCI 1 1 Reserved setting disabled ...

Page 523: ... is 0 to clear the flag Bit Bit Name Value Description 3 Priority mode bit PR 0 Fixed priority Ch 0 Ch 1 initial value 1 Round robin mode Top priority shifts to bottom after each transfer The priority for the first DMA transfer after a reset is Ch 1 Ch 0 2 Address error flag bit 0 No DMAC address error initial value AE 1 Address error by DMAC 1 NMI flag bit NMIF 0 No NMIF interrupt initial value T...

Page 524: ... initial mode specification PSHR 1 Partial share master mode when MD5 0 9 8 Long wait specification 0 0 3 waits initial value of areas 2 and 3 0 1 4 waits AHLW1 AHLW0 1 0 5 waits 1 1 6 waits 7 6 Long wait specification 0 0 3 waits initial value of area 1 A1LW1 0 1 4 waits A1LW0 1 0 5 waits 1 1 6 waits 5 4 Long wait specification 0 0 3 waits initial value of area 0 A0LW1 0 1 4 waits A0LW0 1 0 5 wai...

Page 525: ...A2SZ0 Effective only 1 0 Word 16 bits size when setting ordinary space 1 1 Longword 32 bits size initial value 3 2 Bus size specification of 0 0 Reserved do not set area 1 A1SZ1 A1SZ0 0 1 Byte 8 bits size 1 0 Word 16 bits size 1 1 Longword 32 bits size initial value Wait control register WCR H FFFFFFE8 16 32 Bit Item 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit Name IW31IW30IW21IW20 IW11IW10IW01IW00 ...

Page 526: ... 1 1 Reserved do not set When area 2 or 3 is synchronous DRAM W31 W21 W30 W20 0 0 1 CAS latency cycle 0 1 2 CAS latency cycles 1 0 3 CAS latency cycles 1 1 4 CAS latency cycles initial value When area 3 is pseudo SRAM W31 W30 0 0 2 cycles from BS signal assertion to the end of cycle 0 1 3 cycles from BS signal assertion to the end of cycle 1 0 4 cycles from BS signal assertion to the end of cycle ...

Page 527: ...st enable BE 0 Burst disabled initial value 1 High sped page mode during DRAM interface is enabled Data is continuously transferred in static column mode during pseudo SRAM interface During synchronous DRAM access burst is always enabled regardless of this bit 9 Bank active mode RASD 0 For synchronous DRAM read or write is performed using auto precharge mode The next access always starts with bank...

Page 528: ...erved do not set 1 1 1 Reserved do not set For synchronous DRAM interface 0 0 0 16 Mbit DRAM 1M x 16 bits initial value 0 0 1 16 Mbit DRAM 2M x 8 bits 0 1 0 16 Mbit DRAM 4M x 4 bits 0 1 1 4 Mbit DRAM 256k x 16 bits 1 0 0 Reserved do not set 1 0 1 Reserved do not set 1 1 0 Reserved do not set 1 1 1 2 Mbit DRAM 128k x 16 bits 6 Memory data size SZ 0 Word initial value 1 Longword 3 Refresh control RF...

Page 529: ...aused by CMF 5 t0 3 Clock select bits 0 0 0 Disables count up initialal value CKS2 CKS0 0 0 1 CLK 4 0 1 0 CLK 16 0 1 1 CLK 64 1 0 0 CLK 256 1 0 1 CLK 1024 1 1 0 CLK 2048 1 1 1 CLK 4096 Refresh timer counter RTCNT H FFFFFFF4 16 32 Bit Item 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit Name Initial Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R W R R R R R R R R R W R W R W R W R W R W R W R W Bit Bit Name Des...

Page 530: ...Way 1 1 0 Way 2 1 1 Way 3 4 Cache purge CP 0 Nomal operation initial value 1 Cache purge 3 Two way mode TW 0 Four way mode initial value 1 Two way mode 2 Data replacement 0 Nomal operation initial value disable OD 1 Data not replaced even when cache missed in data access 1 Instruction replacement 0 Nomal operation initial value disable ID 1 Data not replaced even when cache missed in instruction f...

Page 531: ...s the LSI into standby mode 6 Port high impedance 0 Holds pin state in standby mode initial value HIZ 1 Keeps pin at high impedance in standby mode 4 Module stop 4 MSTP4 0 DMAC running initial value 1 Clock supply to DMAC halted 3 Module stop 3 MSTP3 0 MULT running initial value 1 Clock supply to MULT halted 2 Module stop 2 MSTP2 0 DIVU running initial value 1 Clock supply to DIVU halted 1 Module ...

Page 532: ...Hitachi 521 Appendix C External Dimensions Figure C 1 shows the external dimensions of the SH7095 FP 144 Figure C 1 External Dimensions ...

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