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Hitachi H8S/2376 F-ZTAT, Hardware Manual

The Hitachi H8S/2376 F-ZTAT is a cutting-edge microcontroller renowned for its exceptional performance and reliability. Unlock the full potential of this device by accessing the comprehensive Hardware Manual, available for free download at manualshive.com. Get detailed insights and optimize your experience with this exceptional product.

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Rev. 1.0, 09/01, page 373 of 904

When transfer is aborted, register values are retained, and as the address registers indicate the next
transfer addresses, transfer can be resumed by setting the EDA bit to 1 in EDMDR. If the BEF bit
is 1 in EDMDR, transfer can be resumed from midway through a block.

Hardware Standby Mode and Reset Input: The EXDMAC is initialized in hardware standby
mode and by a reset. DMA transfer is not guaranteed in these cases.

8.4.13

Relationship between EXDMAC and Other Bus Masters

The read and write operations in a DMA transfer cycle are indivisible, and a refresh cycle, external
bus release cycle, or internal bus master (CPU, DTC, or DMAC) external space access cycle never
occurs between the two.

When read and write cycles occur consecutively, as in burst transfer or block transfer, a refresh or
external bus release state may be inserted after the write cycle. As the internal bus masters are of
lower priority than the EXDMAC, external space accesses by internal bus masters are not
executed until the EXDMAC releases the bus.

The EXDMAC releases the bus in the following cases:

1. When DMA transfer is performed in cycle steal mode

2. When switching to a different channel

3. When transfer ends in burst transfer mode

4. When transfer of one block ends in block transfer mode

5. When burst transfer or block transfer is performed with the BGUP bit in EDMDR set to 1

(however, the bus is not released between read and write cycles)

8.5

Interrupt Sources

EXDMAC interrupt sources are a transfer end indicated by the transfer counter, and repeat area
overflow interrupts. Table 8.4 shows the interrupt sources and their priority order.

Table 8.4

Interrupt Sources and Priority Order

Interrupt

Interrupt source

Interrupt Priority

EXDMTEND2

Transfer end indicated by channel 2 transfer counter

Channel 2 source address repeat area overflow

Channel 2 destination address repeat area overflow

High

EXDMTEND3

Transfer end indicated by channel 3 transfer counter

Channel 3 source address repeat area overflow

Channel 3 destination address repeat area overflow

Low

Summary of Contents for H8S/2376 F-ZTAT

Page 1: ... Single Chip Microcomputer H8S 2378 H8S 2378R Series H8S 2377R F ZTAT HD64F2377R H8S 2376R F ZTAT HD64F2376R H8S 2377 F ZTAT HD64F2377 H8S 2376 F ZTAT HD64F2376 Hardware Manual ADE 602 260 Rev 1 0 9 25 01 Hitachi Ltd ...

Page 2: ... or cause risk of bodily injury such as aerospace aeronautics nuclear power combustion control transportation traffic safety equipment or medical equipment for life support 4 Design your application so that the product is used within the ranges guaranteed by Hitachi particularly for maximum rating operating supply voltage range heat radiation characteristics installation conditions and other chara...

Page 3: ...ialization Note When power is first supplied the product s state is undefined The states of internal circuits are undefined until full power is supplied throughout the chip and a low level is input on the reset pin During the period where the states are undefined the register settings and the output state of each pin are also undefined Design your system so that it does not malfunction because of ...

Page 4: ...e Points for Caution When designing an application system that includes this LSI take the points for caution into account Each section includes points for caution in relation to the descriptions given and points for caution in usage are given as required as the final part of each section 7 List of Registers 8 Electrical Characteristics 9 Appendix Product type codes and external dimensions Major re...

Page 5: ...t probably change Note F ZTAT TM is a trademark of Hitachi Ltd Target Users This manual was written for users who will be using the H8S 2378 Series in the design of application systems Target users are expected to understand the fundamentals of electrical circuits logical circuits and microcomputers Objective This manual was written to explain the hardware functions and electrical characteristics ...

Page 6: ... are available from our web site Please ensure you have the latest versions of all documents you require http www hitachisemiconductor com H8S 2378 Series manuals Manual Title ADE No H8S 2378 Series Hardware Manual This manual H8S 2600 Series H8S 2000 Series Programming Manual ADE 602 083 User s manuals for development tools Manual Title ADE No H8S H8 300 Series C C Compiler Assembler Optimizing L...

Page 7: ...Extended Register EXR 27 2 4 4 Condition Code Register CCR 28 2 4 5 Initial Register Values 30 2 5 Data Formats 30 2 5 1 General Register Data Formats 30 2 5 2 Memory Data Formats 32 2 6 Instruction Set 33 2 6 1 Table of Instructions Classified by Function 34 2 6 2 Basic Instruction Formats 43 2 7 Addressing Modes and Effective Address Calculation 44 2 7 1 Register Direct Rn 45 2 7 2 Register Indi...

Page 8: ...dling 63 4 1 Exception Handling Types and Priority 63 4 2 Exception Sources and Exception Vector Table 63 4 3 Reset 65 4 3 1 Reset exception handling 65 4 3 2 Interrupts after Reset 67 4 3 3 On Chip Peripheral Functions after Reset Release 67 4 4 Traces 68 4 5 Interrupts 68 4 6 Trap Instruction 69 4 7 Stack Status after Exception Handling 70 4 8 Usage Notes 71 Section 5 Interrupt Controller 73 5 1...

Page 9: ...ng 103 Section 6 Bus Controller BSC 105 6 1 Features 105 6 2 Input Output Pins 107 6 3 Register Descriptions 109 6 3 1 Bus Width Control Register ABWCR 110 6 3 2 Access State Control Register ASTCR 110 6 3 3 Wait Control Registers AH AL BH and BL WTCRAH WTCRAL WTCRBH and WTCRBL 111 6 3 4 Read Strobe Timing Control Register RDNCR 116 6 3 5 CS Assertion Period Control Registers H L CSACRH CSACRL 117...

Page 10: ...ansfer Mode and DRAM Interface 177 6 7 Synchronous DRAM Interface 180 6 7 1 Setting Continuous Synchronous DRAM Space 180 6 7 2 Address Multiplexing 181 6 7 3 Data Bus 182 6 7 4 Pins Used for Synchronous DRAM Interface 182 6 7 5 Synchronous DRAM Clock 184 6 7 6 Basic Timing 184 6 7 7 CAS Latency Control 186 6 7 8 Row Address Output State Control 188 6 7 9 Precharge State Count 190 6 7 10 Bus Cycle...

Page 11: ... Register Descriptions 243 7 3 1 Memory Address Registers MARA and MARB 244 7 3 2 I O Address Registers IOARA and IOARB 245 7 3 3 Execute Transfer Count Registers ETCRA and ETCRB 245 7 3 4 DMA Control Registers DMACRA and DMACRB 247 7 3 5 DMA Band Control Registers H and L DMABCRH and DMABCRL 254 7 3 6 DMA Write Enable Register DMAWER 266 7 3 7 DMA Terminal Control Register DMATCR 268 7 4 Activati...

Page 12: ... Output Pins 319 8 3 Register Descriptions 319 8 3 1 EXDMA Source Address Register EDSAR 320 8 3 2 EXDMA Destination Address Register EDDAR 320 8 3 3 EXDMA Transfer Count Register EDTCR 321 8 3 4 EXDMA Mode Control Register EDMDR 323 8 3 5 EXDMA Address Control Register EDACR 327 8 4 Operation 331 8 4 1 Transfer Modes 331 8 4 2 Address Modes 332 8 4 3 DMA Transfer Requests 336 8 4 4 Bus Modes 336 ...

Page 13: ...s A to H DTCERA to DTCERH 383 9 2 8 DTC Vector Register DTVECR 383 9 3 Activation Sources 384 9 4 Location of Register Information and DTC Vector Table 385 9 5 Operation 388 9 5 1 Normal Mode 390 9 5 2 Repeat Mode 391 9 5 3 Block Transfer Mode 392 9 5 4 Chain Transfer 393 9 5 5 Interrupts 394 9 5 6 Operation Timing 395 9 5 7 Number of DTC Execution States 396 9 6 Procedures for Using DTC 397 9 6 1...

Page 14: ...10 4 Port 4 436 10 4 1 Port 4 Register PORT4 436 10 4 2 Pin Functions 436 10 5 Port 5 438 10 5 1 Port 5 Data Direction Register P5DDR 438 10 5 2 Port 5 Data Register P5DR 438 10 5 3 Port 5 Register PORT5 439 10 5 4 Pin Functions 439 10 6 Port 6 441 10 6 1 Port 6 Data Direction Register P6DDR 441 10 6 2 Port 6 Data Register P6DR 441 10 6 3 Port 6 Register PORT6 442 10 6 4 Pin Functions 442 10 7 Por...

Page 15: ...l Up States 467 10 12 Port D 468 10 12 1 Port D Data Direction Register PDDDR 468 10 12 2 Port D Data Register PDDR 468 10 12 3 Port D Register PORTD 469 10 12 4 Port D Pull up Control Register PDPCR 469 10 12 5 Pin Functions 469 10 12 6 Port D MOS Input Pull Up States 470 10 13 Port E 471 10 13 1 Port E Data Direction Register PEDDR 471 10 13 2 Port E Data Register PEDR 472 10 13 3 Port E Registe...

Page 16: ... 531 11 4 1 Basic Functions 531 11 4 2 Synchronous Operation 536 11 4 3 Buffer Operation 538 11 4 4 Cascaded Operation 541 11 4 5 PWM Modes 543 11 4 6 Phase Counting Mode 548 11 5 Interrupts 554 11 6 DTC Activation 556 11 7 DMAC Activation 556 11 8 A D Converter Activation 556 11 9 Operation Timing 557 11 9 1 Input Output Timing 557 11 9 2 Interrupt Signal Timing 560 11 10 Usage Notes 563 11 10 1 ...

Page 17: ...e Output 583 12 4 3 Example of Normal Pulse Output Example of Five Phase Pulse Output 584 12 4 4 Non Overlapping Pulse Output 585 12 4 5 Sample Setup Procedure for Non Overlapping Pulse Output 586 12 4 6 Example of Non Overlapping Pulse Output Example of Four Phase Complementary Non Overlapping Output 587 12 4 7 Inverted Pulse Output 588 12 4 8 Pulse Output Triggered by Input Capture 589 12 5 Usag...

Page 18: ...tion 609 13 8 6 Mode Setting with Cascaded Connection 611 13 8 7 Interrupts in Module Stop Mode 611 Section 14 Watchdog Timer 613 14 1 Features 613 14 2 Input Output Pin 614 14 3 Register Descriptions 614 14 3 1 Timer Counter TCNT 615 14 3 2 Timer Control Status Register TCSR 615 14 3 3 Reset Control Status Register RSTCSR 617 14 4 Operation 618 14 4 1 Watchdog Timer Mode 618 14 4 2 Interval Timer...

Page 19: ...smission 671 15 5 2 Multiprocessor Serial Data Reception 673 15 6 Operation in Clocked Synchronous Mode 676 15 6 1 Clock 676 15 6 2 SCI Initialization Clocked Synchronous Mode 677 15 6 3 Serial Data Transmission Clocked Synchronous Mode 678 15 6 4 Serial Data Reception Clocked Synchronous Mode 681 15 6 5 Simultaneous Serial Data Transmission and Reception Clocked Synchronous Mode 683 15 7 Operatio...

Page 20: ...5 I 2 C Bus Status Register ICSR 717 16 3 6 Slave address register SAR 719 16 3 7 I 2 C Bus Transmit Data Register ICDRT 719 16 3 8 I 2 C Bus Receive Data Register ICDRR 719 16 3 9 I I 2 C Bus Shift Register ICDRS 719 16 4 Operation 720 16 4 1 I 2 C Bus Format 720 16 4 2 Master Transmit Operation 721 16 4 3 Master Receive Operation 723 16 4 4 Slave Transmit Operation 725 16 4 5 Slave Receive Opera...

Page 21: ...8 4 Operation 760 18 5 Usage Notes 761 18 5 1 Setting for Module Stop Mode 761 18 5 2 D A Output Hold Function in Software Standby Mode 761 Section 19 RAM 763 Section 20 Flash Memory F ZTAT Version 765 20 1 Features 765 20 2 Mode Transitions 766 20 3 Block Configuration 770 20 4 Input Output Pins 772 20 5 Register Descriptions 772 20 5 1 Flash Memory Control Register 1 FLMCR1 772 20 5 2 Flash Memo...

Page 22: ...799 21 5 2 Notes on Oscillator 799 21 5 3 Notes on Board Design 800 Section 22 Power Down Modes 801 22 1 Register Descriptions 804 22 1 1 Standby Control Register SBYCR 804 22 1 2 Module Stop Control Registers H and L MSTPCRH MSTPCRL 806 22 1 3 Extension Module Stop Control Registers H and L EXMSTPCRH EXMSTPCRL 807 22 2 Operation 808 22 2 1 Clock Division Mode 808 22 2 2 Sleep Mode 808 22 2 3 Soft...

Page 23: ...1 24 2 DC Characteristics 852 24 3 AC Characteristics 855 24 3 1 Clock Timing 856 24 3 2 Control Signal Timing 858 24 3 3 Bus Timing 860 24 3 4 DMAC and EXDMAC Timing 881 24 3 5 Timing of On Chip Peripheral Modules 885 24 4 A D Conversion Characteristics 890 24 5 D A Conversion Characteristics 890 24 6 Flash Memory Characteristics 891 24 7 Usage Note 893 Appendix 895 A I O Port States in Each Pin ...

Page 24: ...Rev 1 0 09 01 page xxiv of xliv ...

Page 25: ...emory Map 2 60 Figure 3 3 H8S 2376 Memory Map 1 61 Figure 3 4 H8S 2376 Memory Map 2 62 Section 4 Exception Handling Figure 4 1 Reset Sequence Advanced Mode with On chip ROM Enabled 66 Figure 4 2 Reset Sequence Advanced Mode with On chip ROM Disabled 67 Figure 4 3 Stack Status after Exception Handling 70 Figure 4 4 Operation when SP Value Is Odd 71 Section 5 Interrupt Controller Figure 5 1 Block Di...

Page 26: ...ming when Chip Select Assertion Period is Extended 155 Figure 6 21 DRAM Basic Access Timing RAST 0 CAST 0 159 Figure 6 22 Example of Access Timing with 3 State Column Address Output Cycle RAST 0 160 Figure 6 23 Example of Access Timing when RAS Signal Goes Low from Beginning of Tr State CAST 0 161 Figure 6 24 Example of Timing with One Row Address Output Maintenance State RAST 0 CAST 0 162 Figure ...

Page 27: ...5 Auto Refresh Timing TPC 1 TPC0 1 RCW1 0 RCW0 1 201 Figure 6 56 Auto Refresh Timing TPC 0 TPC0 0 RLW1 0 RLW0 1 202 Figure 6 57 Self Refresh Timing TPC1 1 TPC0 0 RCW1 0 RCW0 0 RLW1 0 RLW0 0 203 Figure 6 58 Example of Timing when Precharge Time after Self Refreshing Is Extended by 2 States TPCS2 to TPCS0 H 2 TPC1 0 TPC0 0 CAS Latency 2 204 Figure 6 59 Synchronous DRAM Mode Setting Timing 205 Figure...

Page 28: ...secutive Read and Write Accesses to DRAM Space in RAS Down Mode 228 Figure 6 82 Example of Timing for Idle Cycle Insertion in Case of Consecutive Read and Write Accesses to Continuous Synchronous DRAM Space in RAS Down Mode SDWCD 1 CAS Latency 2 229 Figure 6 83 Example of Timing when Write Data Buffer Function is Used 231 Figure 6 84 Bus Released State Transition Timing 234 Figure 6 85 Bus Release...

Page 29: ... Using Write Data Buffer Function 307 Figure 7 34 Example of Multi Channel Transfer 308 Figure 7 35 Example of Procedure for Continuing Transfer on Channel Interrupted by NMI Interrupt 309 Figure 7 36 Example of Procedure for Forcibly Terminating DMAC Operation 310 Figure 7 37 Example of Procedure for Clearing Full Address Mode 311 Figure 7 38 Block Diagram of Transfer End Transfer Break Interrupt...

Page 30: ...ycle Steal Mode Normal Transfer Mode Contention with Another Channel Single Address Mode 360 Figure 8 31 Auto Request Burst Mode Normal Transfer Mode CPU Cycles Dual Address Mode BGUP 0 361 Figure 8 32 Auto Request Burst Mode Normal Transfer Mode CPU Cycles Dual Address Mode BGUP 1 361 Figure 8 33 Auto Request Burst Mode Normal Transfer Mode CPU Cycles Single Address Mode BGUP 1 362 Figure 8 34 Au...

Page 31: ... or Repeat Mode 395 Figure 9 10 DTC Operation Timing Example of Block Transfer Mode with Block Size of 2 395 Figure 9 11 DTC Operation Timing Example of Chain Transfer 395 Figure 9 12 Chain Transfer when Counter 0 400 Section 11 16 Bit Timer Pulse Unit TPU Figure 11 1 Block Diagram of TPU 496 Figure 11 2 Example of Counter Operation Setting Procedure 531 Figure 11 3 Free Running Counter Operation ...

Page 32: ... 561 Figure 11 41 TCIU Interrupt Setting Timing 562 Figure 11 42 Timing for Status Flag Clearing by CPU 562 Figure 11 43 Timing for Status Flag Clearing by DTC DMAC Activation 563 Figure 11 44 Phase Difference Overlap and Pulse Width in Phase Counting Mode 564 Figure 11 45 Contention between TCNT Write and Clear Operations 565 Figure 11 46 Contention between TCNT Write and Increment Operations 565...

Page 33: ...to TCNT TCSR and RSTCSR 621 Figure 14 5 Contention between TCNT Write and Increment 622 Figure 14 6 Circuit for System Reset by WDTOVF Signal Example 623 Section 15 Serial Communication Interface SCI IrDA Figure 15 1 Block Diagram of SCI 627 Figure 15 2 Data Format in Asynchronous Communication Example with 8 Bit Data Parity Two Stop Bits 658 Figure 15 3 Receive Data Sampling Timing in Asynchronou...

Page 34: ...on Processing Flow 691 Figure 15 29 Retransfer Operation in SCI Receive Mode 692 Figure 15 30 Example of Reception Processing Flow 693 Figure 15 31 Timing for Fixing Clock Output Level 693 Figure 15 32 Clock Halt and Restart Procedure 694 Figure 15 33 Block Diagram of IrDA 695 Figure 15 34 IrDA Transmit Receive Operations 696 Figure 15 35 Example of Synchronous Transmission Using DTC 702 Figure 15...

Page 35: ...ration 761 Section 20 Flash Memory F ZTAT Version Figure 20 1 Block Diagram of Flash Memory 766 Figure 20 2 Flash Memory State Transitions 767 Figure 20 3 Boot Mode 768 Figure 20 4 User Program Mode 769 Figure 20 5 384 Kbyte Flash Memory Block Configuration Modes 3 4 and 7 771 Figure 20 6 Programming Erasing Flowchart Example in User Program Mode 781 Figure 20 7 Flowchart for Flash Memory Emulatio...

Page 36: ...7 DRAM Access Timing Three State Access RAST 1 873 Figure 24 18 DRAM Access Timing Three State Burst Access 874 Figure 24 19 CAS Before RAS Refresh Timing 875 Figure 24 20 CAS Before RAS Refresh Timing with Wait Cycle Insertion 875 Figure 24 21 Self Refresh Timing Return from Software Standby Mode RAST 0 875 Figure 24 22 Self Refresh Timing Return from Software Standby Mode RAST 1 876 Figure 24 23...

Page 37: ...40 WDT Output Timing 888 Figure 24 41 SCK Clock Input Timing 888 Figure 24 42 SCI Input Output Timing Synchronous Mode 888 Figure 24 43 A D Converter External Trigger Input Timing 889 Figure 24 44 I2 C Bus Interface Input Output Timing Option 889 ...

Page 38: ...Rev 1 0 09 01 page xxxviii of xliv ...

Page 39: ...ion 2 49 Section 3 MCU Operating Modes Table 3 1 MCU Operating Mode Selection 53 Table 3 2 Pin Functions in Each Operating Mode 58 Section 4 Exception Handling Table 4 1 Exception Types and Priority 63 Table 4 2 Exception Handling Vector Table 64 Table 4 3 Status of CCR and EXR after Trace Exception Handling 68 Table 4 4 Status of CCR and EXR after Trap Instruction Exception Handling 69 Section 5 ...

Page 40: ...ter Functions in Normal Mode 284 Table 7 10 Register Functions in Block Transfer Mode 287 Table 7 11 DMAC Channel Priority Order 307 Table 7 12 Interrupt Sources and Priority Order 311 Section 8 EXDMA Controller Table 8 1 Pin Configuration 319 Table 8 2 EXDMAC Transfer Modes 331 Table 8 3 EXDMAC Channel Priority Order 346 Table 8 4 Interrupt Sources and Priority Order 373 Section 9 Data Transfer C...

Page 41: ...H_0 516 Table 11 21 TIORL_0 517 Table 11 22 TIOR_1 518 Table 11 23 TIOR_2 519 Table 11 24 TIORH_3 520 Table 11 25 TIORL_3 521 Table 11 26 TIOR_4 522 Table 11 27 TIOR_5 523 Table 11 28 Register Combinations in Buffer Operation 538 Table 11 29 Cascaded Combinations 541 Table 11 30 PWM Output Registers and Output Pins 544 Table 11 31 Clock Input Pins in Phase Counting Mode 548 Table 11 32 Up Down Cou...

Page 42: ...d Synchronous Mode 653 Table 15 8 Examples of Bit Rate for Various BRR Settings Smart Card Interface Mode when n 0 and S 372 654 Table 15 9 Maximum Bit Rate at Various Frequencies Smart Card Interface Mode when S 372 654 Table 15 10 Serial Transfer Formats Asynchronous Mode 659 Table 15 11 SSR Status Flags and Receive Data Handling 666 Table 15 12 Settings of Bits IrCKS2 to IrCKS0 697 Table 15 13 ...

Page 43: ...96 Table 21 3 External Clock Input Conditions 798 Section 22 Power Down Modes Table 22 1 Operating Modes 802 Table 22 2 Oscillation Stabilization Time Settings 810 Table 22 3 ø Pin State in Each Processing State 813 Section 24 Electrical Characteristics Table 24 1 Absolute Maximum Ratings 851 Table 24 2 DC Characteristics 852 Table 24 3 DC Characteristics 853 Table 24 4 Permissible Output Currents...

Page 44: ...Rev 1 0 09 01 page xliv of xliv ...

Page 45: ...it TPU Programmable pulse generator PPG 8 bit timer TMR Watchdog timer WDT Asynchronous or clocked synchronous serial communication interface SCI 10 bit A D converter 8 bit D A converter Clock pulse generator On chip memory ROM Type Model ROM RAM Remarks Flash memory Version HD64F2377 384 kbytes 24 kbytes In planning stage HD64F2376 384 kbytes 16 kbytes HD64F2377R 384 kbytes 24 kbytes HD64F2376R 3...

Page 46: ...DQML PF1 DQMU PF0 ROM Flash memory RAM WDT EXDMAC TPU x 6 channels IIC bus interface option SCI x 5 channels 8 bit D A converter 10 bit A D converter PPG TMR x 2 channels H8S 2000 CPU DTC Interrupt controller Clock pulse generator Port E Port 4 Port 9 PH3 CKE PH2 PH1 SDRAM PH0 Port H Port 2 Port 1 DMAC Internal adree bus Port F Port G Port 8 Port 6 Port A Port B Port C Port 3 Port 5 Bus controller...

Page 47: ...7 AN15 DA5 AVss PG4 PG5 PG6 P50 TXD2 P51 RXD2 P52 SCK2 P53 P35 SCK1 SCL0 CKE 1 P34 SCK0 SCK4 SDA0 P33 RxD1 SCL1 P32 RxD0 IrRxD SDA1 P31 TxD1 P30 TxD0 IrTxD MD0 MD1 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 Vcc PE7 D7 Vss PE6 D6 PE5 D5 PE4 D4 PE3 D3 PE2 D2 PE1 D1 PE0 D0 DCTL P85 SCK3 P84 P83 RXD3 P...

Page 48: ...PC2 A2 PC2 A2 PC2 A2 8 A3 A3 PC3 A3 PC3 A3 PC3 A3 9 A4 A4 PC4 A4 PC4 A4 PC4 A4 10 Vss Vss Vss Vss Vss Vss 11 A5 A5 PC5 A5 PC5 A5 PC5 A5 12 A6 A6 PC6 A6 PC6 A6 PC6 A6 13 A7 A7 PC7 A7 PC7 A7 PC7 A7 14 A8 A8 PB0 A8 PB0 A8 PB0 A8 15 A9 A9 PB1 A9 PB1 A9 PB1 A9 16 A10 A10 PB2 A10 PB2 A10 PB2 A10 17 A11 A11 PB3 A11 PB3 A11 PB3 A11 18 Vss Vss Vss Vss Vss Vss 19 A12 A12 PB4 A12 PB4 A12 PB4 A12 20 A13 A13 P...

Page 49: ... PH1 SDRAM NC 37 PH2 CS6 I RQ6 PH2 CS6 I RQ6 PH2 CS6 I RQ6 PH2 CS6 I RQ6 PH2 I RQ6 NC 38 PH3 CS7 I RQ7 OE CKE PH3 CS7 I RQ7 OE CKE PH3 CS7 I RQ7 OE CKE PH3 CS7 I RQ7 OE CKE PH3 I RQ7 NC 39 W DTOVF W DTOVF W DTOVF W DTOVF W DTOVF NC 40 NMI NMI NMI NMI NMI Vcc 41 Vcc Vcc Vcc Vcc Vcc Vcc 42 P10 PO8 TIOCA0 P10 PO8 TIOCA0 P10 PO8 TIOCA0 P10 PO8 TIOCA0 P10 PO8 TIOCA0 NC 43 P11 PO9 TIOCB0 P11 PO9 TIOCB0 ...

Page 50: ...55 P24 PO4 TIOCA4 RXD4 I RQ12 P24 PO4 TIOCA4 RXD4 I RQ12 P24 PO4 TIOCA4 RXD4 I RQ12 P24 PO4 TIOCA4 RXD4 I RQ12 P24 PO4 TIOCA4 RXD4 I RQ12 W E 56 P25 PO5 TIOCB4 I RQ13 P25 PO5 TIOCB4 I RQ13 P25 PO5 TIOCB4 I RQ13 P25 PO5 TIOCB4 I RQ13 P25 PO5 TIOCB4 I RQ13 Vss 57 P26 PO6 TIOCA5 I RQ14 P26 PO6 TIOCA5 I RQ14 P26 PO6 TIOCA5 I RQ14 P26 PO6 TIOCA5 I RQ14 P26 PO6 TIOCA5 I RQ14 NC 58 P27 PO7 TIOCB5 I RQ15 ...

Page 51: ...EQ0 I RQ8 NC 82 P61 TMRI1 DREQ1 I RQ9 P61 TMRI1 DREQ1 I RQ9 P61 TMRI1 DREQ1 I RQ9 P61 TMRI1 DREQ1 I RQ9 P61 TMRI1 DREQ1 I RQ9 NC 83 P62 TMCI0 TEND0 I RQ10 P62 TMCI0 TEND0 I RQ10 P62 TMCI0 TEND0 I RQ10 P62 TMCI0 TEND0 I RQ10 P62 TMCI0 TEND0 I RQ10 NC 84 PF0 W AI T PF0 W AI T PF0 W AI T PF0 W AI T PF0 NC 85 PF1 UCAS I RQ14 DQMU PF1 UCAS I RQ14 DQMU PF1 UCAS I RQ14 DQMU PF1 UCAS I RQ14 DQMU PF1 I RQ1...

Page 52: ...TMO1 DACK1 I RQ13 NC 107 PG0 CS0 PG0 CS0 PG0 CS0 PG0 CS0 PG0 NC 108 PG1 CS1 PG1 CS1 PG1 CS1 PG1 CS1 PG1 NC 109 PG2 CS2 RAS2 RAS PG2 CS2 RAS2 RAS PG2 CS2 RAS2 RAS PG2 CS2 RAS2 RAS PG2 NC 110 PG3 CS3 RAS3 CAS PG3 CS3 RAS3 CAS PG3 CS3 RAS3 CAS PG3 CS3 RAS3 CAS PG3 NC 111 AVcc AVcc AVcc AVcc AVcc Vcc 112 Vref Vref Vref Vref Vref NC 113 P40 AN0 P40 AN0 P40 AN0 P40 AN0 P40 AN0 NC 114 P41 AN1 P41 AN1 P41...

Page 53: ... TxD2 I RQ0 P50 TxD2 I RQ0 Vss 134 P51 RxD2 I RQ1 P51 RxD2 I RQ1 P51 RxD2 I RQ1 P51 RxD2 I RQ1 P51 RxD2 I RQ1 Vss 135 P52 SCK2 I RQ2 P52 SCK2 I RQ2 P52 SCK2 I RQ2 P52 SCK2 I RQ2 P52 SCK2 I RQ2 Vcc 136 P53 ADTRG I RQ3 P53 ADTRG I RQ3 P53 ADTRG I RQ3 P53 ADTRG I RQ3 P53 ADTRG I RQ3 NC 137 P35 SCK1 SCL0 OE CKE P35 SCK1 SCL0 OE CKE P35 SCK1 SCL0 OE CKE P35 SCK1 SCL0 OE CKE P35 SCK1 SCL0 NC 138 P34 SCK...

Page 54: ...rator for typical connection diagrams for a crystal oscillator and external clock input 94 Output Supplies the system clock to external devices SDRAM 36 Output When a synchronous DRAM is connected this pin is connected to the CLK pin of the synchronous DRAM For details refer to section 6 Bus Controller Operating mode control MD2 MD1 MD0 1 144 143 Input These pins set the operating mode These pins ...

Page 55: ...M space LW R 87 Output Strobe signal indicating that external address space is to be written and the lower half D7 to D0 of the data bus is enabled BREQ 132 Input The external bus master requests the bus to this LSI BREQO 130 Output External bus request signal when the internal bus master accesses the external space in external bus release state BACK 131 Output Indicates the bus is released to the...

Page 56: ...t pins of OE and OE are selected by the port function control register 2 PFCR2 of port 3 CKE CKE 38 137 Output Clock enable signal of the synchronous DRAM interface space The output pins of CKE and CKE are selected by the port function control register 2 PFCR2 of port 3 Interrupt signals NMI 40 Input Nonmaskable interrupt request pin Fix high when not used I RQ15 to I RQ0 86 85 106 to 104 83 to 81...

Page 57: ...ture input output compare output PWM output pins TIOCA2 TIOCB2 48 49 Input output TGRA_2 and TGRB_2 input capture input output compare output PWM output pins TIOCA3 TIOCB3 TIOCC3 TIOCD3 51 52 53 54 Input output TGRA_3 to TGRD_3 input capture input output compare output PWM output pins TIOCA4 TIOCB4 55 56 Input output TGRA_4 and TGRB_4 input capture input output compare output PWM output pins TIOCA...

Page 58: ...og input pins for the A D converter ADTRG 136 Input Pin for input of an external trigger to start A D conversion D A converter DA5 to DA0 128 to 125 120 119 Output Analog input pins for the D A converter A D converter D A converter AVCC 111 Input The analog power supply pin for the A D converter and D A converter When the A D converter and D A converter are not used this pin should be connected to...

Page 59: ...4 33 3 Input output Six bit input output pins P97 to P90 128 to 121 Input Eight bit input pins PA7 to PA0 31 to 26 24 23 Input output Eight bit input output pins PB7 to PB0 22 to 19 17 to 14 Input output Eight bit input output pins PC7 to PC0 13 to 11 9 to 5 Input output Eight bit input output pins PD7 to PD0 80 to 73 Input output Eight bit input output pins PE7 to PE0 71 69 to 63 Input output Eig...

Page 60: ...Rev 1 0 09 01 page 16 of 904 ...

Page 61: ...2 bit registers Sixty five basic instructions 8 16 32 bit arithmetic and logic instructions Multiply and divide instructions Powerful bit manipulation instructions Eight addressing modes Register direct Rn Register indirect ERn Register indirect with displacement d 16 ERn or d 32 ERn Register indirect with post increment or pre decrement ERn or ERn Absolute address aa 8 aa 16 aa 24 or aa 32 Immedi...

Page 62: ...are as shown below Register configuration The MAC register is supported only by the H8S 2600 CPU Basic instructions The four instructions MAC CLRMAC LDMAC and STMAC are supported only by the H8S 2600 CPU The number of execution states of the MULXU and MULXS instructions Execution States Instruction Mnemonic H8S 2600 H8S 2000 MULXU MULXU B Rs Rd 3 12 MULXU W Rs ERd 4 20 MULXS MULXS B Rs Rd 4 13 MUL...

Page 63: ...ve been enhanced Signed multiply and divide instructions have been added Two bit shift and two bit rotate instructions have been added Instructions for saving and restoring multiple registers have been added A test and set instruction has been added Higher speed Basic instructions are executed twice as fast 2 1 3 Differences from H8 300H CPU In comparison to the H8 300H CPU the H8S 2000 CPU has th...

Page 64: ...es can be used Only the lower 16 bits of effective addresses EA are valid Exception vector table and memory indirect branch addresses In normal mode the top area starting at H 0000 is allocated to the exception vector table One branch address is stored per 16 bits The exception vector table in normal mode is shown in figure 2 1 For details of the exception vector table see section 4 Exception Hand...

Page 65: ...XR 1 Reserved 1 3 CCR CCR 3 PC 16 bits SP SP Notes 1 2 3 When EXR is not used it is not stored on the stack SP when EXR is not used Ignored when returning SP 2 Figure 2 2 Stack Structure in Normal Mode 2 2 2 Advanced Mode Address space Linear access to a maximum address space of 16 Mbytes is possible Extended registers En The extended registers E0 to E7 can be used as 16 bit registers They can als...

Page 66: ...t addressing mode aa 8 employed in the JMP and JSR instructions uses an 8 bit absolute address included in the instruction code to specify a memory operand that contains a branch address In advanced mode the operand is a 32 bit longword operand providing a 32 bit branch address The upper 8 bits of these 32 bits are a reserved area that is regarded as H 00 Branch addresses can be stored in the area...

Page 67: ... 1 Reserved 1 3 CCR PC 24 bits SP SP SP 2 Reserved a Subroutine Branch b Exception Handling Notes 1 2 3 When EXR is not used it is not stored on the stack SP when EXR is not used Ignored when returning Figure 2 4 Stack Structure in Advanced Mode ...

Page 68: ...byte architecturally 4 Gbyte address space in advanced mode The usable modes and address spaces differ depending on the product For details on each product refer to section 3 MCU Operating Modes H 0000 H FFFF Note For this LSI normal mode is not available H 00000000 H FFFFFFFF H 00FFFFFF 64 kbyte 16 Mbyte Not available in this LSI Program area Data area b Advanced Mode a Normal Mode Figure 2 5 Mem...

Page 69: ... E4 E5 E6 E7 R0H R1H R2H R3H R4H R5H R6H R7H R0L R1L R2L R3L R4L R5L R6L R7L SP PC EXR T I2 to I0 CCR I UI Stack pointer Program counter Extended control register Trace bit Interrupt mask bits Condition code register Interrupt mask bit User bit or interrupt mask bit Half carry flag User bit Negative flag Zero flag Overflow flag Carry flag ER0 ER1 ER2 ER3 ER4 ER5 ER6 ER7 SP I UI H U N Z V C CCR 7 6...

Page 70: ...re functionally equivalent providing a maximum sixteen 16 bit registers The E registers E0 to E7 are also referred to as extended registers When the general registers are used as 8 bit registers the R registers are divided into 8 bit general registers designated by the letters RH R0H to R7H and RL R0L to R7L These registers are functionally equivalent providing a maximum sixteen 8 bit registers Th...

Page 71: ...er that can be operated by the LDC STC ANDC ORC and XORC instructions When an instruction other than STC is executed all interrupts including NMI are masked in three states after the instruction is completed Bit Bit Name Initial Value R W Description 7 T 0 R W Trace Bit When this bit is set to 1 trace exception processing starts every when an instruction is executed When this bit is cleared to 0 i...

Page 72: ...PU status information including an interrupt mask bit I and half carry H negative N zero Z overflow V and carry C flags Operations can be performed on the CCR bits by the LDC STC ANDC ORC and XORC instructions The N Z V and C flags are used as branching conditions for conditional branch Bcc instructions ...

Page 73: ...he H flag is set to 1 if there is a carry or borrow at bit 11 and cleared to 0 otherwise When the ADD L SUB L CMP L or NEG L instruction is executed the H flag is set to 1 if there is a carry or borrow at bit 27 and cleared to 0 otherwise 4 U Undefined R W User Bit Can be written to and read from by software using the LDC STC ANDC ORC and XORC instructions 3 N Undefined R W Negative Flag Stores th...

Page 74: ...s 1 bit 4 bit BCD 8 bit byte 16 bit word and 32 bit longword data Bit manipulation instructions operate on 1 bit data by accessing bit n n 0 1 2 7 of byte operand data The DAA and DAS decimal adjust instructions treat byte data as two digits of 4 bit BCD data 2 5 1 General Register Data Formats Figure 2 9 shows the data formats of general registers 7 0 7 0 MSB LSB MSB LSB 7 0 4 3 Don t care Don t ...

Page 75: ...n RnH RnL MSB LSB General register ER General register E General register R General register RH General register RL Most significant bit Least significant bit Data Type Data Image Register Number Word data Word data Rn En Longword data Legend ERn Figure 2 9 General Register Data Formats 2 ...

Page 76: ...curs but the least significant bit of the address is regarded as 0 so the access starts at the preceding address This also applies to instruction fetches When SP ER7 is used as an address register to access the stack the operand size should be word size or longword size 7 0 7 6 5 4 3 2 1 0 MSB LSB MSB MSB LSB LSB Data Type Address 1 bit data Byte data Word data Address L Address L Address 2M Addre...

Page 77: ...ons AND OR XOR NOT B W L 4 Shift SHAL SHAR SHLL SHLR ROTL ROTR ROTXL ROTXR B W L 8 Bit manipulation BSET BCLR BNOT BTST BLD BILD BST BIST BAND BIAND BOR BIOR BXOR BIXOR B 14 Branch BCC 2 JMP BSR JSR RTS 5 System control TRAPA RTE SLEEP LDC STC ANDC ORC XORC NOP 9 Block data transfer EEPMOV 1 Total 65 Notes B Byte size W Word size L Longword size 1 POP W Rn and PUSH W Rn are identical to MOV W SP R...

Page 78: ...t register EAd Destination operand EAs Source operand EXR Extended control register CCR Condition code register N N negative flag in CCR Z Z zero flag in CCR V V overflow flag in CCR C C carry flag in CCR PC Program counter SP Stack pointer IMM Immediate data disp Displacement Addition Subtraction Multiplication Division Logical AND Logical OR Logical exclusive OR Move NOT logical complement 8 16 ...

Page 79: ...be used in this LSI POP W L SP Rn Pops a general register from the stack POP W Rn is identical to MOV W SP Rn POP L ERn is identical to MOV L SP ERn PUSH W L Rn SP Pushes a general register onto the stack PUSH W Rn is identcal to MOV W Rn SP PUSH L ERn is identical to MOV L ERn SP LDM L SP Rn register list Pops two or more general registers from the stack STM L Rn register list SP Pushes two or mo...

Page 80: ...e value 1 can be added to or subtracted from byte operands ADDS SUBS L Rd 1 Rd Rd 2 Rd Rd 4 Rd Adds or subtracts the value 1 2 or 4 to or from data in a 32 bit register DAA DAS B Rd decimal adjust Rd Decimal adjusts an addition or subtraction result in a general register by referring to CCR to produce 4 bit BCD data MULXU B W Rd Rs Rd Performs unsigned multiplication on data in two general registe...

Page 81: ...d Takes the two s complement arithmetic complement of data in a general register EXTU W L Rd zero extension Rd Extends the lower 8 bits of a 16 bit register to word size or the lower 16 bits of a 32 bit register to longword size by padding with zeros on the left EXTS W L Rd sign extension Rd Extends the lower 8 bits of a 16 bit register to word size or the lower 16 bits of a 32 bit register to lon...

Page 82: ...kes the one s complement logical complement of data in a general register Note Size refers to the operand size B Byte W Word L Longword Table 2 6 Shift Instructions Instruction Size Function SHAL SHAR B W L Rd shift Rd Performs an arithmetic shift on data in a general register 1 bit or 2 bit shift is possible SHLL SHLR B W L Rd shift Rd Performs a logical shift on data in a general register 1 bit ...

Page 83: ... operand and sets or clears the Z flag accordingly The bit number is specified by 3 bit immediate data or the lower three bits of a general register BAND B C bit No of EAd C Logically ANDs the carry flag with a specified bit in a general register or memory operand and stores the result in the carry flag BIAND B C bit No of EAd C Logically ANDs the carry flag with the inverse of a specified bit in ...

Page 84: ...ber is specified by 3 bit immediate data BLD B bit No of EAd C Transfers a specified bit in a general register or memory operand to the carry flag BILD B bit No of EAd C Transfers the inverse of a specified bit in a general register or memory operand to the carry flag The bit number is specified by 3 bit immediate data BST B C bit No of EAd Transfers the carry flag value to a specified bit in a ge...

Page 85: ... High C Z 0 BLS Low or same C Z 1 BCC BHS Carry clear high or same C 0 BCS BLO Carry set low C 1 BNE Not equal Z 0 BEQ Equal Z 1 BVC Overflow clear V 0 BVS Overflow set V 1 BPL Plus N 0 BMI Minus N 1 BGE Greater or equal N V 0 BLT Less than N V 1 BGT Greater than Z N V 0 BLE Less or equal Z N V 1 JMP Branches unconditionally to a specified address BSR Branches to a subroutine at a specified addres...

Page 86: ...ry The upper 8 bits are valid STC B W CCR EAd EXR EAd Transfers CCR or EXR contents to a general register or memory operand Although CCR and EXR are 8 bit registers word size transfers are performed between them and memory The upper 8 bits are valid ANDC B CCR IMM CCR EXR IMM EXR Logically ANDs the CCR or EXR contents with immediate data ORC B CCR IMM CCR EXR IMM EXR Logically ORs the CCR or EXR c...

Page 87: ...s of an operation field op a register field r an effective address extension EA and a condition field cc Figure 2 11 shows examples of instruction formats Operation field Indicates the function of the instruction the addressing mode and the operation to be carried out on the operand The operation field always includes the first four bits of the instruction Some instructions have two operation fiel...

Page 88: ...se the register direct and immediate addressing modes Data transfer instructions can use all addressing modes except program counter relative and memory indirect Bit manipulation instructions can use register direct register indirect or absolute addressing mode to specify an operand and register direct BSET BCLR BNOT and BTST instructions or immediate 3 bit addressing mode to specify a bit number ...

Page 89: ... the address of a memory operand After the operand is accessed 1 2 or 4 is added to the address register contents and the sum is stored in the address register The value added is 1 for byte access 2 for word access and 4 for longword access For word or longword transfer instructions the register value should be even Register Indirect with Pre Decrement ERn The value 1 2 or 4 is subtracted from an ...

Page 90: ...uction code specifying a vector address 2 7 7 Program Counter Relative d 8 PC or d 16 PC This mode can be used by the Bcc and BSR instructions An 8 bit or 16 bit displacement contained in the instruction code is sign extended to 24 bits and added to the 24 bit address indicated by the PC value to generate a 24 bit branch address Only the lower 24 bits of this branch address are valid the upper 8 b...

Page 91: ...anch address the least significant bit is regarded as 0 causing data to be accessed or the instruction code to be fetched at the address preceding the specified address For further information see section 2 5 2 Memory Data Formats Specified by aa 8 Specified by aa 8 Branch address Branch address Reserved a Normal Mode b Advanced Mode Note For this LSI normal mode is not available Figure 2 12 Branc...

Page 92: ...on t care 24 24 24 24 Addressing Mode and Instruction Format Effective Address Calculation Effective Address EA Register direct Rn General register contents General register contents General register contents General register contents Sign extension Register indirect ERn Register indirect with post increment or pre decrement Register indirect with post increment ERn Register indirect with pre decr...

Page 93: ...on Format Absolute address Immediate Effective Address Calculation Effective Address EA Sign extension Operand is immediate data 31 23 7 Program counter relative d 8 PC d 16 PC Memory indirect aa 8 Normal mode Advanced mode 31 0 Don t care 23 0 disp 0 31 23 31 0 Don t care disp op 23 op 8 abs 31 0 abs H 000000 7 8 0 15 31 23 31 0 Don t care 15 H 00 16 op abs 31 0 abs H 000000 7 8 0 31 24 24 24 PC ...

Page 94: ...ling state is a transient state that occurs when the CPU alters the normal processing flow due to an exception source such as a reset trace interrupt or trap instruction The CPU fetches a start address vector from the exception vector table and branches to that address For further details refer to section 4 Exception Handling Program execution state In this state the CPU executes program instructi...

Page 95: ...s low A transition can also be made to the reset state when the watchdog timer overflows 2 In every state when the STBY pin becomes low the hardware standby mode is entered 3 For details refer to section 22 Power Down Modes Figure 2 13 State Transitions 2 9 Usage Note 2 9 1 Note on Bit Manipulation Instructions Bit manipulation instructions such as BSET BCLR BNOT BST and BIST read data in byte uni...

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Page 97: ...mode in which the CPU can switch to access an external memory and peripheral devices at the beginning of a program execution Modes 3 is a boot mode in which the flash memory can be programmed or erased For details on the boot mode refer to section 20 ROM Do not change the MD2 to MD0 pin settings during operation Table 3 1 MCU Operating Mode Selection External Data Bus MCU Operating Mode 1 MD2 MD1 ...

Page 98: ...s 0 and cannot be modified 2 1 0 MDS2 MDS1 MDS0 R R R Mode Select 2 to 0 These bits indicate the input levels at pins MD2 to MD0 the current operating mode Bits MDS2 to MDS0 correspond to MD2 to MD0 MDS2 to MDS0 are read only bits and they cannot be written to The mode pin MD2 to MD0 input levels are latched into these bits when MDCR is read These latches are canceled by a reset Note Determined by...

Page 99: ...en to 0 in other than flash memory version 0 Flash memory control registers are not selected for area H FFFFC8 to H FFFFCB 1 Flash memory control registers are selected for area H FFFFC8 to H FFFFCB 2 0 Reserved This bit is always read as 0 and cannot be modified 1 EXPE R W External Bus Mode Enable Sets external bus mode In modes 1 2 and 4 to 6 this bit is fixed at 1 and cannot be modified In mode...

Page 100: ... areas by the bus controller the bus mode switches to 16 bits and port E functions as a data bus 3 3 3 Mode 3 This mode is a boot mode of the flash memory This mode is the same as mode 7 except for the programming and erasure on the flash memory 3 3 4 Mode 4 The CPU can access a 16 Mbyte address space in advanced mode The on chip ROM is enabled Ports A B and C function as input ports immediately a...

Page 101: ...program in an external ROM connected to the first half of area 0 is executed However if 16 bit access is designated for any area by the bus controller the bus mode switches to 16 bits and port E functions as a data bus User program mode is entered by setting 1 to the SWE bit of FLMCR1 3 3 7 Mode 7 The CPU can access a 16 Mbyte address space in advanced mode The on chip ROM is enabled and the chip ...

Page 102: ...A A A P A Port B A A P A P A A A P A Port C A A P A P A A A P A Port D D D P D P D D D P D Port E P D P D P D P D P D P D P D PF7 PF6 P C P C P C P C P C PF5 PF4 C C C C C PF3 P C P C P C P C P C Port F PF2 to PF0 P C P C P C P C P C P C P C PG6 to PG1 P C P C P C P C P C Port G PG0 P C P C P C P C P C P C P C Port H P C P C P C P C P C P C P C Legend P I O port A Address bus output D Data bus inp...

Page 103: ...a Reserved area H FF4000 H FF6000 H FFC000 H FFC800 Reserved area Reserved area Mode 4 Expanded mode with on chip ROM enabled H 000000 H FFFC00 On chip ROM H FFFFFF H FFFF00 H FFFF20 H 060000 External address space Note 1 This area is specified as external address space by clearing the RAME bit in SYSCR to 0 2 When EXPE 1 external address space when EXPE 0 reserved area 3 On chip RAM is used for f...

Page 104: ...F4000 H FF6000 H FFC000 H FFC800 H FF4000 H FF6000 H FFC000 H FFC800 Reserved area Reserved area Reserved area On chip RAM external address space 1 External address space Internal I O registers On chip RAM external address space 3 Reserved area External address space reserved area 2 External address space reserved area 2 Internal I O registers Internal I O registers Note 1 This area is specified a...

Page 105: ...FC800 Reserved area Reserved area Mode 4 Expanded mode with on chip ROM enabled H 000000 H FFFC00 On chip ROM H FFFFFF H FFFF00 H FFFF20 H 060000 External address space Note 1 This area is specified as external address space by clearing the RAME bit in SYSCR to 0 2 When EXPE 1 external address space when EXPE 0 reserved area 3 On chip RAM is used for flash memory programming Do not clear the RAME ...

Page 106: ...H FFFF20 H FFFFFF H FFFF00 H FFFF20 H 060000 H 100000 H 160000 External address space reserved area On chip RAM External address space Internal I O registers On chip RAM external address space 3 Internal I O registers Internal I O registers External address space reserved area 2 External address space reserved area 2 Note 1 This area is specified as external address space by clearing the RAME bit ...

Page 107: ...ion handling ends if the trace T bit in the EXR is set to 1 Direct transition 2 Starts when the direct transition occurs by execution of the SLEEP instruction Interrupt Starts when execution of the current instruction or exception handling ends if an interrupt request has been issued 3 Low Trap instruction 4 Started by execution of a trap instruction TRAPA Notes 1 Traces are enabled only in interr...

Page 108: ...0017 H 002C to H 002F Reserved for system use 12 H 0018 to H 0019 H 0030 to H 0033 13 H 001A to H 001B H 0034 to H 0037 14 H 001C to H 001D H 0038 to H 003B 15 H 001E to H 001F H 003C to H 003F External interrupt IRQ0 16 H 0020 to H 0021 H 0040 to H 0043 IRQ1 17 H 0022 to H 0023 H 0044 to H 0047 IRQ2 18 H 0024 to H 0025 H 0048 to H 004B IRQ3 19 H 0026 to H 0027 H 004C to H 004F IRQ4 20 H 0028 to H...

Page 109: ...e chip during operation hold the 5 6 pin low for at least 20 states A reset initializes the internal state of the CPU and the registers of on chip supporting modules The chip can also be reset by overflow of the watchdog timer For details see section 14 Watchdog Timer The interrupt control mode is 0 immediately after reset 4 3 1 Reset exception handling When the 5 6 pin goes high after being held ...

Page 110: ...ing vector address when reset 1 H 000000 3 H 000002 2 4 Start address contents of reset exception handling vector address 5 Start address 5 2 4 6 First program instruction φ Internal address bus Internal read signal Internal write signal Internal data bus 1 2 4 6 3 5 Figure 4 1 Reset Sequence Advanced Mode with On chip ROM Enabled ...

Page 111: ...t before the stack pointer SP is initialized the PC and CCR will not be saved correctly leading to a program crash To prevent this all interrupt requests including NMI are disabled immediately after a reset Since the first instruction of a program is always executed immediately after the reset state ends make sure that this instruction initializes the stack pointer example MOV L xx 32 SP 4 3 3 On ...

Page 112: ... the trace exception handling routine Table 4 3 Status of CCR and EXR after Trace Exception Handling CCR EXR Interrupt Control Mode I UI I2 to I0 T 0 Trace exception handling cannot be used 2 1 0 Legend 1 Set to 1 0 Cleared to 0 Retains value prior to execution 4 5 Interrupts Interrupts are controlled by the interrupt controller The interrupt controller has two interrupt control modes and can assi...

Page 113: ...bit is cleared to 0 3 A vector address corresponding to the interrupt source is generated the start address is loaded from the vector table to the PC and program execution starts from that address The TRAPA instruction fetches a start address from a vector table entry corresponding to a vector number from 0 to 3 as specified in the instruction code Table 4 4 shows the status of CCR and EXR after e...

Page 114: ...n handling CCR CCR 1 PC 16 bits SP EXR Reserved 1 CCR CCR 1 PC 16 bits SP CCR PC 24 bits SP EXR Reserved 1 CCR PC 24 bits SP a Normal Modes 2 b Advanced Modes Interrupt control mode 0 Interrupt control mode 2 Interrupt control mode 0 Interrupt control mode 2 Note 1 2 Ignored on return Normal modes are not available in this LSI Figure 4 3 Stack Status after Exception Handling ...

Page 115: ...instructions to restore registers POP W Rn or MOV W SP Rn POP L ERn or MOV L SP ERn Setting SP to an odd value may lead to a malfunction Figure 4 4 shows an example of operation when the SP value is odd SP CCR PC R1L SP Condition code register Program counter General register R1L Stack pointer CCR SP SP R1L H FFFEFA H FFFEFB H FFFEFC H FFFEFD H FFFEFE H FFFEFF PC PC TRAP instruction executed SP se...

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Page 117: ... except NMI NMI is assigned the highest priority level of 8 and can be accepted at all times Independent vector addresses All interrupt sources are assigned independent vector addresses making it unnecessary for the source to be identified in the interrupt handling routine Seventeen external interrupts NMI is the highest priority interrupt and is accepted at all times Rising edge or falling edge c...

Page 118: ...nit ISR ISCR ITSR IER IPR Interrupt controller Priority determination Interrupt request Vector number I I2 to I0 CCR EXR CPU Legend ISCR IRQ sense control register IER IRQ enable register ISR IRQ status register IPR Interrupt priority register INTCR Interrupt control register ITSR IRQ pin select register SSIER Software standby release IRQ enable register SSIER Figure 5 1 Block Diagram of Interrupt...

Page 119: ...ters Interrupt control register INTCR IRQ sense control register H ISCRH IRQ sense control register L ISCRL IRQ enable register IER IRQ status register ISR IRQ pin select register ITSR Software standby release IRQ enable register SSIER Interrupt priority register A IPRA Interrupt priority register B IPRB Interrupt priority register C IPRC Interrupt priority register D IPRD Interrupt priority regis...

Page 120: ...ting prohibited 3 NMIEG 0 R W NMI Edge Select Selects the input edge for the NMI pin 0 Interrupt request generated at falling edge of NMI input 1 Interrupt request generated at rising edge of NMI input 2 to 0 0 Reserved These bits are always read as 0 and cannot be modified 5 3 2 Interrupt Priority Registers A to K IPRA to IPRK IPR are eleven 16 bit readable writable registers that set priorities ...

Page 121: ... read as 0 and cannot be modified 10 9 8 IPR10 IPR9 IPR8 1 1 1 R W R W R W Sets the priority of the corresponding interrupt source 000 Priority level 0 Lowest 001 Priority level 1 010 Priority level 2 011 Priority level 3 100 Priority level 4 101 Priority level 5 110 Priority level 6 111 Priority level 7 Highest 7 0 Reserved This bit is always read as 0 and cannot be modified 6 5 4 IPR6 IPR5 IPR4 ...

Page 122: ... IER IER controls enabling and disabling of interrupt requests IRQ15 to IRQ0 Bit Bit Name Initial Value R W Description 15 IRQ15E 0 R W IRQ15 Enable The IRQ15 interrupt request is enabled when this bit is 1 14 IRQ14E 0 R W IRQ14 Enable The IRQ14 interrupt request is enabled when this bit is 1 13 IRQ13E 0 R W IRQ13 Enable The IRQ13 interrupt request is enabled when this bit is 1 12 IRQ12E 0 R W IRQ...

Page 123: ... IRQ6 interrupt request is enabled when this bit is 1 5 IRQ5E 0 R W IRQ5 Enable The IRQ5 interrupt request is enabled when this bit is 1 4 IRQ4E 0 R W IRQ4 Enable The IRQ4 interrupt request is enabled when this bit is 1 3 IRQ3E 0 R W IRQ3 Enable The IRQ3 interrupt request is enabled when this bit is 1 2 IRQ2E 0 R W IRQ2 Enable The IRQ2 interrupt request is enabled when this bit is 1 1 IRQ1E 0 R W ...

Page 124: ... falling and rising edges of 5448 input 13 12 IRQ14SCB IRQ14SCA 0 0 R W R W IRQ14 Sense Control B IRQ14 Sense Control A 00 Interrupt request generated at 5447 input low level 01 Interrupt request generated at falling edge of 5447 input 10 Interrupt request generated at rising edge of 5447 input 11 Interrupt request generated at both falling and rising edges of 5447 input 11 10 IRQ13SCB IRQ13SCA 0 ...

Page 125: ...nput 10 Interrupt request generated at rising edge of 5444 input 11 Interrupt request generated at both falling and rising edges of 5444 input 5 4 IRQ10SCB IRQ10SCA 0 0 R W R W IRQ10 Sense Control B IRQ10 Sense Control A 00 Interrupt request generated at 5443 input low level 01 Interrupt request generated at falling edge of 5443 input 10 Interrupt request generated at rising edge of 5443 input 11 ...

Page 126: ... 14 IRQ7SCB IRQ7SCA 0 0 R W R W IRQ7 Sense Control B IRQ7 Sense Control A 00 Interrupt request generated at 54 input low level 01 Interrupt request generated at falling edge of 54 input 10 Interrupt request generated at rising edge of 54 input 11 Interrupt request generated at both falling and rising edges of 54 input 13 12 IRQ6SCB IRQ6SCA 0 0 R W R W IRQ6 Sense Control B IRQ6 Sense Control A 00 I...

Page 127: ...R W R W IRQ4 Sense Control B IRQ4 Sense Control A 00 Interrupt request generated at 547 input low level 01 Interrupt request generated at falling edge of 547 input 10 Interrupt request generated at rising edge of 547 input 11 Interrupt request generated at both falling and rising edges of 547 input 7 6 IRQ3SCB IRQ3SCA 0 0 R W R W IRQ3 Sense Control B IRQ3 Sense Control A 00 Interrupt request gener...

Page 128: ... W R W IRQ1 Sense Control B IRQ1 Sense Control A 00 Interrupt request generated at 544 input low level 01 Interrupt request generated at falling edge of 544 input 10 Interrupt request generated at rising edge of 544 input 11 Interrupt request generated at both falling and rising edges of 544 input 1 0 IRQ0SCB IRQ0SCA 0 0 R W R W IRQ0 Sense Control B IRQ0 Sense Control A 00 Interrupt request genera...

Page 129: ...R W R W R W R W R W R W R W R W R W R W Setting conditions When the interrupt source selected by ISCR occurs Clearing conditions Cleared by reading IRQnF flag when IRQnF 1 then writing 0 to IRQnF flag When interrupt exception handling is executed when low level detection is set and 54Q input is high When IRQn interrupt exception handling is executed when falling rising or both edge detection is se...

Page 130: ...ts 5447 input pin 0 PF1 1 P26 13 ITS13 0 R W Selects 5446 input pin 0 P65 1 P25 12 ITS12 0 R W Selects 5445 input pin 0 P64 1 P24 11 ITS11 0 R W Selects 5444 input pin 0 P63 1 P23 10 ITS10 0 R W Selects 5443 input pin 0 P62 1 P22 9 ITS9 0 R W Selects 54 input pin 0 P61 1 P21 8 ITS8 0 R W Selects 54 input pin 0 P60 1 P20 7 ITS7 0 R W Selects 54 input pin 0 PA7 1 PH3 6 ITS6 0 R W Selects 549 input p...

Page 131: ...S5 0 R W Selects 548 input pin 0 PA5 1 P85 4 ITS4 0 R W Selects 547 input pin 0 PA4 1 P84 3 ITS3 0 R W Selects 546 input pin 0 P53 1 P83 2 ITS2 0 R W Selects 545 input pin 0 P52 1 P82 1 ITS1 0 R W Selects 544 input pin 0 P51 1 P81 0 ITS0 0 R W Selects 543 input pin 0 P50 1 P80 ...

Page 132: ...Sources 5 4 1 External Interrupts There are seventeen external interrupts NMI and IRQ15 to IRQ0 These interrupts can be used to restore the chip from software standby mode NMI Interrupt Nonmaskable interrupt request NMI is the highest priority interrupt and is always accepted by the CPU regardless of the interrupt control mode or the status of the CPU interrupt mask bits The NMIEG bit in INTCR can...

Page 133: ...terrupts IRQ15 to IRQ0 is shown in figure 5 2 IRQn interrupt request IRQnE IRQnF S R Q Clear signal Edge level detection circuit IRQnSCA IRQnSCB input Note n 15 to 0 Figure 5 2 Block Diagram of Interrupts IRQ15 to IRQ0 5 4 2 Internal Interrupts The sources for internal interrupts from on chip supporting modules have the following features For each on chip supporting module there are flags that ind...

Page 134: ...rces vector addresses and interrupt priorities For default priorities the lower the vector number the higher the priority When interrupt control mode 2 is set priorities among modules can be set by means of the IPR Modules set at the same priority will conform to their default priorities Priorities within a module are fixed ...

Page 135: ...B6 to IPRB4 IRQ7 23 H 005C IPRB2 to IPRB0 IRQ8 24 H 0060 IPRC14 to IPRC12 IRQ9 25 H 0064 IPRC10 to IPRC8 IRQ10 26 H 0068 IPRC6 to IPRC4 IRQ11 27 H 006C IPRC2 to IPRC0 IRQ12 28 H 0070 IPRD14 to IPRD12 IRQ13 29 H 0074 IPRD10 to IPRD8 IRQ14 30 H 0078 IPRD6 to IPRD4 IRQ15 31 H 007C IPRD2 to IPRD0 DTC SWDTEND 32 H 0080 IPRE14 to IPRE12 WDT WOVI 33 H 0084 IPRE10 to IPRE8 Reserved for system use 34 H 008...

Page 136: ...0C4 TCI1V 50 H 00C8 TCI1U 51 H 00CC TPU_2 TGI2A 52 H 00D0 IPRG14 to IPRG12 TGI2B 53 H 00D4 TCI2V 54 H 00D8 TCI2U 55 H 00DC TPU_3 TGI3A 56 H 00E0 IPRG10 to IPRG8 TGI3B 57 H 00E4 TGI3C 58 H 00E8 TGI3D 59 H 00EC TCI3V 60 H 00F0 61 H 00F4 62 H 00F8 Reserved for system use 63 H 00FC TPU_4 TGI4A 64 H 0100 IPRG6 to IPRG4 TGI4B 65 H 0104 TCI4V 66 H 0108 TCI4U 67 H 010C TPU_5 TGI5A 68 H 0110 IPRG2 to IPRG0...

Page 137: ...MTEND0B 81 H 0144 DMTEND1A 82 H 0148 DMTEND1B 83 H 014C EXDMAC 84 H 0150 IPRH0 to IPRH0 Reserved for system use 85 H 0154 IPRI14 to IPRI12 EXDMTEND2 86 H 0158 IPRI10 to IPRI8 EXDMTEND3 87 H 015C IPRI6 to IPRI4 SCI_0 ERI0 88 H 0160 IPRI2 to IPRI0 RXI0 89 H 0164 TXI0 90 H 0168 TEI0 91 H 016C SCI_1 ERI1 92 H 0170 IPRJ14 to IPRJ12 RXI1 93 H 0174 TXI1 94 H 0178 TEI1 95 H 017C SCI_2 ERI2 96 H 0180 IPRJ1...

Page 138: ... H 01B0 IPRK14 to IPRK12 109 H 01B4 110 H 01B8 Reserved for system use 111 H 01BC 112 H 01C0 IPRK10 to IPRK8 113 H 01C4 114 H 01C8 Reserved for system use 115 H 01CC IICI0 116 H 01D0 IPRK6 to IPRK4 Reserved for system use 117 H 01D4 IICI1 118 H 01D8 Reserved for system use 119 H 01DC 120 H 01E0 IPRK2 to IPRK0 121 H 01E4 122 H 01E8 123 H 01EC 124 H 01F0 125 H 01F4 126 H 01F8 Reserved for system use...

Page 139: ...ceptance operation in this case 1 If an interrupt source occurs when the corresponding interrupt enable bit is set to 1 an interrupt request is sent to the interrupt controller 2 If the I bit is set to 1 only an NMI interrupt is accepted and other interrupt requests are held pending If the I bit is cleared an interrupt request is accepted 3 Interrupt requests are sent to the interrupt controller t...

Page 140: ...errupt generated NMI IRQ0 IRQ1 IICI1 I 0 Save PC and CCR I 1 Read vector address Branch to interrupt handling routine Yes No Yes Yes Yes No No No Yes Yes No Hold pending Figure 5 3 Flowchart of Procedure Up to Interrupt Acceptance in Interrupt Control Mode 0 ...

Page 141: ...ble 5 2 is selected 3 Next the priority of the selected interrupt request is compared with the interrupt mask level set in EXR An interrupt request with a priority no higher than the mask level set at that time is held pending and only an interrupt request with a priority higher than the interrupt mask level is accepted 4 When the CPU accepts an interrupt request it starts interrupt exception hand...

Page 142: ...upt handling routine Hold pending Level 1 interrupt Mask level 0 Yes Yes No Yes Yes Yes No Yes Yes No No No No No No Figure 5 4 Flowchart of Procedure Up to Interrupt Acceptance in Interrupt Control Mode 2 5 6 3 Interrupt Exception Handling Sequence Figure 5 5 shows the interrupt exception handling sequence The example shown is for the case where interrupt control mode 0 is set in advanced mode an...

Page 143: ...nal read signal Internal write signal Internal data bus φ 3 1 2 4 3 5 7 Instruction prefetch address Not executed This is the contents of the saved PC the return address Instruction code Not executed Instruction prefetch address Not executed SP 2 SP 4 Saved PC and saved CCR Vector address Interrupt handling routine start address Vector address contents Interrupt handling routine start address 13 1...

Page 144: ...Interrupt control mode 0 Interrupt control mode 2 Interrupt control mode 0 Interrupt control mode 2 1 Interrupt priority determination 1 3 3 3 3 2 Number of wait states until executing instruction ends 2 1 to 19 2 SI 1 to 19 2 SI 1 to 19 2 SI 1 to 19 2 SI 3 PC CCR EXR stack save 2 SK 3 SK 2 SK 3 SK 4 Vector fetch SI SI 2 SI 2 SI 5 Instruction fetch 3 2 SI 2 SI 2 SI 2 SI 6 Internal processing 4 2 2...

Page 145: ...SJ Stack manipulation SK Legend m Number of wait states in an external device access 5 6 5 DTC and DMAC Activation by Interrupt The DTC and DMAC can be activated by an interrupt In this case the following options are available Interrupt request to CPU Activation request to DTC Activation request to DMAC Selection of a number of the above For details of interrupt requests that can be used to activa...

Page 146: ...n completion of the instruction However if there is an interrupt request of higher priority than that interrupt interrupt exception handling will be executed for the higher priority interrupt and the lower priority interrupt will be ignored The same also applies when an interrupt source flag is cleared to 0 Figure 5 6 shows an example in which the TCIEV bit in the TPU s TIER_0 register is cleared ...

Page 147: ...truction an interrupt request including NMI issued during the transfer is not accepted until the transfer is completed With the EEPMOV W instruction if an interrupt request is issued during the transfer interrupt exception handling starts at a break in the transfer cycle The PC value saved on the stack in this case is the address of the next instruction Therefore if an interrupt is generated durin...

Page 148: ...Rev 1 0 09 01 page 104 of 904 ...

Page 149: ...each area Burst ROM DRAM or synchronous DRAM interface can be set Basic bus interface Chip select signals 63 to 6 can be output for areas 0 to 7 8 bit access or 16 bit access can be selected for each area 2 state access or 3 state access can be selected for each area Program wait states can be inserted for each area Burst ROM interface Burst ROM interface can be set independently for areas 0 and 1...

Page 150: ...ge signal DTC bus acknowledge signal DMAC bus acknowledge signal ABWCR ASTCR WTCRAH WTCRAL WTCRBH WTCRBL RDNCR DRAMCR Legend ABWCR Bus width control register ASTCR Access state control register WTCRAH WTCRAL WTCRBH and WTCRBL Wait control registers AH AL BH and BL RDNCR Read strobe timing control register CSACRH and CSACRL assertion period control registers H and L BROMCRH Area 0 burst ROM interfa...

Page 151: ...n to and lower half D7 to D0 of data bus is enabled Chip select 0 63 Output Strobe signal indicating that area 0 is selected Chip select 1 64 Output Strobe signal indicating that area 1 is selected Chip select 2 row address strobe 2 row address strobe 65 5 65 5 6 Output Strobe signal indicating that area 2 is selected DRAM row address strobe signal when area 2 is DRAM space or areas 2 to 5 are set...

Page 152: ...e signal indicating that area 7 is selected Upper column address strobe upper data mask enable 8 6 408 Output 16 bit DRAM space upper column address strobe signal 8 bit DRAM space column address strobe signal upper data mask signal of 16 bit synchronous DRAM space or data mask signal of 8 bit synchronous DRAM space Lower column address strobe lower data mask enable 6 40 Output 16 bit DRAM space lo...

Page 153: ...MAC 4 Output Data transfer acknowledge signal for single address transfer by EXDMAC channel 1 Data transfer acknowledge 0 EXDMAC 3 Output Data transfer acknowledge signal for single address transfer by EXDMAC channel 0 Note These pins are not used for the H8S 2378 Series 6 3 Register Descriptions The bus controller has the following registers Bus width control register ABWCR Access state control r...

Page 154: ... 7 to 0 Note In modes 2 4 and 6 ABWCR is initialized to 1 In modes 1 5 and 7 ABWCR is initialized to 0 6 3 2 Access State Control Register ASTCR ASTCR designates each area in the external address space as either 2 state access space or 3 state access space Bit Bit Name Initial Value R W Description 7 6 5 4 3 2 1 0 AST7 AST6 AST5 AST4 AST3 AST2 AST1 AST0 1 1 1 1 1 1 1 1 R W R W R W R W R W R W R W ...

Page 155: ... is always read as 0 and cannot be modified 14 13 12 W72 W71 W70 1 1 1 R W R W R W Area 7 Wait Control 2 to 0 These bits select the number of program wait states when accessing area 7 while AST7 bit in ASTCR 1 000 Program wait not inserted 001 1 program wait state inserted 010 2 program wait states inserted 011 3 program wait states inserted 100 4 program wait states inserted 101 5 program wait st...

Page 156: ... inserted 110 6 program wait states inserted 111 7 program wait states inserted WTARAL Bit Bit Name Initial Value R W Description 7 0 R Reserved This bit is always read as 0 and cannot be modified 6 5 4 W52 W51 W50 1 1 1 R W R W R W Area 5 Wait Control 2 to 0 These bits select the number of program wait states when accessing area 5 while AST5 bit in ASTCR 1 000 Program wait not inserted 001 1 prog...

Page 157: ...serted 110 6 program wait states inserted 111 7 program wait states inserted WTCRBH Bit Bit Name Initial Value R W Description 15 0 R Reserved This bit is always read as 0 and cannot be modified 14 13 12 W32 W31 W30 1 1 1 R W R W R W Area 3 Wait Control 2 to 0 These bits select the number of program wait states when accessing area 3 while AST3 bit in ASTCR 1 000 Program wait not inserted 001 1 pro...

Page 158: ...00 Program wait not inserted 001 1 program wait state inserted 010 2 program wait states inserted 011 3 program wait states inserted 100 4 program wait states inserted 101 5 program wait states inserted 110 6 program wait states inserted 111 7 program wait states inserted 000 Synchronous DRAM of CAS latency 1 is connected to areas 2 to 5 001 Synchronous DRAM of CAS latency 2 is connected to areas ...

Page 159: ... 100 4 program wait states inserted 101 5 program wait states inserted 110 6 program wait states inserted 111 7 program wait states inserted 3 0 R Reserved This bit is always read as 0 and cannot be modified 2 1 0 W02 W01 W00 1 1 1 R W R W R W Area 0 Wait Control 2 to 0 These bits select the number of program wait states when accessing area 0 while AST0 bit in ASTCR 1 000 Program wait not inserted...

Page 160: ...ead strobe in a corresponding area read access As shown in figure 6 2 the read strobe for an area for which the RDNn bit is set to 1 is negated one half state earlier than that for an area for which the RDNn bit is cleared to 0 The read data setup and hold time specifications are also one half state earlier 0 In an area n read access the 5 is negated at the end of the read cycle 1 In an area n rea...

Page 161: ...y the 6Q and address signals are asserted is inserted before the normal access cycle 0 In area n basic bus interface access the 6Q and address assertion period Th is not extended 1 In area n basic bus interface access the 6Q and address assertion period Th is extended n 7 to 0 CSACRL Bit Bit Name Initial Value R W Description 7 6 5 4 3 2 1 0 CSXT7 CSXT6 CSXT5 CSXT4 CSXT3 CSXT2 CSXT1 CSXT0 0 0 0 0 ...

Page 162: ...Rev 1 0 09 01 page 118 of 904 Th Address T1 T2 T3 Tt Bus cycle Data Write Data Read Figure 6 3 6 6 6 6 and Address Assertion Period Extension Example of 3 State Access Space and RDNn 0 ...

Page 163: ...ce or burst ROM interface 0 Basic bus interface space 1 Burst ROM interface space 6 5 4 BSTSn2 BSTSn1 BSTSn0 0 0 0 R W R W R W Burst Cycle Select These bits select the number of burst cycle states 000 1 state 001 2 states 010 3 states 011 4 states 100 5 states 101 6 states 110 7 states 111 8 states 3 2 0 0 R W R W Reserved These bits are always read as 0 The initial value should not be changed 1 0...

Page 164: ...signal BREQO to the external bus master in the external bus released state when an internal bus master performs an external address space access or when a refresh request is generated 0 5 42 output disabled 5 42 pin can be used as I O port 1 5 42 output enabled 13 0 R W Reserved This bit is always read as 0 The initial value should not be changed 12 IDLC 1 R W Idle Cycle State Number Select Specif...

Page 165: ...ite data buffer function not used 1 Write data buffer function used 8 WAITE 0 R W 7 Pin Enable Selects enabling or disabling of wait input by the 7 pin 0 Wait input by 7 pin disabled 7 pin can be used as I O port 1 Wait input by 7 pin enabled 7 to 3 0 R W Reserved These are readable writable bits but the write value should always be 0 2 ICIS2 0 R W Idle Cycle Insert 2 When an external write cycle ...

Page 166: ...from the OE pin The CKE signal is common to the continuous synchronous DRAM space 0 2 CKE signal output disabled 2 CKE pin can be used as I O port 1 2 CKE signal output enabled 14 RAST 0 R W 5 6 Assertion Timing Select Selects whether in DRAM access the 5 6 signal is asserted from the start of the Tr cycle rising edge of ø or from the falling edge of ø Figure 6 4 shows the relationship between the...

Page 167: ... possible to connect large capacity DRAM exceeding 2 Mbytes per area In this case the 5 6 signal is output from the 65 pin When continuous synchronous DRAM space is set it is possible to connect large capacity synchronous DRAM exceeding 2 Mbytes per area In this case the 5 6 6 and signals are output from 65 66 and 67 pins respectively When synchronous DRAM mode is set the mode registers of the syn...

Page 168: ...s interrupted by an access to normal space an access to an internal I O register etc this bit selects whether the 5 6 signal is held low while waiting for the next DRAM access 5 6 down mode or is driven high again 5 6 up mode The setting of this bit is valid only when the BE bit is set to 1 If this bit is cleared to 0 when set to 1 in the 5 6 down state the 5 6 down state is cleared at that point ...

Page 169: ...or DMAC dual address transfers 0 Full access is always executed 1 Burst access is enabled 4 EDDS 0 R W EXDMAC Single Address Transfer Option Selects whether full access is always performed or burst access is enabled when EXDMAC single address transfer is performed on the DRAM synchronous DRAM When the BE bit is cleared to 0 in DRAMCR disabling DRAM synchronous DRAM burst access EXDMAC single addre...

Page 170: ...mand Precharge sel is output to the upper column address For details refer to sections 6 6 2 and 6 7 2 Address Multiplex DRAM interface 000 8 bit shift When 8 bit access space is designated Row address bits A23 to A8 used for comparison When 16 bit access space is designated Row address bits A23 to A9 used for comparison 001 9 bit shift When 8 bit access space is designated Row address bits A23 to...

Page 171: ...ss space is designated Row address bits A23 to A9 used for comparison The precharge sel is A15 to A9 of the column address 101 9 bit shift When 8 bit access space is designated Row address bits A23 to A9 used for comparison When 16 bit access space is designated Row address bits A23 to A10 used for comparison The precharge sel is A15 to A10 of the column address 110 10 bit shift When 8 bit access ...

Page 172: ...s A23 to A11 used for comparison When 16 bit access space is designated Row address bits A23 to A12 used for comparison The precharge sel is A15 to A12 of the column address Tp Address RAST 0 RAST 1 Tr Tc1 Tc2 Bus cycle Row address Column address Figure 6 4 5 6 5 6 5 6 5 6 Signal Assertion Timing 2 State Column Address Output Cycle Full Access ...

Page 173: ... ICIS2 ICIS1 ICIS0 and IDLC in BCR register 0 Idle cycle not inserted 1 Idle cycle inserted 14 0 R W Reserved This bit is always read as 0 The initial value should not be changed 13 12 TPC1 TPC0 0 0 R W R W Precharge State Control These bits select the number of states in the RAS precharge cycle in normal access and refreshing 00 1 state 01 2 states 10 3 states 11 4 states 11 SDWCD 0 R W CAS Laten...

Page 174: ...d 3 CKSPE 0 R W Clock Suspend Enable Enables clock suspend mode for extend read data during DMAC and EXDMAC single address transfer with the synchronous DRAM interface 0 Disables clock suspend mode 1 Enables clock suspend mode 2 0 R W Reserved This bit is always read as 0 The initial value should not be changed 1 0 RDXC1 RDXC0 0 0 R W R W Read Data Extension Cycle Number Selection Selects the numb...

Page 175: ...Column address Column address Row address Precharge sel Row address Column address High SDWCD 1 CKE Data bus Address bus PALL ACTV NOP WRIT Row address Precharge sel Row address Column address High Figure 6 5 CAS Latency Control Cycle Disable Timing during Continuous Synchronous DRAM Space Write Access for CAS Latency 2 ...

Page 176: ...ndition When RTCOR RTCNT 14 CMIE 0 R W Compare Match Interrupt Enable Enables or disables interrupt requests CMI by the CMF flag when the CMF flag is set to 1 This bit is valid when refresh control is not performed When the refresh control is performed this bit is always cleared to 0 and cannot be modified 0 Interrupt request by CMF flag disabled 1 Interrupt request by CMF flag enabled 13 12 RCW1 ...

Page 177: ...unt on ø 128 101 Count on ø 512 110 Count on ø 2048 111 Count on ø 4096 7 RFSHE 0 R W Refresh Control Refresh control can be performed When refresh control is not performed the refresh timer can be used as an interval timer 0 Refresh control is not performed 1 Refresh control is performed 6 CBRM 0 R W CBR Refresh Control Selects CBR refreshing performed in parallel with other external accesses or ...

Page 178: ...hen a transition is made to the software standby state This bit is valid when the RFSHE bit is set to 1 enabling refresh operations It is cleared after recovery from software standby mode 0 Self refreshing is disabled 1 Self refreshing is enabled 2 1 0 TPCS2 TPCS1 TPCS0 0 0 0 R W R W R W Self Refresh Precharge Cycle Control These bits select the number of states in the precharge cycle immediately ...

Page 179: ...12 Refresh Time Constant Register RTCOR RTCOR is an 8 bit readable writable register that sets the period for compare match operations with RTCNT The values of RTCOR and RTCNT are constantly compared and if they match the CMF flag in REFCR is set to 1 and RTCNT is cleared to H 00 RTCOR is initialized to H FF by a reset and in hardware standby mode It is not initialized in software standby mode 6 4...

Page 180: ...2 Mbytes H 3FFFFF H 400000 Area 2 2 Mbytes H 5FFFFF H 600000 Area 3 2 Mbytes H 7FFFFF H 800000 Area 4 2 Mbytes H 9FFFFF H A00000 Area 5 2 Mbytes H BFFFFF H C00000 Area 6 2 Mbytes H DFFFFF H E00000 Area 7 2 Mbytes H FFFF Advanced mode Normal mode Note Not available in this LSI Figure 6 6 Area Divisions ...

Page 181: ...ccess states can be selected with ASTCR An area for which 2 state access is selected functions as a 2 state access space and an area for which 3 state access is selected functions as a 3 state access space With the DRAM or synchronous DRAM interface and burst ROM interface the number of access states may be determined without regard to the setting of ASTCR When 2 state access space is designated w...

Page 182: ...nd of the read cycle for the read strobe 5 used in the basic bus interface space Chip Select 6 6 6 6 Assertion Period Extension States Some external I O devices require a setup time and hold time between address and 6 signals and strobe signals such as 5 5 and 5 CSACR can be used to insert states in which only the 6 6 and address signals are asserted before and after a basic bus space access cycle...

Page 183: ...sic bus interface or burst ROM interface can be selected for area 0 Area 1 In externally expanded mode all of area 1 is external address space When area 1 external address space is accessed the 64 signal can be output Either basic bus interface or burst ROM interface can be selected for area 1 Areas 2 to 5 In externally expanded mode areas 2 to 5 are all external address space When area 2 to 5 ext...

Page 184: ...tputs low when the corresponding external space area is accessed Figure 6 7 shows an example of 63 to 6 signals output timing Enabling or disabling of 63 to 6 signals output is set by the data direction register DDR bit for the port corresponding to the 63 to 6 pins In expanded mode with on chip ROM disabled the 63 pin is placed in the output state after a reset Pins 64 to 6 are placed in the inpu...

Page 185: ...nt function and when accessing external address space controls whether the upper data bus D15 to D8 or lower data bus D7 to D0 is used according to the bus specifications for the area being accessed 8 bit access space or 16 bit access space and the data size 8 Bit Access Space Figure 6 8 illustrates data alignment control for the 8 bit access space With the 8 bit access space the upper data bus D1...

Page 186: ...s D15 to D8 and lower data bus D7 to D0 are used for accesses The amount of data that can be accessed at one time is one byte or one word and a longword access is executed as two word accesses In byte access whether the upper or lower data bus is used is determined by whether the address is even or odd The upper data bus is used for an even address and the lower data bus for an odd address D15 D8 ...

Page 187: ...Strobe Upper Data Bus D15 to D8 Lower Data Bus D7 to D0 8 bit access Byte Read 5 Valid Invalid space Write 5 Hi Z 16 bit access Byte Read Even 5 Valid Invalid space Odd Invalid Valid Write Even 5 Valid Hi Z Odd 5 Hi Z Valid Word Read 5 Valid Valid Write 5 5 Valid Valid Note Hi Z High impedance state Invalid Input state input value is ignored 6 5 3 Basic Timing 8 Bit 2 State Access Space Figure 6 1...

Page 188: ...ge 144 of 904 Bus cycle T1 T2 Address bus ø D15 to D8 Valid D7 to D0 Invalid Read D15 to D8 Valid D7 to D0 High impedance Write High Notes 1 n 0 to 7 2 When RDNn 0 Figure 6 10 Bus Timing for 8 Bit 2 State Access Space ...

Page 189: ...access space is accessed the upper half D15 to D8 of the data bus is used The 5 pin is always fixed high Wait states can be inserted Bus cycle T1 T2 Address bus ø D15 to D8 Valid D7 to D0 Invalid Read D15 to D8 Valid D7 to D0 Write High T3 High impedance Notes 1 n 0 to 7 2 When RDNn 0 Figure 6 11 Bus Timing for 8 Bit 3 State Access Space ...

Page 190: ...e upper half D15 to D8 of the data bus is used for odd addresses and the lower half D7 to D0 for even addresses Wait states cannot be inserted Bus cycle T1 T2 Address bus ø D15 to D8 Valid D7 to D0 Invalid Read D15 to D8 Valid D7 to D0 Write High High impedance Notes 1 n 0 to 7 2 When RDNn 0 Figure 6 12 Bus Timing for 16 Bit 2 State Access Space Even Address Byte Access ...

Page 191: ...4 Bus cycle T1 T2 Address bus ø D15 to D8 Invalid D7 to D0 Valid Read D15 to D8 D7 to D0 Valid Write High High impedance Notes 1 n 0 to 7 2 When RDNn 0 Figure 6 13 Bus Timing for 16 Bit 2 State Access Space Odd Address Byte Access ...

Page 192: ...page 148 of 904 Bus cycle T1 T2 Address bus ø D15 to D8 Valid D7 to D0 Valid Read D15 to D8 Valid D7 to D0 Valid Write Notes 1 n 0 to 7 2 When RDNn 0 Figure 6 14 Bus Timing for 16 Bit 2 State Access Space Word Access ...

Page 193: ...upper half D15 to D8 of the data bus is used for the even address and the lower half D7 to D0 for the odd address Wait states can be inserted Bus cycle T1 T2 Address bus ø D15 to D8 Valid D7 to D0 Invalid Read D15 to D8 Valid D7 to D0 Write High T3 High impedance Notes 1 n 0 to 7 2 When RDNn 0 Figure 6 15 Bus Timing for 16 Bit 3 State Access Space Even Address Byte Access ...

Page 194: ...Bus cycle T1 T2 Address bus ø D15 to D8 Invalid D7 to D0 Valid Read D15 to D8 D7 to D0 Valid Write High T3 High impedance Notes 1 n 0 to 7 2 When RDNn 0 Figure 6 16 Bus Timing for 16 Bit 3 State Access Space Odd Address Byte Access ...

Page 195: ...te T3 Notes 1 n 0 to 7 2 When RDNn 0 Figure 6 17 Bus Timing for 16 Bit 3 State Access Space Word Access 6 5 4 Wait Control When accessing external space this LSI can extend the bus cycle by inserting one or more wait states Tw There are two ways of inserting wait states program wait insertion and pin wait insertion using the 7 pin ...

Page 196: ... wait is first inserted in accordance with the settings in WTCRA and WTCRB If the 7 pin is low at the falling edge of ø in the last T2 or Tw state another Tw state is inserted If the 7 pin is held low Tw states are inserted until it goes high This is useful when inserting seven or more Tw states or when changing the number of Tw states to be inserted for different external devices The WAITE bit se...

Page 197: ...tate Insertion Timing 6 5 5 Read Strobe 5 5 5 5 Timing The read strobe 5 timing can be changed for individual areas by setting bits RDN7 to RDN0 to 1 in RDNCR Figure 6 19 shows an example of the timing when the read strobe timing is changed in basic bus 3 state access space When the DMAC or EXDMAC is used in single address mode note that if the 5 timing is changed by setting RDNn to 1 the 5 timing...

Page 198: ...as 5 5 and 5 Settings can be made in the CSACR register to insert states in which only the 6 6 and address signals are asserted before and after a basic bus space access cycle Extension of the 6 assertion period can be set for individual areas With the 6 assertion extension period in write access the data setup and hold times are less stringent since the write data is output to the data bus Figure...

Page 199: ...with the upper 8 bits CSXH7 to CSXH0 in the CSACR register and for the Tt state with the lower 8 bits CSXT7 to CSXT0 6 6 DRAM Interface In this LSI external space areas 2 to 5 can be designated as DRAM space and DRAM interfacing performed The DRAM interface allows DRAM to be directly connected to this LSI A DRAM space of 2 4 or 8 Mbytes can be set by means of bits RMTS2 to RMTS0 in DRAMCR Burst op...

Page 200: ...hronous DRAM 1 0 Reserved setting prohibited 1 Continuous DRAM space Continuous DRAM space Continuous DRAM space Continuous DRAM space Note Reserved setting prohibited in the H8S 2378 series With continuous DRAM space 5 65 is valid The bus specifications bus width number of wait states etc for continuous DRAM space conform to the settings for area 2 6 6 2 Address Multiplexing With DRAM space the r...

Page 201: ...5 A14 A13 A12 A11 1 x x Reserved setting prohibited Column address 0 x x A23 to A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 1 x x Reserved setting prohibited x Don t care 6 6 3 Data Bus If a bit in ABWCR corresponding to an area designated as DRAM space is set to 1 that area is designated as 8 bit DRAM space if the bit is cleared to 0 the area is designated as 16 bit DRAM space In 16...

Page 202: ...e 66 5 66 Row address strobe 3 Output Row address strobe when area 3 is designated as DRAM space 67 5 67 Row address strobe 4 Output Row address strobe when area 4 is designated as DRAM space 68 5 68 Row address strobe 5 Output Row address strobe when area 5 is designated as DRAM space 8 6 8 6 Upper column address strobe Output Upper column address strobe for 16 bit DRAM space access or column add...

Page 203: ...rite Data bus Data bus Address bus Tr Tc1 Tc2 Row address High High Column address Note n 2 to 5 Figure 6 21 DRAM Basic Access Timing RAST 0 CAST 0 When DRAM space is accessed the 5 signal is output as the 2 signal for DRAM When connecting DRAM provided with an EDO page mode the 2 signal should be connected to the 2 pin of the DRAM Setting the OEE bit to 1 in DRAMCR enables the 2 signal for DRAM s...

Page 204: ...etting the CAST bit to 1 in DRAMCR Use the setting that gives the optimum specification values 6 pulse width etc according to the DRAM connected and the operating frequency of this LSI Figure 6 22 shows an example of the timing when a 3 state column address output cycle is selected Tp ø Read Write Data bus Data bus Address bus Tr Tc1 Tc2 Tc3 Row address Column address High High Note n 2 to 5 Figur...

Page 205: ... the fall of the 5 6 signal Use the optimum setting according to the DRAM connected and the operating frequency of this LSI Figure 6 23 shows an example of the timing when the 5 6 signal goes low from the beginning of the Tr state Tp ø Read Write Data bus Data bus Address bus Tr Tc1 Tc2 Row address Column address High High Note n 2 to 5 Figure 6 23 Example of Access Timing when 5 6 5 6 5 6 5 6 Sig...

Page 206: ...ycle in which the column address is output Use the setting that gives the optimum row address signal hold time relative to the falling edge of the 5 6 signal according to the DRAM connected and the operating frequency of this LSI Figure 6 24 shows an example of the timing when one Trw state is set Tp ø Read Write Data bus Data bus Address bus Tr Trw Tc1 Tc2 Row address Column address High High Not...

Page 207: ...1 and TPC0 in DRACCR Set the optimum number of Tp cycles according to the DRAM connected and the operating frequency of this LSI Figure 6 25 shows the timing when two Tp states are inserted The setting of bits TPC1 and TPC0 is also valid for Tp states in refresh cycles Tp1 ø Read Write Data bus Data bus Address bus Tp2 Tr Tc1 Tc2 Row address Column address High High Note n 2 to 5 Figure 6 25 Examp...

Page 208: ...t to 1 from 0 to 7 wait states can be inserted automatically between the Tc1 state and Tc2 state according to the settings in registers WTCRA and WTCRB Pin Wait Insertion When the WAITE bit in BCR is set to 1 and the ASTCR bit is set to 1 wait input by means of the 7 pin is enabled When DRAM space is accessed in this state a program wait Tw is first inserted If the 7 pin is low at the falling edge...

Page 209: ...Address bus ø Tr Tc1 Tw Tw Tc2 By pin Read Write Data bus Data bus Row address Column address High High Note Downward arrows indicate the timing of pin sampling n 2 to 5 Figure 6 26 Example of Wait State Insertion Timing 2 State Column Address Output ...

Page 210: ...dress bus ø Tr Tc1 Tw Tw Tc2 Tc3 By pin Read Write Data bus Data bus Row address Column address High High Note Downward arrows indicate the timing of pin sampling n 2 to 5 Figure 6 27 Example of Wait State Insertion Timing 3 State Column Address Output ...

Page 211: ... control signals needed for byte access Figure 6 28 shows the control timing for 2 CAS access and figure 6 29 shows an example of 2 CAS DRAM connection Tp High Z ø Upper data bus Lower data bus Address bus Tr Tc1 Tc2 Note n 2 to 5 Row address Column address Write data High High Figure 6 28 2 CAS Control Timing Upper Byte Write Access RAST 0 CAST 0 ...

Page 212: ...ach access a fast page mode is also provided which can be used when making consecutive accesses to the same row address This mode enables fast burst access of data by simply changing the column address after the row address has been output Burst access can be selected by setting the BE bit to 1 in DRAMCR Burst Access Fast Page Mode Figures 6 30 and 6 31 show the operation timing for burst access W...

Page 213: ...1 page 169 of 904 Tp ø Tr Tc1 Tc2 Tc1 Tc2 Read Write Data bus Data bus Address bus Note n 2 to 5 Row address Column address 1 Column address 2 High High Figure 6 30 Operation Timing in Fast Page Mode RAST 0 CAST 0 ...

Page 214: ...e In this case if the 5 6 signal is held low during the access to the other space burst operation can be resumed when the same row address in DRAM space is accessed again RAS Down Mode To select RAS down mode set both the RCDM bit and the BE bit to 1 in DRAMCR If access to DRAM space is interrupted and another space is accessed the 5 6 signal is held low during the access to the other space and bu...

Page 215: ...low To enter the all module clocks stopped mode with 5 6 high the RCDM bit must be cleared to 0 before executing the SLEEP instruction Normal space read DRAM space read Tp Tr Tc1 Tc2 T1 T2 DRAM space read Tc1 Tc2 Note n 2 to 5 ø Data bus Address bus Row address Column address 1 Column address 2 External address Figure 6 32 Example of Operation Timing in RAS Down Mode RAST 0 CAST 0 ...

Page 216: ...d Tp Tr Tc1 Tc2 Tc1 Tc2 DRAM space read T1 T2 Note n 2 to 5 ø Data bus Address bus Row address Column address 1 Column address 2 External address Figure 6 33 Example of Operation Timing in RAS Up Mode RAST 0 CAST 0 6 6 12 Refresh Control This LSI is provided with a DRAM refresh control function CAS before RAS CBR refreshing is used In addition self refreshing can be executed when the chip enters t...

Page 217: ...n RTCOR and bits RTCK2 to RTCK0 that will meet the refreshing interval specification for the DRAM used When bits RTCK2 to RTCK0 in REFCR are set RTCNT starts counting up RTCNT and RTCOR settings should therefore be completed before setting bits RTCK2 to RTCK0 RTCNT operation is shown in figure 6 34 compare match timing in figure 6 35 and CBR refresh timing in figure 6 36 When the CBRM bit in REFCR...

Page 218: ... the timing when bits RCW1 and RCW0 are set TRp ø TRrw TRr TRc1 TRc2 Figure 6 37 CBR Refresh Timing RCW1 0 RCW0 1 RLW1 0 RLW0 0 Depending on the DRAM used modification of the signal may not be permitted during the refresh period In this case the CBRM bit in REFCR should be set to 1 The bus controller will then insert refresh cycles in appropriate breaks between bus cycles Figure 6 38 shows an exam...

Page 219: ...t the RFSHE bit and SLFRF bit to 1 in REFCR When a SLEEP instruction is executed to enter software standby mode the 6 and 5 6 signals are output and DRAM enters self refresh mode as shown in figure 6 39 When software standby mode is exited the SLFRF bit is cleared to 0 and self refresh mode is exited automatically If a CBR refresh request occurs when making a transition to software standby mode CB...

Page 220: ...n bits TPCS2 to TPCS0 in REFCR to make the precharge time immediately after self refreshing from 1 to 7 states longer than the normal precharge time In this case too normal precharging is performed according to the setting of bits TPC1 and TPC0 in DRACCR and therefore a setting should be made to give the optimum post self refresh precharge time including this time Figure 6 40 shows an example of t...

Page 221: ...XMSTPCR H FFFF and a transition is made to the sleep state the all module clocks stopped mode is entered in which the bus controller and I O port clocks are also stopped As the bus controller clock is also stopped in this mode CBR refreshing is not executed If DRAM is connected externally and DRAM data is to be retained in sleep mode the ACSE bit must be cleared to 0 in MSTPCRH 6 6 13 DMAC and EXD...

Page 222: ...timing for the DRAM interface when DDS 1 or EDDS 1 Tp ø Read Write Data bus Data bus or Address bus Tr Tc1 Tc2 Note n 2 to 5 Row address Column address High High Figure 6 41 Example of Output Timing when DDS 1 or EDDS 1 RAST 0 CAST 0 When DDS 0 or EDDS 0 When DRAM space is accessed in DMAC or EXDMAC single address transfer mode full access normal access is always performed With the DRAM interface ...

Page 223: ... can be used when accessing DRAM space Figure 6 42 shows the or output timing for the DRAM interface when DDS 0 or EDDS 0 Tp ø Read Write Data bus Data bus or Address bus Tr Tc1 Tc2 Note n 2 to 5 Tc3 Row address Column address High High Figure 6 42 Example of Output Timing when DDS 0 or EDDS 0 RAST 0 CAST 1 ...

Page 224: ...S2 to RMTS0 and Synchronous DRAM Space RMTS2 RMTS1 RMTS0 Area 5 Area 4 Area 3 Area 2 0 0 1 Normal space Normal space Normal space DRAM space 1 0 Normal space Normal space DRAM space DRAM space 1 DRAM space DRAM space DRAM space DRAM space 1 0 Continuous synchronous DRAM space 0 1 Mode settings of synchronous DRAM 1 0 Reserved setting prohibited 1 Continuous DRAM space With continuous synchronous D...

Page 225: ... Address Pins MXC2 MXC1 MXC0 Shift Size A23 to A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Row address 0 x x Reserved setting prohibited 1 0 0 8 bits A23 to A16 A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 1 9 bits A23 to A16 A15 A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 1 0 10 bits A23 to A16 A15 A14 A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A...

Page 226: ...o D8 is enabled while in 16 bit continuous synchronous DRAM space both the upper and lower halves of the data bus D15 to D0 are enabled Access sizes and data alignment are the same as for the basic bus interface see section 6 5 1 Data Size and Data Alignment 6 7 4 Pins Used for Synchronous DRAM Interface Table 6 9 shows pins used for the synchronous DRAM interface and their functions To enable the...

Page 227: ...e 68 SDRAMφ Clock Output Clock only for synchronous DRAM 2 CKE Clock enable Output Clock enable signal when areas 2 to 5 are designated as continuous synchronous DRAM space 8 6 DQMU Upper data mask enable Output Upper data mask enable for 16 bit continuous synchronous DRAM space access data mask enable for 8 bit continuous synchronous DRAM space access 6 DQML Lower data mask enable Output Lower da...

Page 228: ...ectly connected to SDRAMφ of this LSI it is recommended to set the frequency multiplication factor of the PLL circuit to 1 or 2 Note SDRAMφ output timing is shown when the frequency multiplication factor of the PLL circuit is 1 or 2 SDRAMø Tcyc 1 4 Tcyc 90 ø Figure 6 43 Relationship between φ φ φ φ and SDRAMφ φ φ φ when PLL frequency multiplication factor is 1 or 2 6 7 6 Basic Timing The four stat...

Page 229: ...PALL ACTV READ NOP DQMU DQML Data bus Address bus Tr Tc1 Tc2 Row address Column address Column address Precharge sel Row address High Write CKE PALL ACTV NOP WRIT DQMU DQML Data bus High Figure 6 44 Basic Access Timing of Synchronous DRAM CAS Latency 1 ...

Page 230: ... timing when synchronous DRAM of CAS latency 3 is connected The initial value of W22 to W20 is H 7 Set the register according to the CAS latency of synchronous DRAM to be connected Table 6 10 Setting CAS Latency W22 W21 W20 Description CAS Latency Control Cycle Inserted 0 0 0 Connect synchronous DRAM of CAS latency 1 0 state 1 Connect synchronous DRAM of CAS latency 2 1 state 1 0 Connect synchrono...

Page 231: ... ACTV READ NOP DQMU DQML Data bus Address bus Tr Tc1 Tcl1 Tcl2 Tc2 Row address Column address Column address Precharge sel Row address High Write CKE PALL ACTV NOP NOP WRIT DQMU DQML Data bus High Figure 6 45 CAS Latency Control Timing SDWCD 0 CAS Latency 3 ...

Page 232: ...es Trw that output the NOP command can be inserted between the Tr cycle that outputs the ACTV command and the Tc1 cycle that outputs the column address by setting the RCD1 and RCD0 bits of DRACCR Use the optimum setting for the wait time according to the synchronous DRAM connected and the operating frequency of this LSI Figure 6 46 shows an example of the timing when the one Trw state is set ...

Page 233: ...ata bus Address bus Tr Trw Tc1 Tcl Tc2 Row address Column address Column address Precharge sel Row address High Write CKE PALL ACTV NOP NOP WRIT DQMU DQML Data bus High Figure 6 46 Example of Access Timing when Row Address Output Hold State is 1 State RCD1 0 RCD0 1 SDWCD 0 CAS Latency 2 ...

Page 234: ... to the next ACTV REF command cannot be satisfied from one to four Tp states can be selected by setting bits TPC1 and TPC0 in DRACCR Set the optimum number of Tp cycles according to the synchronous DRAM connected and the operating frequency of this LSI Figure 6 47 shows the timing when two Tp states are inserted ...

Page 235: ...DRAMø Read CKE PALL NOP ACTV READ NOP DQMU DQML Data bus Address bus Tp2 Tr Tc1 Tcl Tc2 Row address Column address Column address Precharge sel Row address High Write CKE PALL NOP NOP ACTV NOP WRIT DQMU DQML Data bus High Figure 6 47 Example of Timing with Two State Precharge Cycle TPC1 0 TPC0 1 SDWCD 0 CAS Latency 2 ...

Page 236: ...bling the CAS latency control cycle can reduce the write access cycle count as compared to synchronous DRAM read access Figure 6 48 shows the write access timing when the CAS latency control cycle is disabled Tp ø SDRAMø CKE PALL ACTV WRIT NOP DQMU DQML Data bus Address bus Tr Tc1 Tc2 Row address Column address Column address Precharge sel Row address High Figure 6 48 Example of Write Access Timin...

Page 237: ...49 and 6 50 show the control timing for DQM and figure 6 51 shows an example of connection of byte control by DQMU and DQML Tp ø SDRAMø CKE PALL ACTV NOP NOP WRIT DQMU DQML Lower data bus Upper data bus Address bus Tr Tc1 Tcl Tc2 Row address Column address Column address Precharge sel Row address High High High Z Figure 6 49 DQMU and DQML Control Timing Upper Byte Write Access SDWCD 0 CAS Latency ...

Page 238: ...PALL ACTV READ NOP DQMU DQML Lower data bus Upper data bus Address bus Tr Tc1 Tcl Tc2 Row address Column address Column address Precharge sel Row address High High High Z Figure 6 50 DQMU and DQML Control Timing Lower Byte Read Access CAS Latency 2 ...

Page 239: ...A3 A2 A2 A1 A1 DCTL I O PORT A0 D15 to D0 DQ15 to DQ0 CKE CKE Row address input A11 to A0 Column address input A7 to A0 Bank select address A13 A12 Figure 6 51 Example of DQMU and DQML Byte Control 6 7 12 Burst Operation With synchronous DRAM in addition to full access normal access in which data is accessed by outputting a row address for each access burst access is also provided which can be use...

Page 240: ... to issue the READ command Do not set the BE bit to 1 when synchronous DRAM of CAS latency 1 is connected Burst Access Operation Timing Figure 6 52 shows the operation timing for burst access When there are consecutive access cycles for continuous synchronous DRAM space the column address output cycles continue as long as the row address is the same for consecutive access cycles The row address us...

Page 241: ...ven when burst operation is selected it may happen that access to continuous synchronous DRAM space is not continuous but is interrupted by access to another space In this case if the row address active state is held during the access to the other space the read or write command can be issued without ACTV command generation similarly to DRAM RAS down mode To select RAS down mode set the BE bit to ...

Page 242: ...gram execution ensures the value software standby sleep etc auto refresh or self refresh must be set and the restrictions of the maximum active state time of each bank must be satisfied When refresh is not used programs must be developed so that the bank is not in the active state for more than the specified time Tp Address bus External address Column address Column address 2 External address Row ...

Page 243: ...rformed At the same time RTCNT is reset and starts counting up again from H 00 Refreshing is thus repeated at fixed intervals determined by RTCOR and bits RTCK2 to RTCK0 Set a value in RTCOR and bits RTCK2 to RTCK0 that will meet the refreshing interval specification for the synchronous DRAM used When bits RTCK2 to RTCK0 are set RTCNT starts counting up RTCNT and RTCOR settings should therefore be...

Page 244: ...R enables one to three wait states to be inserted after the TRp cycle that is set by the TPC1 and TPC0 bits of DRACCR Set the optimum number of waits according to the synchronous DRAM connected and the operating frequency of this LSI Figure 6 55 shows the timing when one wait state is inserted Since the setting of bits TPC1 and TPC0 of DRACCR is also valid in refresh cycles the command interval ca...

Page 245: ...W0 1 When the interval specification from the REF command to the ACTV cannot be satisfied setting the RLW1 and RLW0 bits of REFCR enables one to three wait states to be inserted in the refresh cycle Set the optimum number of waits according to the synchronous DRAM connected and the operating frequency of this LSI Figure 6 56 shows the timing when one wait state is inserted ...

Page 246: ... within the synchronous DRAM To select self refreshing set the RFSHE bit to 1 in REFCR When a SLEEP instruction is executed to enter software standby mode the SELF command is issued as shown in figure 6 57 When software standby mode is exited the SLFRF bit in REFCR is cleared to 0 and self refresh mode is exited automatically If an auto refresh request occurs when making a transition to software s...

Page 247: ...mand is specified A setting can be made in bits TPCS2 to TPCS0 in REFCR to make the precharge time after self refreshing from 1 to 7 states longer than the normal precharge time In this case too normal precharging is performed according to the setting of bits TPC1 and TPC0 in DRACCR and therefore a setting should be made to give the optimum post self refresh precharge time including this time Figu...

Page 248: ...ll module clocks stopped mode is entered in which the bus controller and I O port clocks are also stopped As the bus controller clock is also stopped in this mode auto refreshing is not executed If synchronous DRAM is connected to the external address space and DRAM data is to be retained in sleep mode the ACSE bit must be cleared to 0 in MSTPCR Software Standby When a transition is made to normal...

Page 249: ...suance time of the MRS command as the setting value of the mode register in the synchronous DRAM Mode of burst read burst write in the synchronous DRAM is not supported by this LSI For setting the mode register of the synchronous DRAM set the burst read single write with the burst length of 1 Figure 6 59 shows the setting timing of the mode in the synchronous DRAM Tp ø SDRAMø CKE PALL MRS NOP NOP ...

Page 250: ...s mode at the same time these bits select whether or not burst access is to be performed The establishment time for the read data can be extended in the clock suspend mode irrespective of the settings of the DDS and EDDS bits 1 Output Timing of or When DDS 1 or EDDS 1 Burst access is performed by determining the address only irrespective of the bus master With the synchronous DRAM interface the or...

Page 251: ...ALL ACTV READ NOP DQMU DQML Data bus Address bus Tr Tc1 Tcl Tc2 Row address Column address Column address Precharge sel Row address High Write CKE PALL ACTV NOP NOP WRIT DQMU DQML or Data bus High Figure 6 60 Example of Output Timing when DDS 1 or EDDS 1 ...

Page 252: ...ess normal access is always performed With the synchronous DRAM interface the or output goes low from the Tr state In modes other than DMAC or EXDMAC single address transfer mode burst access can be used when accessing continuous synchronous DRAM space Figure 6 61 shows the or output timing for connecting the synchronous DRAM interface when DDS 0 or EDDS 0 ...

Page 253: ...ALL ACTV READ NOP DQMU DQML Data bus Address bus Tr Tc1 Tcl Tc2 Row address Column address Column address Precharge sel Row address High Write CKE PALL ACTV NOP NOP WRIT DQMU DQML or Data bus High Figure 6 61 Example of Output Timing when DDS 0 or EDDS 0 ...

Page 254: ...its RDXC1 and RDXC0 in DRACCR Be sure to set the OEE bit to 1 in DRAMCR when the read data will be extended The extension of the read data is not in accordance with the bits DDS and EDDS Figure 6 62 shows the timing chart when the read data is extended by two cycles Address bus ø SDRAMø Column address Row address Row address Column address Data bus Tp Tr Tc2 Tcl Tsp2 Tsp1 Tc1 CKE PALL ACTV NOP REA...

Page 255: ...de independently for area 0 and area 1 In burst ROM space burst access covers only CPU read accesses 6 8 1 Basic Timing The number of access states in the initial cycle full access on the burst ROM interface is determined by the basic bus interface settings in ASTCR ABWCR WTCRA WTCRB and CSACRH When area 0 or area 1 is designated as burst ROM space the settings in RDNCR and CSACRL are ignored From...

Page 256: ... 0 09 01 page 212 of 904 T1 Upper address bus Lower address bus ø Data bus T2 T3 T1 T2 T1 Full access T2 Burst access Note n 1 and 0 Figure 6 63 Example of Burst ROM Access Timing ASTn 1 2 State Burst Cycle ...

Page 257: ...nsertion or pin wait insertion using the 7 pin can be used in the initial cycle full access on the burst ROM interface See section 6 5 5 Wait Control Wait states cannot be inserted in a burst cycle 6 8 3 Write Access When a write access to burst ROM space is executed burst access is interrupted at that point and the write access is executed in line with the basic bus interface settings Write acces...

Page 258: ...nt areas occur while the ICIS1 bit is set to 1 in BCR an idle cycle is inserted at the start of the second read cycle Figure 6 65 shows an example of the operation in this case In this example bus cycle A is a read cycle for ROM with a long output floating time and bus cycle B is a read cycle for SRAM each being located in a different area In a an idle cycle is not inserted and a collision occurs ...

Page 259: ...ycle B Long output floating time Data collision a No idle cycle insertion ICIS0 0 T1 Address bus ø Bus cycle A Data bus T2 T3 T1 Bus cycle B b Idle cycle insertion ICIS0 1 initial value T2 area A area B area A area B y Idle cycle Ti Figure 6 66 Example of Idle Cycle Operation Write after Read Read after Write If an external read occurs after an external write while the ICIS2 bit is set to 1 in BCR...

Page 260: ... Cycle Operation Read after Write Relationship between Chip Select 6 6 6 6 Signal and Read 5 5 5 5 Signal Depending on the system s load conditions the 5 signal may lag behind the 6 signal An example is shown in figure 6 68 In this case with the setting for no idle cycle insertion a there may be a period of overlap between the bus cycle A 5 signal and the bus cycle B 6 signal Setting idle cycle in...

Page 261: ...ead 5 5 5 5 Idle Cycle in Case of DRAM Space Access after Normal Space Access In a DRAM space access following a normal space access the settings of bits ICIS2 ICIS1 ICIS0 and IDLC in BCR are valid However in the case of consecutive reads in different areas for example if the second read is a full access to DRAM space only a Tp cycle is inserted and a Ti cycle is not The timing in this case is sho...

Page 262: ...ø External read Idle cycle Data bus Tr Tc1 Tc2 T1 DRAM space read DRAM space read T2 Tc2 T3 Ti Tc1 Figure 6 70 Example of Idle Cycle Operation in RAS Down Mode Consecutive Reads in Different Areas IDLC 0 RAST 0 CAST 0 Tp Address bus ø External read Idle cycle Data bus Tr Tc1 Tc2 T1 DRAM space write DRAM space read T2 Tc2 T3 Ti Tc1 Figure 6 71 Example of Idle Cycle Operation in RAS Down Mode Write ...

Page 263: ...interface is not supported T1 Address bus ø Column address Row address Row address Column address Data bus T2 T3 Tp Tr Tc2 External space read Synchronous DRAM space read Tcl Tc1 CKE PALL ACTV NOP NOP READ DQMU DQML Precharge sel Figure 6 72 Example of Synchronous DRAM Full Access after External Read CAS Latency 2 In burst access in RAS down mode the settings of bits ICIS2 ICIS1 ICIS0 and IDLC are...

Page 264: ...Idle cycle Data bus Tr Tc1 Tcl Tc2 T3 Tc1 Continuous synchronous DRAM space read External space read Continuous synchronous DRAM space read T2 Ti T1 CKE High High PALL ACTV READ NOP NOP READ DQMU DQML TCl Tc2 Precharge sel ø Row address Figure 6 73 Example of Idle Cycle Operation in RAS Down Mode Read in Different Area IDLC 0 CAS Latency 2 ...

Page 265: ...read Continuous synchronous DRAM space read T2 Ti Ti T1 CKE High High PALL ACTV READ NOP NOP READ DQMU DQML TCl Tc2 Precharge sel ø Row address Row address Column address External address External address Column address 1 Column address 2 Figure 6 74 Example of Idle Cycle Operation in RAS Down Mode Read in Different Area IDLC 1 CAS Latency 2 ...

Page 266: ... Idle Cycle in Case of Normal Space Access after DRAM Space Access Normal space access after DRAM space read access While the DRMI bit is cleared to 0 in DRACCR idle cycle insertion after DRAM space access is disabled Idle cycle insertion after DRAM space access can be enabled by setting the DRMI bit to 1 The conditions and number of states of the idle cycle to be inserted are in accordance with t...

Page 267: ...Ti Tc1 Figure 6 76 Example of Idle Cycle Operation after DRAM Access Consecutive Reads in Different Areas IDLC 0 RAST 0 CAST 0 Tp Address bus ø External address space write Idle cycle Data bus Tr Tc1 Tc2 T1 DRAM space read DRAM space read T2 Tc2 T3 Ti Tc1 Figure 6 77 Example of Idle Cycle Operation after DRAM Access Write after Read IDLC 0 RAST 0 CAST 0 ...

Page 268: ...0 CAST 0 Idle Cycle in Case of Normal Space Access After Continuous Synchronous DRAM Space Access Note In the H8S 2378 Series the synchronous DRAM interface is not supported Normal space access after a continuous synchronous DRAM space read access While the DRMI bit is cleared to 0 in DRACCR idle cycle insertion after continuous synchronous DRAM space read access is disabled Idle cycle insertion a...

Page 269: ...le Operation after Continuous Synchronous DRAM Space Read Access Read between Different Area IDLC 0 CAS Latency 2 Normal space access after a continuous synchronous DRAM space write access If a normal space read cycle occurs after a continuous synchronous DRAM space write access while the ICIS2 bit is set to 1 in BCR idle cycle is inserted at the start of the read cycle The number of states of the...

Page 270: ...QMU DQML TCl Tc2 Precharge sel ø External address External address Column address Column address 2 Row address Row address Column address Figure 6 80 Example of Idle Cycle Operation after Continuous Synchronous DRAM Space Write Access IDLC 0 ICIS1 0 SDWCD 1 CAS Latency 2 Table 6 11 shows whether there is an idle cycle insertion or not in the case of mixed accesses to normal space and DRAM space co...

Page 271: ...ce read DRAM continuous synchronous DRAM 1 space write 1 2 states inserted 0 Disabled 1 0 Disabled 1 0 1 state inserted Normal space read 1 2 states inserted 0 Disabled 1 0 Disabled 1 0 1 state inserted DRAM continuous synchronous DRAM 1 space read 1 2 states inserted 0 Disabled 1 0 Disabled 1 0 1 state inserted Normal space write 1 2 states inserted 0 Disabled 1 0 Disabled 1 0 1 state inserted DR...

Page 272: ...s bit is reserved and cannot be set Setting the DRMI bit in DRACCR to 1 enables an idle cycle to be inserted in the case of consecutive read and write operations in DRAM continuous synchronous DRAM space burst access Figures 6 81 and 6 82 show an example of the timing for idle cycle insertion in the case of consecutive read and write accesses to DRAM continuous synchronous DRAM space Tp Address bu...

Page 273: ...ynchronous DRAM space read Tc2 Ti Tc1 CKE High PALL ACTV READ NOP WRIT DQMU DQML Precharge sel ø External address Column address Row address Column address Figure 6 82 Example of Timing for Idle Cycle Insertion in Case of Consecutive Read and Write Accesses to Continuous Synchronous DRAM Space in RAS Down Mode SDWCD 1 CAS Latency 2 ...

Page 274: ...te data buffer function enables external writes and DMA single address mode transfers to be executed in parallel with internal accesses The write data buffer function is made available by setting the WDBE bit to 1 in BCR Figure 6 83 shows an example of the timing when the write data buffer function is used When this function is used if an external address space write or DMA single address mode tra...

Page 275: ...s If any of the following requests are issued in the external bus released state the 5 42 signal can be driven low to output a bus request externally When an internal bus master wants to perform an external access When a refresh request is generated When a SLEEP instruction is executed to place the chip in software standby mode or all module clocks stopped mode 6 11 1 Operation In externally expan...

Page 276: ... is canceled If the BREQOE bit is set to 1 in BCR the 5 42 pin can be driven low when any of the following requests are issued to request cancellation of the bus request externally When an internal bus master wants to perform an external access When a refresh request is generated When a SLEEP instruction is executed to place the chip in software standby mode or all module clocks stopped mode When ...

Page 277: ...n states in the external bus released state Table 6 13 Pin States in Bus Released State Pins Pin State A23 to A0 High impedance D15 to D0 High impedance 6Q n 7 to 0 High impedance 8 6 6 High impedance 6 High impedance 5 High impedance 2 High impedance 5 5 High impedance Q n 1 0 High Q n 3 to 0 High ...

Page 278: ...f external space access cycle At least one state from sampling of signal 3 signal is driven low releasing bus to external bus master 4 signal state is also sampled in external bus released state 5 High level of signal is sampled 6 signal is driven high ending external bus release cycle 7 When there is external access or refresh request of internal bus master during external bus release while BREQO...

Page 279: ...ow releasing bus to external bus master 5 BREQ signal state is also sampled in external bus released state 6 High level of BREQ signal is sampled 7 BACK signal is driven high ending external bus release cycle 8 When there is external access or refresh request of internal bus master during external bus release while the BREQOE bit is set to 1 BREQO signal goes low 9 BREQO signal goes high 1 5 state...

Page 280: ...bus until that signal is canceled The order of priority of the bus masters is as follows High EXDMAC DMAC DTC CPU Low An internal bus access by internal bus masters except the EXDMAC and external bus release a refresh when the CBRM bit is 0 and an external bus access by the EXDMAC can be executed in parallel If an external bus release request a refresh request and an external access by an internal...

Page 281: ...or a register information write 3 states DMAC The DMAC sends the bus arbiter a request for the bus when an activation request is generated In the case of an external request in short address mode or normal mode and in cycle steal mode the DMAC releases the bus after a single transfer In block transfer mode it releases the bus after transfer of one block and in burst mode after completion of the tr...

Page 282: ...MSTPCR must be cleared to 0 Conversely if a SLEEP instruction to place the chip in all module clocks stopped mode is executed in the external bus released state the transition to all module clocks stopped mode is deferred and performed until after the bus is recovered 6 14 2 External Bus Release Function and Software Standby In this LSI internal bus master operation does not stop even while the bu...

Page 283: ...t change the DCTL pin during operation Connection Clock Be sure to set the clock to be connected to the synchronous DRAM to SDRAMφ 7 7 7 7 Pin In the continuous synchronous DRAM space insertion of the wait state by the 7 pin is disabled regardless of the setting of the WAITE bit in BCR Bank Control This LSI cannot carry out the bank control of the synchronous DRAM All banks are selected Burst Acce...

Page 284: ...Rev 1 0 09 01 page 240 of 904 ...

Page 285: ...ress mode transfer can be performed in one bus cycle Choice of sequential mode idle mode or repeat mode for dual address mode and single address mode Full address mode Maximum of 2 channels can be used Transfer source and transfer destination addresses as specified as 24 bits Choice of normal mode or block transfer mode 16 Mbyte address space can be specified directly Byte or word can be set as th...

Page 286: ...DMATCR DMABCR Data buffer Internal data bus MAR_0AH IOAR_0A ETCR_0A MAR_0BH IOAR_0B ETCR_0B MAR_1AH IOAR_1A ETCR_1A MAR_1BH MAR_0AL MAR_0BL MAR_1AL MAR_1BL IOAR_1B ETCR_1B Legend DMAWER DMA write enable register DMATCR DMA terminal control register DMABCR DMA band control register for all channels DMACR DMA control register MAR Memory address register IOAR I O address register ETCR Execute transfe...

Page 287: ...Channel 1 transfer end 7 3 Register Descriptions Memory address register_0AH MAR_0AH Memory address register_0AL MAR_0AL I O address register_0A IOAR_0A Transfer count register_0A ECTR_0A Memory address register_0BH MAR_0BH Memory address register_0BL MAR_0BL I O address register_0B IOAR_0B Transfer count register_0B ECTR_0B Memory address register_1AH MAR_1AH Memory address register_1AL MAR_1AL I...

Page 288: ...ansfer destination transfer source address Specifies number of transfers Specifies transfer size mode activation source IOAR_0A ETCR_0A DMACR_0A Channel 0B MAR_0BH MAR_0AL MAR_0BL IOAR_0B ETCR_0B DMACR_0B 1 Full address mode specified channels 0A and 0B operate in combination as channel 0 Channel 0 MAR_0AH Specifies transfer source address Specifies transfer destination address Not used Not used S...

Page 289: ...ress transfer source address or destination address transfer destination address The upper 8 bits of the transfer address are automatically set to H FF The DMA has four IOAR registers IOAR_0A in channel 0 channel 0A IOAR_0B in channel 0 channel 0B IOAR_1A in channel 1 channel 1A and IOAR_1B in channel 1 channel 1B Whether IOAR functions as the source address register or as the destination address ...

Page 290: ...formed repeatedly until the DTE bit is cleared by the user Full Address Mode The function of ETCR in normal mode differs from that in block transfer mode In normal mode ETCRA functions as a 16 bit transfer counter ETCRA is decremented by 1 each time a data transfer is performed and transfer ends when the count reaches H 0000 ETCRB is not used in normal mode In block transfer mode ETCRAL functions ...

Page 291: ...r mode Short Address Mode DMACR_0A DMACR_0B DMACR_1A and DMARC_1B Bit Bit Name Initial Value R W Description 7 DTSZ 0 R W Data Transfer Size Selects the size of data to be transferred at one time 0 Byte size transfer 1 Word size transfer 6 DTID 0 R W Data Transfer Increment Decrement Selects incrementing or decrementing of MAR after every data transfer in sequential mode or repeat mode In idle mod...

Page 292: ...he SAE bit in DMABCR to specify the data transfer direction source or destination The function of this bit is therefore different in dual address mode and single address mode When SAE 0 0 Transfer with MAR as source address and IOAR as destination address 1 Transfer with IOAR as source address and MAR as destination address When SAE 1 0 Transfer with MAR as source address and pin as write strobe 1...

Page 293: ...ransmission complete interrupt 0111 Activated by SCI channel 1 reception complete interrupt 1000 Activated by TPU channel 0 compare match input capture A interrupt 1001 Activated by TPU channel 1 compare match input capture A interrupt 1010 Activated by TPU channel 2 compare match input capture A interrupt 1011 Activated by TPU channel 3 compare match input capture A interrupt 1100 Activated by TP...

Page 294: ...eption complete interrupt 1000 Activated by TPU channel 0 compare match input capture A interrupt 1001 Activated by TPU channel 1 compare match input capture A interrupt 1010 Activated by TPU channel 2 compare match input capture A interrupt 1011 Activated by TPU channel 3 compare match input capture A interrupt 1100 Activated by TPU channel 4 compare match input capture A interrupt 1101 Activated...

Page 295: ...fixed 01 MARA is incremented after a data transfer When DTSZ 0 MARA is incremented by 1 When DTSZ 1 MARA is incremented by 2 10 MARA is fixed 11 MARA is decremented after a data transfer When DTSZ 0 MARA is decremented by 1 When DTSZ 1 MARA is decremented by 2 12 11 BLKDIR BLKE 0 0 R W R W Block Direction Block Enable These bits specify whether normal mode or block transfer mode is to be used for ...

Page 296: ...ster MARB is to be incremented decremented or left unchanged when data transfer is performed 00 MARB is fixed 01 MARB is incremented after a data transfer When DTSZ 0 MARB is incremented by 1 When DTSZ 1 MARB is incremented by 2 10 MARB is fixed 11 MARB is decremented after a data transfer When DTSZ 0 MARB is decremented by 1 When DTSZ 1 MARB is decremented by 2 4 0 R W Reserved These bits can be ...

Page 297: ...vated by SCI channel 0 transmission complete interrupt 0101 Activated by SCI channel 0 reception complete interrupt 0110 Activated by SCI channel 1 transmission complete interrupt 0111 Activated by SCI channel 1 reception complete interrupt 1000 Activated by TPU channel 0 compare match input capture A interrupt 1001 Activated by TPU channel 1 compare match input capture A interrupt 1010 Activated ...

Page 298: ...MABCRH Bit Bit Name Initial Value R W Description 15 FAE1 0 R W Full Address Enable 1 Specifies whether channel 1 is to be used in short address mode or full address mode In short address mode channels 1A and 1B can be used as independent channels 0 Short address mode 1 Full address mode 14 FAE0 0 R W Full Address Enable 0 Specifies whether channel 0 is to be used in short address mode or full add...

Page 299: ...ng when DMA transfer is performed for the internal interrupt source selected by the DTF3 to DTF0 bits in DMACR It the DTA bit is set to 1 when DTE 1 the internal interrupt source is cleared automatically by DMA transfer When DTE 1 and DTA 1 the internal interrupt source does not issue an interrupt request to the CPU or DTC If the DTA bit is cleared to 0 when DTE 1 the internal interrupt source is ...

Page 300: ... enabled and the DMAC ignores the activation source selected by the DTF3 to DTF0 bits in DMACR When DTE 1 data transfer is enabled and the DMAC waits for a request by the activation source selected by the DTF3 to DTF0 bits in DMACR When a request is issued by the activation source DMA transfer is executed Clearing conditions When initialization is performed When the specified number of transfers h...

Page 301: ...ese bits enable or disable an interrupt to the CPU or DTC when transfer ends If the DTIE bit is set to 1 when DTE 0 the DMAC regards this as indicating the end of a transfer and issues a transfer end interrupt request to the CPU or DTC A transfer end interrupt can be canceled either by clearing the DTIE bit to 0 in the interrupt handling routine or by performing processing to continue transfer by ...

Page 302: ...ode In full address mode channels 1A and 1B are used together as channel 1 0 Short address mode 1 Full address mode 14 FAE0 0 R W Full Address Enable 0 Specifies whether channel 0 is to be used in short address mode or full address mode In full address mode channels 0A and 0B are used together as channel 0 0 Short address mode 1 Full address mode 13 12 0 0 R W R W Reserved These bits can be read f...

Page 303: ...d DTA1 1 the internal interrupt source does not issue an interrupt request to the CPU or DTC It the DTA1 bit is cleared to 0 when DTE1 1 the internal interrupt source is not cleared when a transfer is performed and can issue an interrupt request to the CPU or DTC in parallel In this case the interrupt source should be cleared by the CPU or DTC transfer When DTE1 0 the internal interrupt source iss...

Page 304: ...d DTA0 1 the internal interrupt source does not issue an interrupt request to the CPU or DTC It the DTA0 bit is cleared to 0 when DTE0 1 the internal interrupt source is not cleared when a transfer is performed and can issue an interrupt request to the CPU or DTC in parallel In this case the interrupt source should be cleared by the CPU or DTC transfer When DTE0 0 the internal interrupt source iss...

Page 305: ...e of a burst mode transfer when an NMI interrupt is generated the DTME1 bit is cleared the transfer is interrupted and bus mastership passes to the CPU When the DTME1 bit is subsequently set to 1 again the interrupted transfer is resumed In block transfer mode however the DTME1 bit is not cleared by an NMI interrupt and transfer is not interrupted Clearing conditions When initialization is perform...

Page 306: ... DTIE1 bit is set to 1 when DTE1 0 the DMAC regards this as indicating the end of a transfer and issues a transfer end interrupt request to the CPU When DTE1 1 and DTME1 1 data transfer is enabled and the DMAC waits for a request by the activation source When a request is issued by the activation source DMA transfer is executed Clearing conditions When initialization is performed When the specifie...

Page 307: ... a burst mode transfer when an NMI interrupt is generated the DTME0 bit is cleared the transfer is interrupted and bus mastership passes to the CPU When the DTME0 bit is subsequently set to 1 again the interrupted transfer is resumed In block transfer mode however the DTME0 bit is not cleared by an NMI interrupt and transfer is not interrupted Clearing conditions When initialization is performed W...

Page 308: ...ce When a request is issued by the activation source DMA transfer is executed Clearing conditions When initialization is performed When the specified number of transfers have been completed When 0 is written to the DTE0 bit to forcibly suspend the transfer or for a similar reason Setting condition When 1 is written to the DTE0 bit after reading DTE0 0 3 DTIE1B 0 R W Data Transfer Interrupt Enable ...

Page 309: ...on channel 1 is interrupted If the DTIE0B bit is set to 1 when DTME0 0 the DMAC regards this as indicating a break in the transfer and issues a transfer break interrupt request to the CPU or DTC A transfer break interrupt can be canceled either by clearing the DTIE0B bit to 0 in the interrupt handling routine or by performing processing to continue transfer by setting the DTME0 bit to 1 0 DTIE0A 0...

Page 310: ... are disabled 1 Writes are enabled 2 WE1A 0 R W Write Enable 1A Enables or disables writes to all bits in DMACR1A and bits 10 6 and 2 in DMABCR 0 Writes are disabled 1 Writes are enabled 1 WE0B 0 R W Write Enable 0B Enables or disables writes to all bits in DMACR0B bits 9 5 and 1 in DMABCR and bit 4 in DMATCR 0 Writes are disabled 1 Writes are enabled 0 WE0A 0 R W Write Enable 0A Enables or disabl...

Page 311: ...C to bits 15 to 12 FAE and SAE in DMABCR are invalid regardless of the DMAWER settings These bits should be changed if necessary by CPU processing In writes by the DTC to bits 7 to 4 DTE in DMABCR 1 can be written without first reading 0 To reactivate a channel set to full address mode write 1 to both Write Enable A and Write Enable B for the channel to be reactivated MAR IOAR and ETCR can always ...

Page 312: ...it Name Initial Value R W Description 7 6 0 0 Reserved These bits are always read as 0 and cannot be modified 5 TEE1 0 R W Transfer End Enable 1 Enables or disables transfer end pin 1 7 1 4 output 0 7 1 4 pin output disabled 1 7 1 4 pin output enabled 4 TEE0 0 R W Transfer End Enable 0 Enables or disables transfer end pin 0 7 1 3 output 0 7 1 3 pin output disabled 1 7 1 3 pin output enabled 3 to 0...

Page 313: ...X TXI1 X RXI1 X TGI0A X TGI1A X TGI2A X TGI3A X TGI4A X Internal interrupts TGI5A X 5 4 pin falling edge input X External requests 5 4 pin low level input X Auto request X X X Legend Can be specified X Cannot be specified 7 4 1 Activation by Internal Interrupt Request An interrupt request selected as a DMAC activation source can also simultaneously generate an interrupt request for the CPU or DTC ...

Page 314: ...tion source the relevant port should be set to input mode in advance Level sensing or edge sensing can be used for external requests External request operation in normal mode of short address mode or full address mode is described below When edge sensing is selected a byte or word is transferred each time a high to low transition is detected on the 5 4 pin The next data transfer may not be perform...

Page 315: ... a single transfer request Memory address fixed Number of transfers 1 to 65 536 3 Repeat mode 1 byte or 1 word transfer for a single transfer request Memory address incremented or decremented by 1 or 2 Continues transfer after sending number of transfers 1 to 256 and restoring the initial value TPU channel 0 to 5 compare match input capture A interrupt SCI transmission complete interrupt SCI recep...

Page 316: ...cle steal transfer can be selected Auto request Full address mode 2 External request 1 byte or 1 word transfer for a single transfer request Number of transfers 1 to 65 536 External request Block transfer mode Transfer of 1 block size selected for a single transfer request Number of transfers 1 to 65 536 Source or destination can be selected as block area Block size 1 to 256 bytes or word TPU chan...

Page 317: ...nitial Setting Operation 23 0 MAR Source address register Destination address register Start address of transfer destination or transfer source Incremented decremented every transfer 23 0 IOAR 15 H FF Destination address register Source address register Start address of transfer source or transfer destination Fixed 0 15 ETCR Transfer counter Number of transfers Decremented every transfer transfer ...

Page 318: ...when its value reaches H 0000 the DTE bit is cleared and data transfer ends If the DTIE bit is set to 1 at this time an interrupt request is sent to the CPU or DTC The maximum number of transfers when H 0000 is set in ETCR is 65 536 Transfer requests activation sources consist of A D converter conversion end interrupts external requests SCI transmission complete and reception complete interrupts a...

Page 319: ...t Specify whether MAR is to be incremented or decremented with the DTID bit Clear the RPE bit to 0 to select sequential mode Specify the transfer direction with the DTDIR bit Select the activation source with bits DTF3 to DTF0 5 Read the DTE bit in DMABCRL as 0 6 Set each bit in DMABCRL Specify enabling or disabling of transfer end interrupts with the DTIE bit Set the DTE bit to 1 to enable transf...

Page 320: ...transfer IOAR specifies the lower 16 bits of the other address The upper 8 bits of IOAR have a value of H FF Figure 7 5 illustrates operation in idle mode Transfer IOAR 1 byte or word transfer performed in response to 1 transfer request MAR Figure 7 5 Operation in Idle Mode The number of transfers is specified as 16 bits in ETCR ETCR is decremented by 1 each time a transfer is executed and when it...

Page 321: ...fy whether MAR is to be incremented or decremented with the DTID bit Set the RPE bit to 1 Specify the transfer direction with the DTDIR bit Select the activation source with bits DTF3 to DTF0 5 Read the DTE bit in DMABCRL as 0 6 Set each bit in DMABCRL Set the DTIE bit to 1 Set the DTE bit to 1 to enable transfer Figure 7 6 Example of Idle Mode Setting Procedure 7 5 4 Repeat Mode Repeat mode can b...

Page 322: ...00 MAR specifies the start address of the transfer source or transfer destination as 24 bits MAR is incremented or decremented by 1 or 2 each time a byte or word is transferred IOAR specifies the lower 16 bits of the other address The upper 8 bits of IOAR have a value of H FF The number of transfers is specified as 8 bits by ETCRH and ETCRL The maximum number of transfers when H 00 is set in both ...

Page 323: ...performed in response to 1 transfer request Legend Address T L Address B L 1 DTID 2DTSZ N 1 Where L Value set in MAR N Value set in ETCR Figure 7 7 Operation in Repeat mode Transfer requests activation sources consist of A D converter conversion end interrupts external requests SCI transmission complete and reception complete interrupts and TPU channel 0 to 5 compare match input capture A interrup...

Page 324: ...ber of transfers in both ETCRH and ETCRL 4 Set each bit in DMACR Set the transfer data size with the DTSZ bit Specify whether MAR is to be incremented or decremented with the DTID bit Set the RPE bit to 1 Specify the transfer direction with the DTDIR bit Select the activation source with bits DTF3 to DTF0 5 Read the DTE bit in DMABCRL as 0 6 Set each bit in DMABCRL Clear the DTIE bit to 0 Set the ...

Page 325: ...n address register Start address of transfer destination or transfer source See sections 7 5 2 Sequential Mode 7 5 3 Idle Mode and 7 5 4 Repeat Mode pin Write strobe Read strobe Set automatically by SAE bit IOAR is invalid Strobe for external device 0 15 ETCR Transfer counter Number of transfers See sections 7 5 2 Sequential Mode 7 5 3 Idle Mode and 7 5 4 Repeat Mode MAR specifies the start addres...

Page 326: ... to 1 transfer request Legend Address T L Address B L 1 DTID 2DTSZ N 1 Where L Value set in MAR N Value set in ETCR Figure 7 9 Operation in Single Address Mode When Sequential Mode is Specified Figure 7 10 shows an example of the setting procedure for single address mode when sequential mode is specified ...

Page 327: ... DTSZ bit Specify whether MAR is to be incremented or decremented with the DTID bit Clear the RPE bit to 0 to select sequential mode Specify the transfer direction with the DTDIR bit Select the activation source with bits DTF3 to DTF0 5 Read the DTE bit in DMABCRL as 0 6 Set each bit in DMABCRL Specify enabling or disabling of transfer end interrupts with the DTIE bit Set the DTE bit to 1 to enabl...

Page 328: ...ber of transfers Decremented every transfer transfer ends when count reaches H 0000 MARA and MARB specify the start addresses of the transfer source and transfer destination respectively as 24 bits MAR can be incremented or decremented by 1 or 2 each time a byte or word is transferred or can be fixed Incrementing decrementing or holding a fixed value can be set separately for MARA and MARB The num...

Page 329: ...ransfer requests activation sources are external requests and auto requests With auto request the DMAC is only activated by register setting and the specified number of transfers are performed automatically With auto request cycle steal mode or burst mode can be selected In cycle steal mode the bus is released to another bus master each time a transfer is performed In burst mode the bus is held co...

Page 330: ... bits Clear the BLKE bit to 0 to select normal mode Specify whether MARB is to be incremented decremented or fixed with the DAID and DAIDE bits Select the activation source with bits DTF3 to DTF0 5 Read DTE 0 and DTME 0 in DMABCRL 6 Set each bit in DMABCRL Specify enabling or disabling of transfer end interrupts with the DTIE bit Set both the DTME bit and the DTE bit to 1 to enable transfer Figure...

Page 331: ...ize Block size Fixed Decremented every transfer ETCRH value copied when count reaches H 00 15 0 ETCRB Block transfer counter Number of block transfers Decremented every block transfer transfer ends when count reaches H 0000 MARA and MARB specify the start addresses of the transfer source and transfer destination respectively as 24 bits MAR can be incremented or decremented by 1 or 2 each time a by...

Page 332: ...sponse to one request Legend Address Address Address Address Where LA LB LA SAIDE 1 SAID 2DTSZ M N 1 LB DAIDE 1 DAID 2DTSZ N 1 Value set in MARA Value set in MARB Value set in ETCRB Value set in ETCRAH and ETCRAL TA TB BA BB LA LB N M Figure 7 13 Operation in Block Transfer Mode BLKDIR 0 Figure 7 14 illustrates operation in block transfer mode when MARA is designated as a block area ...

Page 333: ...IR 1 ETCRAL is decremented by 1 each time a byte or word transfer is performed In response to a single transfer request burst transfer is performed until the value in ETCRAL reaches H 00 ETCRAL is then loaded with the value in ETCRAH At this time the value in the MAR register for which a block designation has been given by the BLKDIR bit in DMACRA is restored in accordance with the DTSZ SAID DAID ...

Page 334: ...0 ETCRAL ETCRAH ETCRB ETCRB 1 ETCRB H 0000 Start DTE DTME 1 Read address specified by MARA MARA MARA SAIDE 1 SAID 2DTSZ Write to address specified by MARB MARB MARB DAIDE 1 DAID 2DTSZ MARB MARB DAIDE 1 DAID 2DTSZ ETCRAH MARA MARA SAIDE 1 SAID 2DTSZ ETCRAH No Yes No Yes No Yes No Yes Clear DTE bit to 0 to end transfer Figure 7 15 Operation Flow in Block Transfer Mode ...

Page 335: ...fer source address in MARA and the transfer destination address in MARB 3 Set the block size in both ETCRAH and ETCRAL Set the number of transfers in ETCRB 4 Set each bit in DMACRA and DMACRB Set the transfer data size with the DTSZ bit Specify whether MARA is to be incremented decremented or fixed with the SAID and SAIDE bits Set the BLKE bit to 1 to select block transfer mode Specify whether the...

Page 336: ...te operations As like CPU cycles DMA cycles conform to the bus controller settings The address is not output to the external address bus in an access to on chip memory or an internal I O register ø Address bus DMAC cycle 1 word transfer Source address Destination address CPU cycle CPU cycle T1 T2 T3 T1 T2 T3 T1 T2 Figure 7 17 Example of DMA Transfer Bus Timing 7 5 9 DMA Transfer Dual Address Mode ...

Page 337: ...s is released one or more bus cycles are executed by the CPU or DTC In the transfer end cycle the cycle in which the transfer counter reaches 0 a one state DMA dead cycle is inserted after the DMA write cycle In repeat mode when 7 1 output is enabled 7 1 output goes low in the transfer end cycle Full Address Mode Cycle Steal Mode Figure 7 19 shows a transfer example in which 7 1 output is enabled ...

Page 338: ...quest and after the transfer the bus is released While the bus is released one bus cycle is executed by the CPU or DTC In the transfer end cycle the cycle in which the transfer counter reaches 0 a one state DMA dead cycle is inserted after the DMA write cycle Full Address Mode Burst Mode Figure 7 20 shows a transfer example in which 7 1 output is enabled and word size full address mode transfer bu...

Page 339: ...MI interrupt is generated while a channel designated for burst transfer is in the transfer enabled state the DTME bit in DMABCRL is cleared and the channel is placed in the transfer disabled state If burst transfer has already been activated inside the DMAC the bus is released on completion of a one byte or one word transfer within the burst transfer and burst transfer is suspended If the last tra...

Page 340: ...he bus is released one or more bus cycles are executed by the CPU or DTC In the transfer end cycle of each block the cycle in which the transfer counter reaches 0 a one state DMA dead cycle is inserted after the DMA write cycle Even if an NMI interrupt is generated during data transfer block transfer operation is not affected until data transfer for one block has ended 5 4 5 4 5 4 5 4 Pin Falling ...

Page 341: ... is sampled on the rising edge of ø and the request is held Note In write data buffer mode bus breaks from 2 to 7 may be hidden and not visible Figure 7 22 Example of 5 4 5 4 5 4 5 4 Pin Falling Edge Activated Normal Mode Transfer 5 4 pin sampling is performed every cycle with the rising edge of the next ø cycle after the end of the DMABCR write cycle for setting the transfer enabled state as the ...

Page 342: ...d the request is held Note In write data buffer mode bus breaks from 2 to 7 may be hidden and not visible Figure 7 23 Example of 5 4 5 4 5 4 5 4 Pin Falling Edge Activated Block Transfer Mode Transfer 5 4 pin sampling is performed every cycle with the rising edge of the next ø cycle after the end of the DMABCR write cycle for setting the transfer enabled state as the starting point When the 5 4 pi...

Page 343: ...ompleted As in 1 the pin low level is sampled on the rising edge of ø and the request is held Note In write data buffer mode bus breaks from 2 to 7 may be hidden and not visible Figure 7 24 Example of 5 4 5 4 5 4 5 4 Pin Low Level Activated Normal Mode Transfer 5 4 pin sampling is performed every cycle with the rising edge of the next ø cycle after the end of the DMABCR write cycle for setting the...

Page 344: ...dge of ø and the request is held Note In write data buffer mode bus breaks from 2 to 7 may be hidden and not visible Figure 7 25 Example of 5 4 5 4 5 4 5 4 Pin Low Level Activated Block Transfer Mode Transfer 5 4 pin sampling is performed every cycle with the rising edge of the next ø cycle after the end of the DMABCR write cycle for setting the transfer enabled state as the starting point When th...

Page 345: ...led and word size single address mode transfer read is performed from external 8 bit 2 state access space to an external device DMA read ø Address bus DMA read DMA read DMA dead Bus release Bus release Bus release Bus release Last transfer cycle Figure 7 27 Example of Single Address Mode Word Read Transfer A byte or word transfer is performed for a single transfer request and after the transfer th...

Page 346: ... mode transfer write is performed from an external device to external 8 bit 2 state access space DMA write ø Address bus DMA dead Bus release DMA write DMA write DMA write Bus release Bus release Bus release Bus release Last transfer cycle Figure 7 28 Example of Single Address Mode Transfer Byte Write Figure 7 29 shows a transfer example in which 7 1 output is enabled and word size single address ...

Page 347: ...ter the transfer the bus is released While the bus is released one or more bus cycles are executed by the CPU or DTC In the transfer end cycle the cycle in which the transfer counter reaches 0 a one state DMA dead cycle is inserted after the DMA write cycle 5 4 5 4 5 4 5 4 Pin Falling Edge Activation Timing Set the DTA bit in DMABCRH to 1 for the channel for which the 5 4 pin is selected Figure 7 ...

Page 348: ...he request is held Note In write data buffer mode bus breaks from 2 to 7 may be hidden and not visible Figure 7 30 Example of 5 4 5 4 5 4 5 4 Pin Falling Edge Activated Single Address Mode Transfer 5 4 pin sampling is performed every cycle with the rising edge of the next ø cycle after the end of the DMABCR write cycle for setting the transfer enabled state as the starting point When the 5 4 pin l...

Page 349: ...cycle is started 4 7 Acceptance is resumed after the single cycle is completed As in 1 the pin low level is sampled on the rising edge of ø and the request is held Note In write data buffer mode bus breaks from 2 to 7 may be hidden and not visible Figure 7 31 Example of 5 4 5 4 5 4 5 4 Pin Low Level Activated Single Address Mode Transfer 5 4 pin sampling is performed every cycle with the rising ed...

Page 350: ...from the 7 1 pin if the bus cycle in which a low level is to be output from the 7 1 pin is an external bus cycle However a low level is not output from the 7 1 pin if the bus cycle in which a low level is to be output from the 7 1 pin is an internal bus cycle and an external write cycle is executed in parallel with this cycle Figure 7 32 shows an example of burst mode transfer from on chip RAM to ...

Page 351: ...B Table 7 11 summarizes the priority order for DMAC channels Table 7 11 DMAC Channel Priority Order Short Address Mode Full Address Mode Priority Channel 0A Channel 0 High Channel 0B Channel 1A Channel 1 Channel 1B Low If transfer requests are issued simultaneously for more than one channel or if a transfer request for another channel is issued during a transfer when the bus is released the DMAC s...

Page 352: ...al bus release cycle may arise In this case the bus controller will suspend the transfer and insert a refresh cycle EXDMAC cycle or external bus release cycle in accordance with the external bus priority order even if the DMAC is executing a burst transfer or block transfer An external access by the DTC or CPU which has a lower priority than the DMAC is not executed until the DMAC releases the ext...

Page 353: ...etting the DTME bit to 1 again Figure 7 35 shows the procedure for continuing transfer when it has been interrupted by an NMI interrupt on a channel designated for burst mode transfer Resumption of transfer on interrupted channel Set DTME bit to 1 Transfer continues 1 2 DTE 1 DTME 0 Transfer ends No Yes 1 2 Check that DTE 1 and DTME 0 in DMABCRL Write 1 to the DTME bit Figure 7 35 Example of Proce...

Page 354: ...MAC operation clear the DTIE bit to 0 at the same time Figure 7 36 Example of Procedure for Forcibly Terminating DMAC Operation 7 5 16 Clearing Full Address Mode Figure 7 37 shows the procedure for releasing and initializing a channel designated for full address mode After full address mode has been cleared the channel can be set to another transfer mode using the appropriate setting procedure ...

Page 355: ...urces The sources of interrupts generated by the DMAC are transfer end and transfer break Table 7 12 shows the interrupt sources and their priority order Table 7 12 Interrupt Sources and Priority Order Interrupt Interrupt Source Interrupt Name Short Address Mode Full Address Mode Priority Order DMTEND0A Interrupt due to end of transfer on channel 0A Interrupt due to end of transfer on channel 0 Hi...

Page 356: ... when the DTME bit is cleared to 0 while the DTIEB bit is set to 1 In both short address mode and full address mode DMABCR should be set so as to prevent the occurrence of a combination that constitutes a condition for interrupt generation during setting 7 7 Usage Notes 7 7 1 DMAC Register Access during Operation Except for forced termination of the DMAC the operating including transfer waiting st...

Page 357: ...r mode the update timing is the same as 1 The MAR operation is post incrementing decrementing of the DMA internal address value 3 2 2 1 1 DMA transfer cycle DMA read DMA read DMA write DMA write DMA dead DMA Internal address DMA control DMA register operation DMA last transfer cycle Transfer destination Transfer destination Transfer source Transfer source Idle Idle Idle Read Read Dead Write Write ...

Page 358: ...ontrols external accesses is changed during execution of an external access by means of the write data buffer function the external access may not be performed normally Registers that control external accesses should only be manipulated when external reads etc are used with DMAC operation disabled and the operation is not performed in parallel with external access Write data buffer function and DM...

Page 359: ...or the refresh cycle ø Internal address Internal read signal External address Internal write signal Not output DMA read External write by CPU etc DMA write Figure 7 41 Example in Which Low Level is Not Output at 7 1 7 1 7 1 7 1 Pin 7 7 5 Activation by Falling Edge on 5 4 5 4 5 4 5 4 Pin 5 4 pin falling edge detection is performed in synchronization with DMAC internal operations The operation is as...

Page 360: ... already been initiated when operation is forcibly terminated the transfer is executed but flag clearing is not performed for the selected internal interrupt even if the DTA bit is set to 1 An internal interrupt request following the end of transfer or a forcible termination should be handled by the CPU as necessary 7 7 8 Channel Re Setting To reactivate a number of channels when multiple channels...

Page 361: ...M 16 777 215 infinite free running Selection of dual address mode or single address mode Selection of cycle steal mode or burst mode as bus mode Selection of normal mode or block transfer mode as transfer mode Two kinds of transfer requests external request and auto request An interrupt request can be sent to the CPU at the end of the specified number of transfers Repeat area designation function ...

Page 362: ...l pins EDMDR EDACR EDTCR EDDAR EDSAR Processor Address buffer Data buffer Control logic Module data bus Legend EDSAR EXDMA source address register EDDAR EXDMA destination address register EDTCR EXDMA transfer count register EDMDR EXDMA mode control register EDACR EXDMA address control register Figure 8 1 Block Diagram of EXDMAC ...

Page 363: ...nal request EXDMA transfer acknowledge 3 6 Output Channel 3 single address transfer acknowledge EXDMA transfer end 3 7 1 6 Output Channel 3 transfer end 5 46 acceptance acknowledge 5 6 Output Notification to external device of channel 3 external request acceptance and start of transfer processing 8 3 Register Descriptions The EXDMAC has the following registers EXDMA source address register_2 EDSAR...

Page 364: ...e to EDSAR for a channel on which EXDMA transfer is in progress The initial values of EDSAR are undefined 8 3 2 EXDMA Destination Address Register EDDAR EDDAR is a 32 bit readable writable register that specifies the transfer destination address An address update function is provided that updates the register contents to the next transfer destination address each time transfer processing is perfor...

Page 365: ...it Transfer Counter These bits specify the number of transfers Setting H 000001 specifies one transfer Setting H 000000 means no specification for the number of transfers and the transfer counter function is halted In this case there is no transfer end interrupt by the transfer counter Setting H FFFFFF specifies the maximum number of transfers that is 16 777 215 During EXDMA transfer this counter ...

Page 366: ...imum block size that is 256 The register value always indicates the specified block size 15 to 0 Undefined R W 16 Bit Transfer Counter These bits specify the number of block transfers Setting H 0001 specifies one block transfer Setting H 0000 means no specification for the number of transfers and the transfer counter function is halted In this case there is no transfer end interrupt by the transfe...

Page 367: ...A operation in block transfer mode transfer processing is continued for the currently executing one block transfer and the bit is cleared on completion of the currently executing one block transfer If an external source that ends aborts transfer occurs this bit is automatically cleared to 0 and transfer is terminated Do not change the operating mode transfer method or other parameters while this b...

Page 368: ...n NMI interrupt during block transfer 13 EDRAKE 0 R W 5 Pin Output Enable Enables output from the 5 4 acknowledge transfer processing start 5 pin 0 5 pin output disabled 1 5 pin output enabled 12 ETENDE 0 R W 7 1 Pin Output Enable Enables output from the EXDMA transfer end 7 1 pin 0 7 1 pin output disabled 1 7 1 pin output enabled 11 EDREQS 0 R W 5 4 Select Specifies low level sensing or falling e...

Page 369: ...quests When this bit is set to 1 an interrupt is requested when the IRF bit is set to 1 The interrupt request is cleared by clearing this bit or the IRF bit to 0 0 Interrupt request is not generated 1 Interrupt request is generated 6 IRF 0 R W Interrupt Request Flag Flag indicating that an interrupt request has occurred and transfer has ended 0 No interrupt request Clearing conditions Writing 1 to...

Page 370: ...the data transfer direction in single address mode In dual address mode the specification by this bit is ignored 0 Transfer direction EDSAR external device with 1 Transfer direction External device with EDDAR 3 DTSIZE 0 R W Data Transmit Size Specifies the size of data to be transferred 0 Byte size 1 Word size 2 BGUP 0 R W Bus Give Up When this bit is set to 1 the bus can be transferred to an inte...

Page 371: ... Interrupt Enable When this bit is set to 1 in the event of source address repeat area overflow the IRF bit is set to 1 and the EDA bit cleared to 0 in EDMDR and transfer is terminated If the EDIE bit in EDMDR is 1 when the IRF bit in EDMDR is set to 1 an interrupt request is sent to the CPU When used together with block transfer mode a source address repeat interrupt is requested at the end of a ...

Page 372: ...at area in the case of address incrementing or the last address of the repeat area in the case of address decrementing If the SARIE bit is set to 1 an interrupt can be requested when repeat area overflow occurs 00000 Not designated as repeat area 00001 Lower 1 bit 2 byte area designated as repeat area 00010 Lower 2 bits 4 byte area designated as repeat area 00011 Lower 3 bits 8 byte area designate...

Page 373: ...ress repeat area overflow the IRF bit is set to 1 and the EDA bit cleared to 0 in EDMDR and transfer is terminated If the EDIE bit in EDMDR is 1 when the IRF bit in EDMDR is set to 1 an interrupt request is sent to the CPU When used together with block transfer mode a destination address repeat interrupt is requested at the end of a block size transfer If the EDA bit is set to 1 in EDMDR for the c...

Page 374: ...a in the case of address incrementing or the last address of the repeat area in the case of address decrementing If the DARIE bit is set to 1 an interrupt can be requested when repeat area overflow occurs 00000 Not designated as repeat area 00001 Lower 1 bit 2 byte area designated as repeat area 00010 Lower 2 bits 4 byte area designated as repeat area 00011 Lower 3 bits 8 byte area designated as r...

Page 375: ...es or words External request 1 to 65 535 or no specification Single address mode Direct data transfer to from external device using pin instead of source or destination address register Above transfer mode can be specified in addition to address register setting One transfer possible in one bus cycle Transfer mode variations are the same as in dual address mode EDSAR EDDAR The transfer mode can be...

Page 376: ...Mode In dual address mode both the transfer source and transfer destination are specified by registers in the EXDMAC and one transfer is executed in two bus cycles The transfer source address is set in the source address register EDSAR and the transfer destination address is set in the transfer destination address register EDDAR In a transfer operation the value in external memory specified by the...

Page 377: ...ernal device with DACK shown in figure 8 3 data is output to the data bus by the external device and written to external memory in the same bus cycle The transfer direction that is whether the external device with DACK is the transfer source or transfer destination can be specified with the SDIR bit in EDMDR Transfer is performed from the external memory EDSAR to the external device with DACK when...

Page 378: ...Rev 1 0 09 01 page 334 of 904 Microcomputer Data flow External address bus External data bus EXDMAC External memory External device with DACK Figure 8 3 Data Flow in Single Address Mode ...

Page 379: ...ry Address bus ø ø Data bus EXDMA cycle EDDAR Address to external memory space signal to external memory space Address bus Transfer from external memory to external device with DACK Transfer from external device with DACK to external memory Data bus Data output from external device with DACK Figure 8 4 Example of Timing in Single Address Mode ...

Page 380: ...ables a signal confirming transfer request acceptance to be output from the 5 K pin The 5 signal is output when acceptance and transfer processing has been started in response to a single external request The 5 signal enables the external device to determine the timing of 5 4 signal negation and makes it possible to provide handshaking between the transfer request source and the EXDMAC In external...

Page 381: ...AC acquires the bus it continues transferring data without releasing the bus until the transfer end condition is satisfied There is no burst mode in external request mode In burst mode once transfer is started it is not interrupted even if there is a transfer request from another channel with higher priority When the burst mode channel finishes its transfer it releases the bus in the next cycle in...

Page 382: ...transfer mode When the activation source is an external request either normal transfer mode or block transfer mode can be selected When the activation source is an auto request normal transfer mode is used Normal Transfer Mode In normal transfer mode transfer of one transfer unit is processed in response to one transfer request EDTCR functions as a 24 bit transfer counter The 7 1 signal is output ...

Page 383: ... transfer of a block transfer requests for other higher priority channels are held pending When transfer of one block is completed the bus is released in the next cycle When the BGUP bit is set to 1 in EDMDR the bus is released if a bus request is issued by another bus master during block transfer Address register values are updated in the same way as in normal mode There is no function for restor...

Page 384: ... to restore the address register value to the buffer start address each time the address register value is the last address in the buffer i e when ring buffer address overflow occurs but if the repeat area function is used the operation that restores the address register value to the buffer start address is performed automatically within the EXDMAC The repeat area function can be set independently...

Page 385: ...H 240004 H 240005 H 240006 H 240007 When lower 3 bits 8 byte area of EDSAR are designated as repeat area SARA4 to SARA0 3 Figure 8 9 Example of Repeat Area Function Operation Caution is required when the repeat area overflow interrupt function is used together with block transfer mode If transfer is always terminated when repeat area overflow occurs in block transfer mode the block size must be a ...

Page 386: ... updated values depend on various settings and the transfer status The following registers and bits are updated EDSAR EDDAR EDTCR and bits EDA BEF and IRF in EDMDR EXDMA Source Address Register EDSAR When the EDSAR address is accessed as the transfer source after the EDSAR value is output EDSAR is updated with the address to be accessed next Bits SAT1 and SAT0 in EDACR specify incrementing or decr...

Page 387: ... by address updating When EDDAR is read during a transfer operation a longword access must be used During a transfer operation EDDAR may be updated without regard to accesses from the CPU and the correct values may not be read if the upper and lower words are read separately In a longword access the EXDMAC buffers the EDDAR value to ensure that the correct value is output Do not write to EDDAR for...

Page 388: ...ed 23 0 0 Before update After update 23 0 1 to H FFFFFF EDTCR 1 23 0 0 to H FFFFFE EDTCR EDTCR in normal transfer mode EDTCR in block transfer mode Fixed Before update After update 23 15 0 16 1 to H FFFF Block size EDTCR 1 23 15 0 16 0 Block size 23 15 0 16 0 to H FFFE Block size 23 15 0 16 0 Block size Figure 8 11 EDTCR Update Operations in Normal Transfer Mode and Block Transfer Mode EDA Bit in ...

Page 389: ...EDA bit are prohibited to registers of a channel for which the EDA bit is set to 1 When changing register settings after a 0 write to the EDA bit it is necessary to confirm that the EDA bit has been cleared to 0 Figure 8 12 shows the procedure for changing register settings in an operating channel Read EDA bit Write 0 to EDA bit Change register settings EDA bit 0 1 2 3 4 1 Write 0 to the EDA bit i...

Page 390: ...ion 8 5 Interrupts 8 4 8 Channel Priority Order The priority order of the EXDMAC channels is channel 2 channel 3 Table 8 3 shows the EXDMAC channel priority order Table 8 3 EXDMAC Channel Priority Order Channel Priority Channel 2 High Channel 3 Low If transfer requests occur simultaneously for a number of channels the highest priority channel according to the priority order in table 8 3 is selecte...

Page 391: ...ds on the channel priority If the channel that made the transfer request is of higher priority than the channel currently performing transfer the channel that made the transfer request is selected If the channel that made the transfer request is of lower priority than the channel currently performing transfer that channel s transfer request is held pending and the currently transferring channel re...

Page 392: ...Channel 2 Channel 1 Channel 1 Channel 2 Channel 1 Bus Conditions 2 Channel 1 External request cycle steal mode low level activation Channel 2 Auto request cycle steal mode Channel 1 pin Channel 2 EDA bit Channel 2 Channel 2 Channel 0 Channel 2 Channel 0 Bus Conditions 3 Channel 0 Auto request cycle steal mode Channel 2 Auto request cycle steal mode Bus release Channel 0 EDA bit Channel 2 EDA bit F...

Page 393: ... DMA read DMA write DMA read DMA write DMA read DMA write Address bus Bus release Bus release Bus release Bus release Last transfer cycle ø Figure 8 15 Example of Normal Transfer Mode Cycle Steal Mode Transfer Normal Transfer Mode Burst Mode Figure 8 16 shows an example of transfer when 7 1 output is enabled and word size normal transfer mode burst mode is performed from external 16 bit 2 state ac...

Page 394: ...in burst transfer has been initiated within the EXDMAC transfer is executed to the end even if the EDA bit is cleared Block Transfer Mode Cycle Steal Mode Figure 8 17 shows an example of transfer when 7 1 output is enabled and word size block transfer mode cycle steal mode is performed from external 16 bit 2 state access space to external 16 bit 2 state access space One block is transferred in res...

Page 395: ... is sampled at rise of ø and request is held Transfer destination Request clearance period Request clearance period Minimum 3 cycles Minimum 3 cycles Figure 8 18 Example of Normal Mode Transfer Activated by 5 4 5 4 5 4 5 4 Pin Falling Edge 5 4 pin sampling is performed in each cycle starting at the next rise of ø after the end of the EDMDR write cycle for setting the transfer enabled state When a ...

Page 396: ...ld Read Request clearance period Request clearance period Minimum 3 cycles Figure 8 19 Example of Block Transfer Mode Transfer Activated by 5 4 5 4 5 4 5 4 Pin Falling Edge 5 4 pin sampling is performed in each cycle starting at the next rise of ø after the end of the EDMDR write cycle for setting the transfer enabled state When a low level is sampled at the 5 4 pin while acceptance via the 5 4 pi...

Page 397: ... and request is held Minimum 3 cycles Request Minimum 3 cycles Request clearance period Request clearance period Figure 8 20 Example of Normal Mode Transfer Activated by 5 4 5 4 5 4 5 4 Pin Low Level 5 4 pin sampling is performed in each cycle starting at the next rise of ø after the end of the EDMDR write cycle for setting the transfer enabled state When a low level is sampled at the 5 4 pin whil...

Page 398: ...t clearance period Request clearance period Figure 8 21 Example of Block Transfer Mode Transfer Activated by 5 4 5 4 5 4 5 4 Pin Low Level 5 4 pin sampling is performed in each cycle starting at the next rise of ø after the end of the EDMDR write cycle for setting the transfer enabled state When a low level is sampled at the 5 4 pin while acceptance via the 5 4 pin is possible the request is held ...

Page 399: ...e to an external device DMA read Address bus Bus release Bus release Bus release Last transfer cycle Bus release DMA read DMA read ø Figure 8 23 Example of Single Address Mode Word Read Transfer After one byte or word has been transferred in response to one transfer request the bus is released While the bus is released one or more CPU DMAC or DTC bus cycles are initiated Single Address Mode Write ...

Page 400: ... an external device to external 8 bit 2 state access space DMA write Address bus Bus release Bus release Bus release Last transfer cycle Bus release DMA write DMA write ø Figure 8 25 Example of Single Address Mode Word Write Transfer After one byte or word has been transferred in response to one transfer request the bus is released While the bus is released one or more CPU DMAC or DTC bus cycles a...

Page 401: ...quest Minimum 3 cycles Request Figure 8 26 Example of Single Address Mode Transfer Activated by 5 4 5 4 5 4 5 4 Pin Falling Edge 5 4 pin sampling is performed in each cycle starting at the next rise of ø after the end of the EDMDR write cycle for setting the transfer enabled state When a low level is sampled at the 5 4 pin while acceptance via the 5 4 pin is possible the request is held within the...

Page 402: ...is started 4 7 Acceptance is resumed after completion of single cycle As in 1 pin low level is sampled at rise of ø and request is held Figure 8 27 Example of Single Address Mode Transfer Activated by 5 4 5 4 5 4 5 4 Pin Low Level 5 4 pin sampling is performed in each cycle starting at the next rise of ø after the end of the EDMDR write cycle for setting the transfer enabled state When a low level...

Page 403: ... the transfer request by the original channel is held pending and transfer is performed on the higher priority channel from the next transfer Transfer on the original channel is resumed on completion of the higher priority channel transfer Figures 8 28 to 8 30 show operation timing examples for various conditions ø pin Bus cycle CPU operation EDA bit EXDMA read EDA 1 write 0 0 1 EXDMA write EXDMA ...

Page 404: ...l EXDMA cycle EXDMA single cycle EXDMA single cycle EXDMA single cycle Bus release Bus release Bus release Bus release Bus release Figure 8 30 Auto Request Cycle Steal Mode Normal Transfer Mode Contention with Another Channel Single Address Mode Auto Request Burst Mode Normal Transfer Mode When the EDA bit is set to 1 in EDMDR an EXDMA transfer cycle is started a minimum of three cycles later Once...

Page 405: ...peated Last transfer cycle CPU cycle CPU cycle CPU cycle Figure 8 31 Auto Request Burst Mode Normal Transfer Mode CPU Cycles Dual Address Mode BGUP 0 ø pin Bus cycle CPU operation EXDMA read EXDMA write EXDMA read EXDMA write EXDMA read EXDMA write External space External space External space External space 1 bus cycle 1 bus cycle CPU cycle CPU cycle CPU cycle CPU cycle Figure 8 32 Auto Request Bu...

Page 406: ...nel transfer request EXDMA single transfer cycle EXDMA single transfer cycle EXDMA single transfer cycle 1 cycle Last transfer cycle Other channel EXDMA cycle Bus release Bus release Bus release Figure 8 34 Auto Request Burst Mode Normal Transfer Mode Contention with Another Channel Single Address Mode External Request Cycle Steal Mode Normal Transfer Mode In external request mode an EXDMA transfe...

Page 407: ...nd falling edge sensing The same applies to transfer request acceptance and transfer start timing Figures 8 35 to 8 38 show operation timing examples for various conditions ø pin Bus cycle EDA bit Bus release Bus release Bus release EXDMA read EXDMA write EXDMA read EXDMA write 0 1 Last transfer cycle 3 cycles Figure 8 35 External Request Cycle Steal Mode Normal Transfer Mode No Contention Dual Ad...

Page 408: ...CPU Cycles Single Address Mode Low Level Sensing ø pin Bus cycle acceptance internal processing state Bus release Bus release Bus release Start of high level sensing Start of high level sensing Start of high level sensing EXDMA single transfer cycle EXDMA single transfer cycle EXDMA single transfer cycle Edge confirmation Start of transfer processing Edge confirmation Start of transfer processing ...

Page 409: ...Request Cycle Steal Mode Block Transfer Mode In block transfer mode transfer of one block is performed continuously in the same way as in burst mode The timing of the start of the next block transfer is the same as in normal transfer mode If a transfer request is generated for another channel an EXDMA cycle for the other channel is generated before the next block transfer The 5 4 pin sensing timin...

Page 410: ...ite EXDMA read EXDMA write EXDMA read EXDMA write EXDMA read EXDMA write 0 1 Last transfer in block 1 block size transfer period Last block Last transfer cycle 3 cycles Repeated Bus release Repeated Figure 8 39 External Request Cycle Steal Mode Block Transfer Mode No Contention Dual Address Mode Low Level Sensing BGUP 0 ...

Page 411: ...ock Last transfer cycle 3 cycles EXDMA single transfer cycle EXDMA single transfer cycle EXDMA single transfer cycle EXDMA single transfer cycle EXDMA single transfer cycle Repeated Repeated Bus release Figure 8 40 External Request Cycle Steal Mode Block Transfer Mode No Contention Single Address Mode Falling Edge Sensing BGUP 0 ...

Page 412: ...e transfer cycle EXDMA single transfer cycle EXDMA single transfer cycle EXDMA single transfer cycle External space External space External space External space External space CPU cycle CPU cycle CPU cycle CPU cycle CPU cycle CPU cycle External space Repeated Repeated Figure 8 41 External Request Cycle Steal Mode Block Transfer Mode CPU Cycles Single Address Mode Low Level Sensing BGUP 0 ...

Page 413: ...cle External space External space External space External space EXDMA read EXDMA write EXDMA read EXDMA read EXDMA write EXDMA read EXDMA write 1 bus cycle 1 bus cycle Last transfer in block External space External space External space External space Repeated Figure 8 42 External Request Cycle Steal Mode Block Transfer Mode CPU Cycles Dual Address Mode Low Level Sensing BGUP 1 ...

Page 414: ...xternal space External space External space External space External space External space 1 bus cycle 1 bus cycle Last transfer in block EXDMA transfer cycle EXDMA transfer cycle EXDMA transfer cycle EXDMA transfer cycle EXDMA transfer cycle EXDMA transfer cycle EXDMA transfer cycle Repeated Figure 8 43 External Request Cycle Steal Mode Block Transfer Mode CPU Cycles Single Address Mode Low Level S...

Page 415: ...d EXDMA write EXDMA read EXDMA write Last transfer in block Last transfer in block 1 block size transfer period 1 block size transfer period Other channel EXDMA cycle Bus release Bus release Repeated Repeated Figure 8 44 External Request Cycle Steal Mode Block Transfer Mode Contention with Another Channel Dual Address Mode Low Level Sensing ...

Page 416: ...flow interrupt is requested during a read cycle the following write cycle processing is still executed In block transfer mode if a repeat area overflow interrupt is requested during transfer of a block transfer continues to the end of the block Transfer end by means of a repeat area overflow interrupt occurs between block size transfers Transfer End by 0 Write to EDA Bit in EDMDR When 0 is written...

Page 417: ...an the EXDMAC external space accesses by internal bus masters are not executed until the EXDMAC releases the bus The EXDMAC releases the bus in the following cases 1 When DMA transfer is performed in cycle steal mode 2 When switching to a different channel 3 When transfer ends in burst transfer mode 4 When transfer of one block ends in block transfer mode 5 When burst transfer or block transfer is...

Page 418: ...ansfer counter s transfer end interrupt is enabled or disabled by means of the TCEIE bit in EDMDR the source address register repeat area overflow interrupt by means of the SARIE bit in EDACR and the destination address register repeat area overflow interrupt by means of the DARIE bit in EDACR When an interrupt source occurs while the corresponding interrupt enable bit is set to 1 the IRF bit in E...

Page 419: ...n etc interrupt masking is cleared 6 Write set values to the registers transfer counter address registers etc 7 Write 1 to the EDA bit in EDMDR to restart EXDMA operation End of transfer restart processing Write 1 to EDA bit Change register settings End of interrupt handling routine Clear IRF bit to 0 Transfer restart after end of interrupt handling routine Transfer end interrupt exception handlin...

Page 420: ...e changed if necessary before making the module stop transition ETENDE 1 in EDMDR 7 1 pin enable EDRAKE 1 in EDMDR 5 pin enable AMS 1 in EDMDR pin enable 8 6 3 5 4 5 4 5 4 5 4 Pin Falling Edge Activation Falling edge sensing on the 5 4 pin is performed in synchronization with EXDMAC internal operations as indicated below 1 Activation request standby state Waits for low level sensing on 5 4 pin the...

Page 421: ...ith the EDA bit in EDMDR enabling interrupt requests an interrupt will be requested since EDIE 1 and IRF 1 To prevent the occurrence of an erroneous interrupt request when transfer starts ensure that the IRF bit is cleared to 0 before the EDIE bit is set to 1 8 6 6 7 1 7 1 7 1 7 1 Pin and CBR Refresh Cycle If the last EXDMAC transfer cycle and a CBR refresh cycle occur simultaneously note that alt...

Page 422: ...Rev 1 0 09 01 page 378 of 904 ...

Page 423: ...bus connects the DTC to the on chip RAM 1 kbyte enabling 32 bit 1 state reading and writing of the DTC register information 9 1 Features Transfer possible over any number of channels Three transfer modes Normal repeat and block transfer modes available One activation source can trigger a number of data transfers chain transfer Direct specification of 16 Mbyte address space possible Activation by s...

Page 424: ...DTC vector register Figure 9 1 Block Diagram of DTC 9 2 Register Configuration DTC has the following registers DTC mode register A MRA DTC mode register B MRB DTC source address register SAR DTC destination address register DAR DTC transfer count register A CRA DTC transfer count register B CRB These six registers cannot be directly accessed from the CPU When activated the DTC reads a set of regis...

Page 425: ...sfer 0x DAR is fixed 10 DAR is incremented after a transfer by 1 when Sz 0 by 2 when Sz 1 11 DAR is decremented after a transfer by 1 when Sz 0 by 2 when Sz 1 3 2 MD1 MD0 Undefined Undefined DTC Mode These bits specify the DTC transfer mode 00 Normal mode 01 Repeat mode 10 Block transfer mode 11 Setting prohibited 1 DTS Undefined DTC Transfer Mode Select Specifies whether the source side or the de...

Page 426: ...n Transfer Select Specifies the chain transfer condition 0 Chain transfer every time 1 Chain transfer only when transfer counter 0 4 to 0 Undefined Reserved These bits have no effect on DTC operation and should always be written with 0 9 2 3 DTC Source Address Register SAR SAR is a 24 bit register that designates the source address of data to be transferred by the DTC For word size transfer specif...

Page 427: ...tivation interrupt sources The correspondence between interrupt sources and DTCE bits is shown in table 9 1 For DTCE bit setting use bit manipulation instructions such as BSET and BCLR for reading and writing If all interrupts are masked multiple activation sources can be set at one time only at the initial setting by writing data after executing a dummy read on the relevant register Bit Bit Name ...

Page 428: ...ress is expressed as H 0400 vector number 2 For example when DTVEC6 to DTVEC0 H 10 the vector address is H 0420 When the bit SWDTE is 0 these bits can be written 9 3 Activation Sources The DTC operates when activated by an interrupt or by a write to DTVECR by software An interrupt request can be directed to the CPU or DTC as designated by the corresponding DTCER bit At the end of a data transfer o...

Page 429: ...ers in that order from the start address of the register information In the case of chain transfer register information should be located in consecutive areas as shown in figure 9 3 and the register information start address should be located at the corresponding vector address to the activation source The DTC reads the start address of the register information from the vector address set for each...

Page 430: ... information Register information for second transfer in case of chain transfer Chain transfer Lower addresses Four bytes 0 1 2 3 SAR MRB DAR CRA CRB MRA SAR MRB DAR CRA CRB Figure 9 3 Correspondence between DTC Vector Address and Register Information Note Not available in this LSI ...

Page 431: ... H 042E DTCEA0 IRQ8 24 H 0430 DTCEB7 IRQ9 25 H 0432 DTCEB6 IRQ10 26 H 0434 DTCEB5 IRQ11 17 H 0436 DTCEB4 IRQ12 18 H 0438 DTCEB3 IRQ13 19 H 043A DTCEB2 IRQ14 30 H 043C DTCEB1 IRQ15 31 H 043E DTCEB0 A D ADI 38 H 044C DTCEC6 TPU_0 TGI0A 40 H 0450 DTCEC5 TGI0B 41 H 0452 DTCEC4 TGI0C 42 H 0454 DTCEC3 TGI0D 43 H 0456 DTCEC2 TPU_1 TGI1A 48 H 0460 DTCEC1 TGI1B 49 H 0462 DTCEC0 TPU_2 TGI2A 52 H 0468 DTCED7...

Page 432: ...CE bit 9 5 Operation The DTC stores register information in the on chip RAM When activated the DTC reads register information that is already stored in the on chip RAM and transfers data on the basis of that register information After the data transfer it writes updated register information back to the on chip RAM Pre storage of register information in the on chip RAM makes it possible to transfer...

Page 433: ...g the second and third transfers are omitted Start Read DTC vector Next transfer Read register information Data transfer Write register information Clear activation flag CHNE 1 End No No No No No Yes Yes Yes Yes Yes Transfer counter 0 or DISEL 1 Clear DTCER Interrupt exception handling CHNS 0 DISEL 1 Transfer counter 0 Figure 9 4 Flowchart of DTC Operation ...

Page 434: ...equest to CPU 1 1 1 Not 0 Ends at 1st transfer Interrupt request to CPU 9 5 1 Normal Mode In normal mode one operation transfers one byte or one word of data Table 9 3 lists the register function in normal mode From 1 to 65 536 transfers can be specified Once the specified number of transfers has ended a CPU interrupt can be requested Table 9 3 Register Function in Normal Mode Name Abbreviation Fu...

Page 435: ...address register specified as the repeat area is restored and transfer is repeated In repeat mode the transfer counter value does not reach H 00 and therefore CPU interrupts cannot be requested when DISEL 0 Table 9 4 Register Function in Repeat Mode Name Abbreviation Function DTC source address register SAR Designates source address DTC destination address register DAR Designates destination addre...

Page 436: ...e counter and the address register specified as the block area is restored The other address register is then incremented decremented or left fixed From 1 to 65 536 transfers can be specified Once the specified number of transfers has ended a CPU interrupt is requested Table 9 5 Register Function in Block Transfer Mode Name Abbreviation Function DTC source address register SAR Designates source ad...

Page 437: ...then reads the first register information at that start address The CHNE bit in MRB is checked after the end of data transfer if the value is 1 the next register information which is located consecutively is read and transfer is performed This operation is repeated until the end of data transfer of register information with CHNE 0 It is also possible by setting both the CHNE bit and CHNS bit to 1 ...

Page 438: ...ivation source is generated These interrupts to the CPU are subject to CPU mask level and interrupt controller priority level control In the case of activation by software a software activated data transfer end interrupt SWDTEND is generated When the DISEL bit is 1 and one data transfer has ended or the specified number of transfers has ended after data transfer ends the SWDTE bit is held at 1 and...

Page 439: ...est DTC request Address Vector read Read Write Read Write Data transfer Transfer information write Transfer information read Figure 9 10 DTC Operation Timing Example of Block Transfer Mode with Block Size of 2 φ DTC activation request DTC request Address Vector read Read Write Read Write Data transfer Data transfer Transfer information write Transfer information write Transfer information read Tra...

Page 440: ...cess states 1 1 2 2 2 3 2 3 Execution Vector read SI 1 4 6 2m 2 3 m status Register information read write SJ 1 Byte data read SK 1 1 2 2 2 3 m 2 3 m Word data read SK 1 1 4 2 4 6 2m 2 3 m Byte data write SL 1 1 2 2 2 3 m 2 3 m Word data write SL 1 1 4 2 4 6 2m 2 3 m Internal operation SM 1 The number of execution states is calculated from the formula below Note that Σ means the sum of all transfe...

Page 441: ...2 Set the start address of the register information in the DTC vector address 3 Check that the SWDTE bit is 0 4 Write 1 to SWDTE bit and the vector number to DTVECR 5 Check the vector number written to DTVECR 6 After the end of one data transfer if the DISEL bit is 0 and a CPU interrupt is not requested the SWDTE bit is cleared to 0 If the DTC is to continue transferring data set the SWDTE bit to ...

Page 442: ...tivation source and interrupt generation at the end of the specified number of transfers are restricted to the second half of the chain transfer transfer when CHNE 0 1 Perform settings for transfer to the PPG s NDR Set MRA to source address incrementing SM1 1 SM0 0 fixed destination address DM1 DM0 0 repeat mode MD1 0 MD0 1 and word size Sz 1 Set the source side as a repeat area DTS 1 Set MRB to c...

Page 443: ...r in a separate area in ROM etc For example if the input buffer comprises H 200000 to H 21FFFF prepare H 21 and H 20 3 For the second transfer set repeat mode with the source side as the repeat area for re setting the transfer destination address for the first data transfer Use the upper 8 bits of DAR in the first register information area as the transfer destination Set CHNE DISEL 0 If the above ...

Page 444: ...0 so the vector address is H 04C0 1 Set MRA to incrementing source address SM1 1 SM0 0 incrementing destination address DM1 1 DM0 0 block transfer mode MD1 1 MD0 0 and byte size Sz 0 The DTS bit can have any value Set MRB for one block transfer by one interrupt CHNE 0 Set the transfer source address H 1000 in SAR the destination address H 2000 in DAR and 128 H 8080 in CRA Set 1 H 0001 in CRB 2 Set...

Page 445: ...r Down Modes 9 8 2 On Chip RAM The MRA MRB SAR DAR CRA and CRB registers are all located in on chip RAM When the DTC is used the RAME bit in SYSCR must not be cleared to 0 9 8 3 DTCE Bit Setting For DTCE bit setting use bit manipulation instructions such as BSET and BCLR If all interrupts are disabled multiple activation sources can be set at one time only at the initial setting by writing data af...

Page 446: ... of 904 Therefore when the DTC is activated by an interrupt or activation source if a read write of the relevant register is not included in the last chained data transfer the interrupt or activation source will be retained ...

Page 447: ...register Ports A to E have a built in pull up MOS function and a pull up MOS control register PCR to control the on off state of MOS input pull up Ports 3 and A include an open drain control register ODR that controls the on off state of the output buffer PMOS Ports 1 to 3 5 P50 to P53 and 6 to 8 can drive a single TTL load and 30 pF capacitive load Ports A to H can drive a single TTL load and 50 ...

Page 448: ...t 2 General I O port also functioning as PPG outputs TPU I Os interrupt inputs and bus control I Os P27 PO7 TIOCB5 5448 P26 PO6 TIOCA5 5447 P25 PO5 TIOCB4 5446 P24 PO4 TIOCA4 5445 P23 PO3 TIOCD3 5444 P22 PO2 TIOCC3 5443 P21 PO1 TIOCB3 54 P20 PO0 TIOCA3 54 Schmitt triggered input P35 SCK1 SCL0 2 CKE P35 SCK1 SCL0 2 CKE P35 SCK1 SCL0 Port 3 General I O port also functioning as SCI I Os I 2 C I Os an...

Page 449: ...0 7 1 3 5443 P61 TMRI1 5 44 54 P60 TMRI0 5 43 54 Schmitt triggered input when used as IRQ input Port 8 General I O port also functioning as EXDMAC I Os and interrupt inputs P85 6 548 SCK3 P84 5 547 P83 7 1 6 546 RXD3 P82 7 1 5 545 P81 5 46 544 TXD3 P80 5 45 543 P85 6 548 SCK3 P84 5 547 P83 7 1 6 546 RXD3 P82 7 1 5 545 P81 5 46 544 TXD3 P80 5 45 543 P85 548 SCK3 P84 547 P83 546 RXD3 P82 545 P81 5 4...

Page 450: ...B General I O port also functioning as address outputs A15 A14 A13 A12 A11 A10 A9 A8 PB7 A15 PB6 A14 PB5 A13 PB4 A12 PB3 A11 PB2 A10 PB1 A9 PB0 A8 PB7 A15 PB6 A14 PB5 A13 PB4 A12 PB3 A11 PB2 A10 PB1 A9 PB0 A8 PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 Built in MOS input pull up Port C General I O port also functioning as address outputs A7 A6 A5 A4 A3 A2 A1 A0 PC7 A7 PC6 A6 PC5 A5 PC4 A4 PC3 A3 PC2 A2 PC1 A1...

Page 451: ...PF1 8 6 408 5447 PF1 5447 Port F General I O port also functioning as interrupt inputs and bus control I Os PF0 7 PF0 7 PF0 Only PF1 and PF2 are Schmitt triggered inputs when used as the IRQ input PG6 5 4 PG5 PG4 5 42 PG6 5 4 PG5 PG4 5 42 PG6 PG5 PG4 PG3 66 5 66 6 PG3 66 5 66 6 PG3 Port G General I O port also functioning as bus control I Os PG2 65 5 65 5 6 PG1 64 PG0 63 PG2 65 5 65 5 6 PG1 64 PG0...

Page 452: ... 6 P16DDR 0 W 5 P15DDR 0 W 4 P14DDR 0 W 3 P13DDR 0 W 2 P12DDR 0 W 1 P11DDR 0 W 0 P10DDR 0 W When a pin function is specified to a general purpose I O setting this bit to 1 makes the corresponding port 1 pin an output pin while clearing this bit to 0 makes the pin an input pin 10 1 2 Port 1 Data Register P1DR P1DR stores output data for the port 1 pins Bit Bit Name Initial Value R W Description 7 P...

Page 453: ...tion as the pins for PPG outputs TPU I Os and EXDMAC outputs The correspondence between the register specification and the pin functions is shown below P17 PO15 TIOCB2 TCLKD 5 6 The pin function is switched as shown below according to the combination of the TPU channel 2 settings by bits MD3 to MD0 in TMDR_2 bits IOB3 to IOB0 in TIOR_2 and bits CCLR1 and CCLR0 in TCR_2 bits TPSC2 to TPSC0 in TCR_0...

Page 454: ...0 B 0000 B000 and B 01xx and IOB3 1 2 TCLKD input when the setting for either TCR_0 or TCR_5 is TPSC2 to TPSC0 B 111 TCLKD input when channels 2 and 4 are set to phase counting mode TPU channel 2 settings 2 1 2 1 1 2 MD3 to MD0 B 0000 B 01xx B 001x B 0010 B 0011 IOA3 to IOA0 B 0000 B 0100 B 1xxx B 0001 to B 0011 B 0101 to B 0111 B xx00 Other than B xx00 CCLR1 CCLR0 Other than B 10 B 10 Output func...

Page 455: ... in EDMDR_2 and bit P16DDR Modes 1 2 4 5 6 7 EXPE 1 EDRAKE 0 1 TPU channel 2 settings 1 in table below 2 in table below P16DDR 0 1 1 NDER14 0 1 TIOCA2 output P16 input P16 output PO14 output 5 5 output Pin function TIOCA input 1 Mode 7 EXPE 0 EDRAKE TPU channel 2 settings 1 in table below 2 in table below P16DDR 0 1 1 NDER14 0 1 TIOCA2 output P16 input P16 output PO14 output Pin function TIOCA2 in...

Page 456: ... 0000 B 01xx B 001x B 0010 B 0011 IOA3 to IOA0 B 0000 B 0100 B 1xxx B 0001 to B 0011 B 0101 to B 0111 B xx00 Other than B xx00 CCLR1 CCLR0 Other than B 10 B 10 Output function Output compare output PWM 2 mode 1 output PWM mode 2 output x Don t care Note 2 TIOCB2 output disabled ...

Page 457: ...ut PO13 output TIOCB1 output TIOCB1 input 1 Pin function TCLKC input 2 Notes 1 TIOCB1 input when MD3 to MD0 B 0000 or B 01XX and IOB3 B 10xx 2 TCLKC input when the setting for either TCR_0 or TCR_2 is TPSC2 to TPSC0 B 110 or when the setting for either TCR_4 or TCR_5 is TPSC2 to TPSC0 B 101 TCLKC input when phase counting mode is set for channels 2 and 4 TPU channel 1 settings 2 1 2 2 1 2 MD3 to M...

Page 458: ...e below P14DDR 0 1 1 NDER12 0 1 P14 input P14 output PO12 output Pin function TIOCA1 output TIOCA1 input 1 Note 1 TIOCA1 input when MD3 to MD0 B 0000 B 000 and B 01xx and IOA3 B 10xx TPU channel 1 settings 2 1 2 1 1 2 MD3 to MD0 B 0000 B 01xx B 001x B 0010 B 0011 IOA3 to IOA0 B 0000 B 0100 B 1xxx B 0001 to B 0011 B 0101 to B 0111 B xx00 Other than B xx00 Other than B xx00 CCLR1 CCLR0 Other than B ...

Page 459: ...DDR 0 1 1 NDER11 0 1 P13 input P13 output PO11 output TIOCD0 output TIOCD0 input 1 Pin function TCLKB input 2 Notes 1 TIOCD0 input when MD3 to MD0 B 0000 and IOD3 B 10xx 2 TCLKB input when the setting for any of TCR_0 to TCR_2 is TPSC2 to TPSC0 B 101 TCLKB input when phase counting mode is set for channels 1 and 5 TPU channel 0 settings 2 1 2 2 1 2 MD3 to MD0 B 0000 B 0010 B 0011 IOD3 to IOD0 B 00...

Page 460: ...nput 1 Pin function TCLKA input 2 Notes 1 TIOCC0 input when MD3 to MD0 B 0000 and IOC3 to IOC0 B 10xx 2 TCLKA input when the setting for any of TCR_0 to TCR_5 is TPSC2 to TPSC0 B 100 TCLKA input when phase counting mode is set for channels 1 and 5 TPU channel 0 settings 2 1 2 1 1 2 MD3 to MD0 B 0000 B 001x B 0010 B 0011 IOC3 to IOC0 B 0000 B 0100 B 1xxx B 0001 to B 0011 B 0101 to B 0111 B xx00 Oth...

Page 461: ...ngs 1 in table below 2 in table below P11DDR 0 1 1 NDER9 0 1 P11 input P11 output PO9 output Pin function TIOCB0 output TIOCB0 input 1 Note 1 TIOCB0 input when MD3 to MD0 B 0000 and IOB3 to IOB0 B 10xx TPU channel 0 settings 2 1 2 2 1 2 MD3 to MD0 B 0000 B 0010 B 0011 IOB3 to IOB0 B 0000 B 0100 B 1xxx B 0001 to B 0011 B 0101 to B 0111 B xx00 Other than B xx00 CCLR2 CCLR0 Other than B 010 B 010 Out...

Page 462: ...in table below P10DDR 0 1 1 NDER8 0 1 P10 input P10 output PO8 output Pin function TIOCA0 output TIOCA0 input 1 Note 1 TIOCA0 input when MD3 to MD0 B 0000 and IOA3 to IOA0 B 10xx TPU channel 0 settings 2 1 2 1 1 2 MD3 to MD0 B 0000 B 001x B 0010 B 0011 IOA3 to IOA0 B 0000 B 0100 B 1xxx B 0001 to B 0011 B 0101 to B 0111 B xx00 Other than B xx00 Other than B xx00 CCLR2 CCLR0 Other than B 001 B 001 O...

Page 463: ...ue R W Description 7 P27DDR 0 W 6 P26DDR 0 W 5 P25DDR 0 W 4 P24DDR 0 W 3 P23DDR 0 W 2 P22DDR 0 W 1 P21DDR 0 W 0 P20DDR 0 W When a pin function is specified to a general purpose I O setting this bit to 1 makes the corresponding port 1 pin an output pin while clearing this bit to 0 makes the pin an input pin 10 2 2 Port 2 Data Register P2DR P2DR stores output data for the port 2 pins Bit Bit Name In...

Page 464: ...Name Initial Value R W Description 7 P27 R 6 P26 R 5 P25 R 4 P24 R 3 P23 R 2 P22 R 1 P21 R 0 P20 R If a port 2 read is performed while P2DDR bits are set to 1 the P2DR values are read If a port 2 read is performed while P2DDR bits are cleared to 0 the pin states are read Note Determined by the states of pins P27 to P20 ...

Page 465: ...and CCLR0 in TCR_5 bit NDER7 in NDERL bit P27DDR and bit ITS15 in ITSR TPU channel 5 settings 1 in table below 2 in table below P27DDR 0 1 1 NDER7 0 1 P27 input P27 output PO7 output TIOCB5 output TIOCB5 input 1 Pin function 548 interrupt input 2 Notes 1 TIOCB5 input when MD3 to MD0 B 0000 or B 01xx and IOB3 1 2 5448 input when ITS15 1 TPU channel 5 settings 2 1 2 2 1 2 MD3 to MD0 B 0000 to B 0011...

Page 466: ...26DDR 0 1 1 NDER6 0 1 P26 input P26 output PO6 output TIOCA5 output TIOCA5 input 1 Pin function 5447 interrupt input 2 Notes 1 TIOCA5 input when MD3 to MD0 B 0000 or B 01xx and IOA3 1 2 5447 input when ITS14 1 TPU channel 5 settings 2 1 2 2 1 2 MD3 to MD0 B 0000 to B 0011 B 0010 B 0010 B 0011 IOA3 to IOA0 B 0000 B 0100 B 1xxx B 0001 to B 0011 B 0101 to B 0111 B xx00 Other than B xx00 Other than B ...

Page 467: ... table below 2 in table below P25DDR 0 1 1 NDER5 0 1 P25 input P25 output PO5 output TIOCB4 output TIOCB4 input 1 Pin function 5446 interrupt input 2 Notes 1 TIOCB4 input when MD3 to MD0 B 0000 or B 01xx and IOB3 to IOB0 B 10xx 2 5446 input when ITS13 1 TPU channel 4 settings 2 1 2 2 1 2 MD3 to MD0 B 0000 to B 0011 B 0010 B 0011 IOB3 to IOB0 B 0000 B 0100 B 1xxx B 0001 to B 0011 B 0101 to B 0111 B...

Page 468: ...R4 0 1 P24 input P24 output PO4 output TIOCA4 output TIOCA4 input 1 RXD4 input pin Pin function 5445 interrupt input 2 Notes 1 TIOCA4 input when MD3 to MD0 B 0000 or B 01xx and IOA3 to IOA0 B 10xx 2 5445 input when ITS12 1 TPU channel 4 settings 2 1 2 1 1 2 MD3 to MD0 B 0001 to B 01xx B 001x B 0010 B 0011 IOA3 to IOA0 B 0000 B 0100 B 1xxx B 0001 to B 0011 B 0101 to B 0111 B xx00 Other than B xx00 ...

Page 469: ... settings 1 in table below 2 in table below P23DDR 0 1 1 NDER3 0 1 P23 input P23 output PO3 output TIOCD3 output TIOCA3 input 1 TXD4 output Pin function 5444 interrupt input 2 Notes 1 TIOCD3 input when MD3 to MD0 B 0000 and IOD3 to IOD0 B 10xx 2 5444 input when ITS11 1 TPU channel 3 settings 2 1 2 2 1 2 MD3 to MD0 B 0001 to B 0011 B 0010 B 0011 IOD3 to IOD0 B 0000 B 0100 B 1xxx B 0001 to B 0011 B ...

Page 470: ...ut PO2 output TIOCC3 output TIOCC3 input 1 Pin function 5443 interrupt input 2 Notes 1 TIOCC3 input when MD3 to MD0 B 0000 and IOC3 to IOC0 B 10xx 2 5443 input when ITS10 1 TPU channel 3 settings 2 1 2 1 1 2 MD3 to MD0 B 0001 to B 01xx B 001x B 0010 B 0011 IOC3 to IOC0 B 0000 B 0100 B 1xxx B 0001 to B 0011 B 0101 to B 0111 B xx00 Other than B xx00 Other than B xx00 CCLR2 to CCLR0 Other than B 101 ...

Page 471: ... in table below 2 in table below P21DDR 0 1 1 NDER1 0 1 P21 input P21 output PO1 output TIOCB3 output TIOCB3 input 1 Pin function 54 interrupt input 2 Notes 1 TIOCB3 input when MD3 to MD0 B 0000 and IOB3 to IOB0 B 10xx 2 54 input when ITS9 1 TPU channel 3 settings 2 1 2 2 1 2 MD3 to MD0 B 0001 to B 0011 B 0010 B 0011 IOB3 to IOB0 B 0000 B 0100 B 1xxx B 0001 to B 0011 B 0101 to B 0111 B xx00 Other ...

Page 472: ...DR 0 1 1 NDER0 0 1 P20 input P20 output PO0 output TIOCA3 output TIOCA3 input 1 Pin function 54 interrupt input 2 Notes 1 TIOCA3 input when MD3 to MD0 B 0000 and IOA3 to IOA0 B 10xx 2 54 input when ITS8 1 TPU channel 3 settings 2 1 2 1 1 2 MD3 to MD0 B 0001 to B 01xx B 001x B 0010 B 0011 IOA3 to IOA0 B 0000 B 0100 B 1xxx B 0001 to B 0011 B 0101 to B 0111 B xx00 Other than B xx00 Other than B xx00 ...

Page 473: ...n Register P3DDR The individual bits of P3DDR specify input or output for the pins of port 3 P3DDR cannot be read if it is an undefined value will be read Bit Bit Name Initial Value R W Description 7 0 6 0 Reserved These bits are always read as 0 and cannot be modified 5 P35DDR 0 W 4 P34DDR 0 W 3 P33DDR 0 W 2 P32DDR 0 W 1 P31DDR 0 W 0 P30DDR 0 W When a pin function is specified to a general purpos...

Page 474: ...stored when the pin function is specified to a general purpose I O 10 3 3 Port 3 Register PORT3 PORT3 shows the pin states PORT3 cannot be modified Bit Bit Name Initial Value R W Description 7 0 6 0 Reserved These bits are always read as 0 and cannot be modified 5 P35 R 4 P34 R 3 P33 R 2 P32 R 1 P31 R 0 P30 R If a port 3 read is performed while P3DDR bits are set to 1 the P3DR values are read If a...

Page 475: ...e Initial Value R W Description 7 0 6 0 Reserved These bits are always read as 0 and cannot be modified 5 P35ODR 0 R W 4 P34ODR 0 R W 3 P33ODR 0 R W 2 P32ODR 0 R W 1 P31ODR 0 R W 0 P30ODR 0 R W Setting a P3ODR bit to 1 makes the corresponding port 3 pin an NMOS open drain output pin while clearing the bit to 0 makes the pin a CMOS output pin ...

Page 476: ...tput pin 0 PF6 is designated as I O port 1 PF6 is designated as 6 output pin 2 LWROE 1 R W 5 Output Enable Selects to enable or disable the 5 output pin 0 PF3 is designated as I O port 1 PF3 is designated as 5 output pin 1 OES 1 R W 2 Output Select Selects the 2 CKE output pin port when the OEE bit is set to 1 in DRAMCR enabling 2 CKE output 0 P35 is designated as 2 CKE output pin 1 PH3 is designa...

Page 477: ...to RMTS0 in DRAMCR bit OES in PFCR2 and bit P35DDR Modes 1 2 4 5 6 7 EXPE 1 OEE 0 1 OES 1 0 SDRAM space 0 1 3 ICE 0 1 0 1 CKE1 0 1 0 1 C A 0 1 0 1 CKE0 0 1 0 1 P35DDR 0 1 0 1 Pin function P35 input P35 output 1 SCK1 output 1 SCK1 output 1 SCK1 input SCL0 I O P35 input P35 output 1 SCK1 output 1 SCK1 output 1 SCK1 input SCL0 I O 2 output CKE output Mode 7 EXPE 0 OEE OES SDRAM space ICE 0 1 CKE1 0 1...

Page 478: ...cannot be set P33 RxD1 SCL1 The pin function is switched as shown below according to the combination of bit ICE in ICCRA of I 2 C_0 bit RE in SCR of SCI_1 and bit P33DDR ICE 0 1 RE 0 1 P33DDR 0 1 Pin function P33 input P33 output 1 RxD1 input SCL1 I O 2 Notes 1 NMOS open drain output when P33ODR 1 2 NMOS open drain output regardless of P33ODR P32 RxD0 IrRxD SDA1 The pin function is switched as sho...

Page 479: ...DDR TE 0 1 P31DDR 0 1 Pin function P31 input P31 output TxD1 output Note NMOS open drain output when P31ODR 1 P30 TxD0 IrTxD The pin function is switched as shown below according to the combination of bit TE in SCR of SCI_0 and bit P30DDR TE 0 1 P30DDR 0 1 Pin function P30 input P30 output RxD0 IrRxD output Note NMOS open drain output when P30ODR 1 ...

Page 480: ...Bit Name Initial Value R W Description 7 P47 R 6 P46 R 5 P45 R 4 P44 R 3 P43 R 2 P42 R 1 P41 R 0 P40 R The pin states are always read from this register Note Determined by the states of pins P47 to P40 10 4 2 Pin Functions Port 4 also functions as the pins for A D converter analog input and D A converter analog output The correspondence between pins are as follows P47 AN7 DA1 AN7 input Pin functio...

Page 481: ... 09 01 page 437 of 904 P45 AN5 Pin function AN5 input P44 AN4 Pin function AN4 input P43 AN3 Pin function AN3 input P42 AN2 Pin function AN2 input P41 AN1 Pin function AN1 input P40 AN0 Pin function AN0 input ...

Page 482: ...ed These bits are always read as 0 and cannot be modified 3 P53DDR 0 W 2 P52DDR 0 W 1 P51DDR 0 W 0 P50DDR 0 W When a pin function is specified to a general purpose I O setting this bit to 1 makes the corresponding port 1 pin an output pin while clearing this bit to 0 makes the pin an input pin 10 5 2 Port 5 Data Register P5DR P5DR stores output data for the port 5 pins Bit Bit Name Initial Value R...

Page 483: ... pin states are read Note Determined by the states of pins P53 to P50 10 5 4 Pin Functions Port 5 pins also function as the pins for SCI I Os A D converter inputs and interrupt inputs The correspondence between the register specification and the pin functions is shown below P53 75 75 75 75 546 546 546 546 The pin function is switched as shown below according to the combination of bits TRGS1 and TR...

Page 484: ...nput when ITS2 0 P51 RxD2 544 544 544 544 The pin function is switched as shown below according to the combination of bit RE in SCR of SCI_2 bit ITS1 in ITSR and bit P51DDR RE 0 1 P51DDR 0 1 P51 input P51 output RxD2 input Pin function 544 interrupt input Note 544 input when ITS1 0 P50 TxD2 543 543 543 543 The pin function is switched as shown below according to the combination of bit TE in SCR of...

Page 485: ...7 0 6 0 Reserved 5 P65DDR 0 W 4 P64DDR 0 W 3 P63DDR 0 W 2 P62DDR 0 W 1 P61DDR 0 W 0 P60DDR 0 W When a pin function is specified to a general purpose I O setting this bit to 1 makes the corresponding port 1 pin an output pin while clearing this bit to 0 makes the pin an input pin 10 6 2 Port 6 Data Register P6DR P6DR stores output data for the port 6 pins Bit Bit Name Initial Value R W Description ...

Page 486: ...ared to 0 the pin states are read Note Determined by the states of pins P65 to P60 10 6 4 Pin Functions Port 6 pins also function as 8 bit timer I Os interrupt inputs and DMAC I Os The correspondence between the register specification and the pin functions is shown below P65 TMO1 4 4 4 4 5446 5446 5446 5446 The pin function is switched as shown below according to the combination of bit SAE1 in DMA...

Page 487: ...1 4 7 1 4 7 1 4 5444 5444 5444 5444 The pin function is switched as shown below according to the combination of bit TEE1 in DMATCR of the DMAC bit P63DDR and bit ITS11 in ITSR TEE1 0 1 P63DDR 0 1 P63 input P63 output 7 1 4 output Pin function 5444 interrupt input Note 5444 interrupt input when ITS11 0 P62 TMCI0 7 1 3 7 1 3 7 1 3 7 1 3 5443 5443 5443 5443 The pin function is switched as shown below...

Page 488: ... 0 1 P61 input P61 output TMRI1 input 5 44 input Pin function 54 interrupt input Notes 1 54 interrupt input when ITS9 0 P60 TMRI0 5 43 5 43 5 43 5 43 54 54 54 54 The pin function is switched as shown below according to the combination of bit and bit ITS8 in ITSR P60DDR 0 1 P60 input P60 output TMRI0 input 5 43 input Pin function 54 interrupt input Notes 1 54 interrupt input when ITS8 0 ...

Page 489: ...P8DDR specify input or output for the pins of port 8 P8DDR cannot be read if it is an undefined value will be read Bit Bit Name Initial Value R W Description 7 0 6 0 Reserved These bits are always read as 0 and cannot be modified 5 P85DDR 0 W 4 P84DDR 0 W 3 P83DDR 0 W 2 P82DDR 0 W 1 P81DDR 0 W 0 P80DDR 0 W When a pin function is specified to a general purpose I O setting this bit to 1 makes the co...

Page 490: ...e pin function is specified to a general purpose I O 10 7 3 Port 8 Register PORT8 PORT8 shows the pin states PORT8 cannot be modified Bit Bit Name Initial Value R W Description 7 Undefined 6 Undefined Reserved These bits are reserved if read they will return an undefined value 5 P85 R 4 P84 R 3 P83 R 2 P82 R 1 P81 R 0 P80 R If a port 8 read is performed while P8DDR bits are set to 1 the P8DR value...

Page 491: ...ed as shown below according to the combination of bit AMS in EDMDR_3 of the EXDMAC bit C in SMR in SCI_3 bit P85DDR and bit ITS5 in ITSR Modes 1 2 4 5 6 7 EXPE 1 AMS 0 1 CKE1 0 1 C 0 1 CKE0 0 1 P85DDR 0 1 P85 input P85 output SCK3 output SCK3 output SCK3 input 6 output Pin function 548 interrupt input Mode 7 EXPE 0 AMS CKE1 0 1 C 0 1 CKE0 0 1 P85DDR 0 1 P85 input P85 output SCK3 output SCK3 output...

Page 492: ...unction 547 interrupt input Mode 7 EXPE 0 AMS P84DDR 0 1 P84 input P84 output Pin function 547 interrupt input Note 547 input when ITS4 1 P83 7 1 6 7 1 6 7 1 6 7 1 6 546 546 546 546 RXD3 The pin function is switched as shown below according to the combination of bit ETENDE in EDMDR_3 of the EXDMAC bit RE in SCR of SCI_3 bit P83DDR and bit ITS3 in ITSR Modes 1 2 4 5 6 7 EXPE 1 ETENDE 0 1 RE 0 1 P83...

Page 493: ... 1 5 7 1 5 7 1 5 The pin function is switched as shown below according to the combination of bit ETENDE in EDMDR_2 of the EXDMAC bit P82DDR and bit ITS2 in ITSR Modes 1 2 4 5 6 7 EXPE 1 ETENDE 0 1 P82DDR 0 1 P82 input P82 output 7 1 5 output Pin function 545 interrupt input Mode 7 EXPE 0 ETENDE P82DDR 0 1 P82 input P82 output Pin function 545 interrupt input Notes 545 input when ITS2 1 ...

Page 494: ...and bit ITS1 in ITSR TE 0 1 P81DDR 0 1 P81 input P81 output TXD3 input 5 46 input Pin function 544 interrupt input Note 544 input when ITS1 1 P80 543 543 543 543 5 45 5 45 5 45 5 45 The pin function is switched as shown below according to the combination of bit P80DDR and bit ITS0 in ITSR P80DDR 0 1 P80 input P80 output 5 45 input Pin function 543 interrupt input Note 543 input when ITS0 1 ...

Page 495: ... Initial Value R W Description 7 P97 R 6 P96 R 5 P95 R 4 P99 R 3 P93 R 2 P92 R 1 P91 R 0 P90 R The pin states are always read when a port 9 read is performed Note Determined by the states of pins P97 to P90 10 8 2 Pin Functions Port 9 also functions as the pins for A D converter analog input and D A converter analog output The correspondence between pins are as follows P97 AN15 DA5 AN15 input Pin ...

Page 496: ...904 P95 AN13 DA3 AN13 input Pin function DA3 output P94 AN12 DA2 AN12 input Pin function DA2 output P93 AN11 Pin function AN11 input P92 AN10 Pin function AN10 input P91 AN9 Pin function AN9 input P90 AN8 Pin function AN8 input ...

Page 497: ...at also has other functions The port A has the following registers Port A data direction register PADDR Port A data register PADR Port A register PORTA Port A MOS pull up control register PAPCR Port A open drain control register PAODR Port function control register 1 PFCR1 ...

Page 498: ...sponding port A pin an I O port and its function can be switched with PADDR Mode 4 When the corresponding bit of A23E to A16E is set to 1 setting a PADDR bit to 1 makes the corresponding port A pin an address output while clearing the bit to 0 makes the pin an input port Clearing one of bits A23E to A16E to 0 makes the corresponding port A pin an I O port and its function can be switched with PADD...

Page 499: ...n is stored when the pin function is specified to a general purpose I O 10 9 3 Port A Register PORTA PORTA shows port A pin states PORTA cannot be modified Bit Bit Name Initial Value R W Description 7 PA7 R 6 PA6 R 5 PA5 R 4 PA4 R 3 PA3 R 2 PA2 R 1 PA1 R 0 PA0 R If a port A read is performed while PADDR bits are set to 1 the PADR values are read If a port A read is performed while PADDR bits are c...

Page 500: ... on the MOS input pull up for that pin 10 9 5 Port A Open Drain Control Register PAODR PAODR specifies an output type of port A Bit Bit Name Initial Value R W Description 7 PA7ODR 0 R W 6 PA6ODR 0 R W 5 PA5ODR 0 R W 4 PA4ODR 0 R W 3 PA3ODR 0 R W 2 PA2ODR 0 R W 1 PA1ODR 0 R W 0 PA0ODR 0 R W When not specified for address output setting the corresponding bit to 1 specifies a pin output type to NMOS ...

Page 501: ... 4 A20E 1 R W Address 20 Enable Enables or disables output for address output 20 A20 0 DR output when PA4DDR 1 1 A20 output when PA4DDR 1 3 A19E 1 R W Address 19 Enable Enables or disables output for address output 19 A19 0 DR output when PA3DDR 1 1 A19 output when PA3DDR 1 2 A18E 1 R W Address 18 Enable Enables or disables output for address output 18 A18 0 DR output when PA2DDR 1 1 A18 output wh...

Page 502: ...R Operating mode 1 2 4 5 6 7 EXPE 0 1 AxxE 0 1 0 1 PADDR 0 1 0 1 0 1 0 1 0 1 PA input PA output PA input Address output PA input PA output PA input PA output PA input Address output Pin function 54Q interrupt input xx 23 to 21 n 7 to 5 Note 54Q input when ITSn 0 PA4 A20 The pin function is switched as shown below according to the operating mode bit EXPE bit A20E and bit PA4DDR Operating mode 1 2 5...

Page 503: ...Up States Port A has a built in MOS input pull up function that can be controlled by software This MOS input pull up function can be used by pins PA7 to PA5 in modes 1 2 5 and 6 and by all pins in modes 4 and 7 MOS input pull up can be specified as on or off on a bit by bit basis Table 10 2 summarizes the MOS input pull up states Table 10 2 MOS Input Pull Up States Port A Mode Reset Hardware Stand...

Page 504: ... for the pins of port B PBDDR cannot be read if it is an undefined value will be read Bit Bit Name Initial Value R W Description 7 PB7DDR 0 W 6 PB6DDR 0 W 5 PB5DDR 0 W 4 PB4DDR 0 W 3 PB3DDR 0 W 2 PB2DDR 0 W 1 PB1DDR 0 W 0 PB0DDR 0 W Modes 1 2 5 and 6 Port B pins are address outputs regardless of the PBDDR settings Modes 4 and 7 when EXPE 1 Setting a PBDDR bit to 1 makes the corresponding port B pi...

Page 505: ...a pin is stored when the pin function is specified to a general purpose I O 10 10 3 Port B Register PORTB PORTB shows port B pin states PORTB cannot be modified Bit Bit Name Initial Value R W Description 7 PB7 R 6 PB6 R 5 PB5 R 4 PB4 R 3 PB3 R 2 PB2 R 1 PB1 R 0 PB0 R If this register is read is while PBDDR bits are set to 1 the PBDR values are read If a port B read is performed while PBDDR bits ar...

Page 506: ...t setting the corresponding bit to 1 turns on the MOS input pull up for that pin 10 10 5 Pin Functions Port B pins also function as the pins for address outputs The correspondence between the register specification and the pin functions is shown below PB7 A15 PB6 A14 PB5 A13 PB4 A12 PB3 A11 PB2 A10 PB1 A9 PB0 A8 The pin function is switched as shown below according to the operating mode bit EXPE a...

Page 507: ...ff on a bit by bit basis In modes 4 and 7 when a PBDDR bit is cleared to 0 setting the corresponding PBPCR bit to 1 turns on the MOS input pull up for that pin Table 10 3 summarizes the MOS input pull up states Table 10 3 MOS Input Pull Up States Port B Mode Reset Hardware Standby Mode Software Standby Mode In Other Operations 1 2 5 6 Off Off Off Off 4 7 On Off On Off Legend Off MOS input pull up ...

Page 508: ... for the pins of port C PCDDR cannot be read if it is an undefined value will be read Bit Bit Name Initial Value R W Description 7 PC7DDR 0 W 6 PC6DDR 0 W 5 PC5DDR 0 W 4 PC4DDR 0 W 3 PC3DDR 0 W 2 PC2DDR 0 W 1 PC1DDR 0 W 0 PC0DDR 0 W Modes 1 2 5 and 6 Port C pins are address outputs regardless of the PCDDR settings Modes 4 and 7 when EXPE 1 Setting a PCDDR bit to 1 makes the corresponding port C pi...

Page 509: ...is stored when the pin function is specified to a general purpose I O 10 11 3 Port C Register PORTC PORTC is shows port C pin states PORTC cannot be modified Bit Bit Name Initial Value R W Description 7 PC7 R 6 PC6 R 5 PC5 R 4 PC4 R 3 PC3 R 2 PC2 R 1 PC1 R 0 PC0 R If a port C read is performed while PCDDR bits are set to 1 the PCDR values are read If a port C read is performed while PCDDR bits are...

Page 510: ...port setting the corresponding bit to 1 turns on the MOS input pull up for that pin 10 11 5 Pin Functions Port C pins also function as the pins for address outputs The correspondence between the register specification and the pin functions is shown below PC7 A7 PC6 A6 PC5 A5 PC4 A4 PC3 A3 PC2 A2 PC1 A1 PC0 A0 The pin function is switched as shown below according to the operating mode bit EXPE and ...

Page 511: ...ff on a bit by bit basis In modes 4 and 7 when a PCDDR bit is cleared to 0 setting the corresponding PCPCR bit to 1 turns on the MOS input pull up for that pin Table 10 4 summarizes the MOS input pull up states Table 10 4 MOS Input Pull Up States Port C Mode Reset Hardware Standby Mode Software Standby Mode In Other Operations 1 2 5 6 Off Off Off Off 4 7 On Off On Off Legend Off MOS input pull up ...

Page 512: ...Bit Bit Name Initial Value R W Description 7 PD7DDR 0 W 6 PD6DDR 0 W 5 PD5DDR 0 W 4 PD4DDR 0 W 3 PD3DDR 0 W 2 PD2DDR 0 W 1 PD1DDR 0 W 0 PD0DDR 0 W Modes 1 2 4 5 6 and 7 when EXPE 1 Port D is automatically designated for data input output Mode 7 when EXPE 0 Port D is an I O port and its pin functions can be switched with PDDDR 10 12 2 Port D Data Register PDDR PDDR stores output data for the port D...

Page 513: ...ined by the states of pins PD7 to PD0 10 12 4 Port D Pull up Control Register PDPCR PDPCR controls on off states of the input pull up MOS of port D PDPCR is valid in mode 7 Bit Bit Name Initial Value R W Description 7 PD7PCR 0 R W 6 PD6PCR 0 R W 5 PD5PCR 0 R W 4 PD4PCR 0 R W 3 PD3PCR 0 R W 2 PD2PCR 0 R W 1 PD1PCR 0 R W 0 PD0PCR 0 R W When PDDDR 0 input port the input pull up MOS of the input pin i...

Page 514: ...an be controlled by software This MOS input pull up function can be used in mode 7 MOS input pull up can be specified as on or off on a bit by bit basis In mode 7 when a PDDDR bit is cleared to 0 setting the corresponding PDPCR bit to 1 turns on the MOS input pull up for that pin Table 10 5 summarizes the MOS input pull up states Table 10 5 MOS Input Pull Up States Port D Mode Reset Hardware Stand...

Page 515: ...5DDR 0 W 4 PE4DDR 0 W 3 PE3DDR 0 W 2 PE2DDR 0 W 1 PE1DDR 0 W 0 PE0DDR 0 W Modes 1 2 4 5 and 6 When 8 bit bus mode is selected port E functions as an I O port The pin states can be changed with PEDDR When 16 bit bus mode is selected port E is designated for data input output For details on 8 bit and 16 bit bus modes see section 6 Bus Controller Mode 7 when EXPE 1 When 8 bit bus mode is selected por...

Page 516: ...n is stored when the pin function is specified to a general purpose I O 10 13 3 Port E Register PORTE PORTE shows port E pin states PORTE cannot be modified Bit Bit Name Initial Value R W Description 7 PE7 R 6 PE6 R 5 PE5 R 4 PE4 R 3 PE3 R 2 PE2 R 1 PE1 R 0 PE0 R If a port E read is performed while PEDDR bits are set to 1 the PEDR values are read If a port E read is performed while PEDDR bits are ...

Page 517: ...orresponding bit is set to 1 10 13 5 Pin Functions Port E pins also function as the pins for data I Os The correspondence between the register specification and the pin functions is shown below PE7 D7 PE6 D6 PE5 D5 PE4 D4 PE3 D3 PE2 D2 PE1 D1 PE0 D0 The pin function is switched as shown below according to the operating mode bus mode bit EXPE and bit PEDDR Operating mode 1 2 4 5 6 7 Bus mode All ar...

Page 518: ...t by bit basis In 8 bit bus mode when a PEDDR bit is cleared to 0 setting the corresponding PEPCR bit to 1 turns on the MOS input pull up for that pin Table 10 6 summarizes the MOS input pull up states Table 10 6 MOS Input Pull Up States Port E Mode Reset Hardware Standby Mode Software Standby Mode In Other Operations 8 bit bus Off Off On Off On Off 1 2 4 to 7 16 bit bus Off Off Legend Off MOS inp...

Page 519: ... register 2 refer to section 10 3 5 Port Function Control Register 2 PFCR2 Port F data direction register PFDDR Port F data register PFDR Port F register PORTF Port Function Control Register 2 PFCR2 10 14 1 Port F Data Direction Register PFDDR The individual bits of PFDDR specify input or output for the pins of port F PFDDR cannot be read if it is an undefined value will be read ...

Page 520: ...3DDR Pins PF2 and PF1 are I O ports and their pin functions can be switched with PFDDR Pin PF0 functions as bus control input output pins 6 8 6 and 7 when the appropriate bus controller settings are made Otherwise these pins are output ports when the corresponding PFDDR bit is set to 1 and input ports when the bit is cleared to 0 Mode 7 when EXPE 1 Pin PF7 to PF3 function in the same way as in mod...

Page 521: ...n is stored when the pin function is specified to a general purpose I O 10 14 3 Port F Register PORTF PORTF shows port F pin states PORTF cannot be modified Bit Bit Name Initial Value R W Description 7 PF7 R 6 PF6 R 5 PF5 R 4 PF4 R 3 PF3 R 2 PF2 R 1 PF1 R 0 PF0 R If a port F read is performed while PFDDR bits are set to 1 the PFDR values are read If a port F read is performed while PFDDR bits are ...

Page 522: ...de 1 2 4 to 7 PFDDR 0 1 Pin function PF7 input ø output PF6 6 6 6 6 The pin function is switched as shown below according to the operating mode bit EXPE bit ASOE and bit PF6DDR Operating mode 1 2 4 5 6 7 EXPE 0 1 ASOE 1 0 1 0 PF6DDR 0 1 0 1 0 1 Pin function 6 output PF6 input PF6 output PF6 input PF6 output 6 output PF6 input PF6 output PF5 5 5 5 5 The pin function is switched as shown below accor...

Page 523: ... 5 6 7 EXPE 0 1 PF4DDR 0 1 Pin function 5 output PF4 input PF4 output 5 output PF3 5 5 5 5 The pin function is switched as shown below according to the operating mode bit EXPE bit LWROE and bit PF3DDR Operating mode 1 2 4 5 6 7 EXPE 0 1 LWROD 1 0 1 0 PF3DDR 0 1 0 1 0 1 Pin function 5 output PF3 input PF3 output PF3 input PF3 output 5 output PF3 input PF3 output ...

Page 524: ...M 2 space area is 16 bit bus space All DRAM synchro nous DRAM 2 space areas are 8 bit bus space or areas 2 to 5 are all normal space Any DRAM synchr onous DRAM 2 space area is 16 bit bus space All DRAM synchro nous DRAM 2 space areas are 8 bit bus space or areas 2 to 5 are all normal space PF2DDR 0 1 0 1 0 1 6 40 2 output PF2 input PF2 output PF2 input PF2 output 6 40 2 output PF2 input PF2 output...

Page 525: ... is DRAM synchr onous DRAM 2 space Areas 2 to 5 are all normal space PF1DDR 0 1 0 1 0 1 8 6 408 2 output PF1 input PF1 output PF1 input PF1 output 8 6 408 2 output PF1 input PF1 output Pin function 5447 interrupt 1 Notes 1 5447 interrupt input when bit ITS14 in ITSR is cleared to 0 2 Not used in H8S 2378 series PF0 7 7 7 7 The pin function is switched as shown below according to the operating mode...

Page 526: ...lowing registers Port G data direction register PGDDR Port G data register PGDR Port G register PORTG Port Function Control Register 0 PFCR0 10 15 1 Port G Data Direction Register PGDDR The individual bits of PGDDR specify input or output for the pins of port G PGDDR cannot be read if it is an undefined value will be read ...

Page 527: ... pins PG3 to PG0 are I O ports and their functions can be switched with PGDDR Mode 7 when EXPE 1 Pins PG6 to PG4 function as bus control input output pins 5 42 and 5 4 when the appropriate bus controller settings are made Otherwise these pins are output ports when the corresponding PGDDR bit is set to 1 and as input ports when the bit is cleared to 0 When the 6 output enable bits CS3E to CS0E are ...

Page 528: ...ored when the pin function is specified to a general purpose I O 10 15 3 Port G Register PORTG PORTG shows port G pin states PORTG cannot be modified Bit Bit Name Initial Value R W Description 7 Undefined Reserved If this bit is read it will return an undefined value 6 PG6 R 5 PG5 R 4 PG4 R 3 PG3 R 2 PG2 R 1 PG1 R 0 PG0 R If a port G read is performed while PGDDR bits are set to 1 the PGDR values ...

Page 529: ... designated as I O port 1 Pin is designated as 6Q output pin n 7 to 0 10 15 5 Pin Functions Port G pins also function as the pins for bus control signal I Os The correspondence between the register specification and the pin functions is shown below PG6 5 4 5 4 5 4 5 4 The pin function is switched as shown below according to the operating mode bit EXPE bit BRLE and bit PG6DDR Operating mode 1 2 4 5...

Page 530: ... output output PG5 input PG5 output PG5 input PG5 output output PG4 5 42 5 42 5 42 5 42 The pin function is switched as shown below according to the operating mode bit EXPE bit BRLE bit BREQO and bit PG4DDR Operating mode 1 2 4 5 6 7 EXPE 0 1 BRLE 0 1 0 1 BREQO 0 1 0 1 PG4DDR 0 1 0 1 0 1 0 1 0 1 Pin function PG4 input PG4 output PG4 input PG4 output 5 42 output PG4 input PG4 output PG4 input PG4 o...

Page 531: ...rea n is in DRAM space Area 3 is in synchro nous DRAM space Area 2 is in synchro nous DRAM space PGnDDR 0 1 0 1 1 0 1 Pin function PGn input PGn output PGn input 6Q output 5 6Q output 6 output 5 6 output PGn input PGn output PGn input PGn output PGn input 6Q output 5 6Q output 6 output 5 6 output PG1 64 64 64 64 PG0 63 63 63 63 The pin function is switched as shown below according to the operating...

Page 532: ...for details on the port function control register 2 refer to section 10 3 5 Port Function Control Register 2 PFCR2 Port H data direction register PHDDR Port H data register PHDR Port H register PORTH Port Function Control Register 0 PFCR0 Port Function Control Register 2 PFCR2 10 16 1 Port H Data Direction Register PHDDR The individual bits of PHDDR specify input or output for the pins of port H P...

Page 533: ...t PH1DDR is set to 1 if the bit is cleared to 0 pin PH1 functions as an I O port When bit CS5E is cleared to 0 pin PH1 is an I O port and its function can be switched with PH1DDR When area 5 is specified as DRAM space and bit CS5E is set to 1 pin PH1 functions as the 5 68 output pin and as an I O port when the bit is cleared to 0 Pin PH0 functions as the 67 output pin when area 4 is specified as n...

Page 534: ...ed when the pin function is specified to a general purpose I O 10 16 3 Port H Register PORTH PORTH shows port H pin states PORTH cannot be modified Bit Bit Name Initial Value R W Description 7 to 4 Undefined Reserved If these bits are read they will return an undefined value 3 PH3 R 2 PH2 R 1 PH1 R 0 PH0 R If a port H read is performed while PHDDR bits are set to 1 the PHDR values are read If a po...

Page 535: ...0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 PH3 input PH3 output PH3 input 6 output PH3 input PH3 output PH3 input 6 output 2 output CKE 2 output PH3 input PH3 output PH3 input PH3 output PH3 input 6 output PH3 input PH3 output PH3 input 6 output 2 output CKE 2 output Pin function 54 input 1 Notes 1 54 interrupt input pin when bit ITS7 is set to 1 in ITSR 2 Not used in H8S 2378 series PH2 69 69 69 69 549 549 ...

Page 536: ...t PH1 input 68 output PH1 input PH1 output 5 68 output SDRAM 2 φ output Notes 1 When SDRAM interface is not used input a low level signal on the DCTL pin 2 Not used in H8S 2378 series PH0 67 67 67 67 5 67 5 67 5 67 5 67 The pin function is switched as shown below according to the operating mode bit EXPE bit CS4E bits RMTS2 to RMTS0 and bit PH0DDR Operating mode 1 2 4 5 6 7 EXPE 0 1 Area 4 Normal s...

Page 537: ...peration Synchronous operations Multiple timer counters TCNT can be written to simultaneously Simultaneous clearing by compare match and input capture possible Register simultaneous input output possible by counter synchronous operation Maximum of 15 phase PWM output possible by combination with synchronous operation Buffer operation settable for channels 0 and 3 Phase counting mode settable indep...

Page 538: ...GRB_1 TGRA_2 TGRB_2 TGRA_3 TGRB_3 TGRA_4 TGRB_4 TGRA_5 TGRB_5 General registers buffer registers TGRC_0 TGRD_0 TGRC_3 TGRD_3 I O pins TIOCA0 TIOCB0 TIOCC0 TIOCD0 TIOCA1 TIOCB1 TIOCA2 TIOCB2 TIOCA3 TIOCB3 TIOCC3 TIOCD3 TIOCA4 TIOCB4 TIOCA5 TIOCB5 Counter clear function TGR compare match or input capture TGR compare match or input capture TGR compare match or input capture TGR compare match or input...

Page 539: ...TGRA compare match or input capture PPG trigger TGRA TGRB compare match or input capture TGRA TGRB compare match or input capture TGRA TGRB compare match or input capture TGRA TGRB compare match or input capture Interrupt sources 5 sources Compare match or input capture 0A Compare match or input capture 0B Compare match or input capture 0C Compare match or input capture 0D Overflow 4 sources Compa...

Page 540: ...OCA2 TIOCB2 Interrupt request signals Channel 3 Channel 4 Channel 5 Interrupt request signals Channel 0 Channel 1 Channel 2 Internal data bus A D conversion start request signal PPG output trigger signal TIORL Module data bus TGI3A TGI3B TGI3C TGI3D TCI3V TGI4A TGI4B TCI4V TCI4U TGI5A TGI5B TCI5V TCI5U TGI0A TGI0B TGI0C TGI0D TCI0V TGI1A TGI1B TCI1V TCI1U TGI2A TGI2B TCI2V TCI2U Channel 3 Channel ...

Page 541: ...t compare output PWM output pin 1 TIOCA1 I O TGRA_1 input capture input output compare output PWM output pin TIOCB1 I O TGRB_1 input capture input output compare output PWM output pin 2 TIOCA2 I O TGRA_2 input capture input output compare output PWM output pin TIOCB2 I O TGRB_2 input capture input output compare output PWM output pin 3 TIOCA3 I O TGRA_3 input capture input output compare output PW...

Page 542: ...r mode register_1 TMDR_1 Timer I O control register _1 TIOR_1 Timer interrupt enable register_1 TIER_1 Timer status register_1 TSR_1 Timer counter_1 TCNT_1 Timer general register A_1 TGRA_1 Timer general register B_1 TGRB_1 Timer control register_2 TCR_2 Timer mode register_2 TMDR_2 Timer I O control register_2 TIOR_2 Timer interrupt enable register_2 TIER_2 Timer status register_2 TSR_2 Timer cou...

Page 543: ...mer general register B_4 TGRB_4 Timer control register_5 TCR_5 Timer mode register_5 TMDR_5 Timer I O control register_5 TIOR_5 Timer interrupt enable register_5 TIER_5 Timer status register_5 TSR_5 Timer counter_5 TCNT_5 Timer general register A_5 TGRA_5 Timer general register B_5 TGRB_5 Common Registers Timer start register TSTR Timer synchronous register TSYR 11 3 1 Timer Control Register TCR T...

Page 544: ...ing edge If phase counting mode is used on channels 1 2 4 and 5 this setting is ignored and the phase counting mode setting has priority Internal clock edge selection is valid when the input clock is ø 4 or slower This setting is ignored if the input clock is ø 1 or when overflow underflow of another channel is selected 00 Count at rising edge 01 Count at falling edge 1x Count at both edges Legend...

Page 545: ...onous operation 1 Notes 1 Synchronous operation setting is performed by setting the SYNC bit in TSYR to 1 2 When TGRC or TGRD is used as a buffer register TCNT is not cleared because the buffer register setting has priority and compare match input capture does not occur Table 11 4 CCLR2 to CCLR0 Channels 1 2 4 and 5 Channel Bit 7 Reserved 2 Bit 6 CCLR1 Bit 5 CCLR0 Description 1 2 4 5 0 0 0 TCNT cl...

Page 546: ... 1 0 External clock counts on TCLKC pin input 1 External clock counts on TCLKD pin input Table 11 6 TPSC2 to TPSC0 Channel 1 Channel Bit 2 TPSC2 Bit 1 TPSC1 Bit 0 TPSC0 Description 1 0 0 0 Internal clock counts on ø 1 1 Internal clock counts on ø 4 1 0 Internal clock counts on ø 16 1 Internal clock counts on ø 64 1 0 0 External clock counts on TCLKA pin input 1 External clock counts on TCLKB pin i...

Page 547: ...B pin input 1 0 External clock counts on TCLKC pin input 1 Internal clock counts on ø 1024 Note This setting is ignored when channel 2 is in phase counting mode Table 11 8 TPSC2 to TPSC0 Channel 3 Channel Bit 2 TPSC2 Bit 1 TPSC1 Bit 0 TPSC0 Description 3 0 0 0 Internal clock counts on ø 1 1 Internal clock counts on ø 4 1 0 Internal clock counts on ø 16 1 Internal clock counts on ø 64 1 0 0 Externa...

Page 548: ... 1024 1 Counts on TCNT5 overflow underflow Note This setting is ignored when channel 4 is in phase counting mode Table 11 10 TPSC2 to TPSC0 Channel 5 Channel Bit 2 TPSC2 Bit 1 TPSC1 Bit 0 TPSC0 Description 5 0 0 0 Internal clock counts on ø 1 1 Internal clock counts on ø 4 1 0 Internal clock counts on ø 16 1 Internal clock counts on ø 64 1 0 0 External clock counts on TCLKA pin input 1 External cl...

Page 549: ...n channels 1 2 4 and 5 which have no TGRD bit 5 is reserved It is always read as 0 and cannot be modified 0 TGRB operates normally 1 TGRB and TGRD used together for buffer operation 4 BFA 0 R W Buffer Operation A Specifies whether TGRA is to operate in the normal way or TGRA and TGRC are to be used together for buffer operation When TGRC is used as a buffer register TGRC input capture output compa...

Page 550: ... and 3 In this case 0 should always be written to MD2 11 3 3 Timer I O Control Register TIOR TIOR registers control the TGR registers The TPU has eight TIOR registers two each for channels 0 and 3 and one each for channels 1 2 4 and 5 Care is required since TIOR is affected by the TMDR setting The initial output specified by TIOR is valid when the counter is stopped the CST bit in TSTR is cleared ...

Page 551: ...3 IOA2 IOA1 IOA0 0 0 0 0 R W R W R W R W I O Control A3 to A0 Specify the function of TGRA For details see tables 11 20 11 22 11 23 11 24 11 26 and 11 27 TIORL_0 TIORL_3 Bit Bit Name Initial Value R W Description 7 6 5 4 IOD3 IOD2 IOD1 IOD0 0 0 0 0 R W R W R W R W I O Control D3 to D0 Specify the function of TGRD For details see tables 11 13 and 11 17 3 2 1 0 IOC3 IOC2 IOC1 IOC0 0 0 0 0 R W R W R ...

Page 552: ...pare match 1 0 Initial output is 1 output 1 output at compare match 1 Initial output is 1 output Toggle output at compare match 1 0 0 0 Capture input source is TIOCB0 pin Input capture at rising edge 1 Capture input source is TIOCB0 pin Input capture at falling edge 1 x Input capture register Capture input source is TIOCB0 pin Input capture at both edges 1 x x Capture input source is channel 1 cou...

Page 553: ...tput is 1 output Toggle output at compare match 1 0 0 0 Capture input source is TIOCD0 pin Input capture at rising edge 1 Capture input source is TIOCD0 pin Input capture at falling edge 1 x Input capture register 2 Capture input source is TIOCD0 pin Input capture at both edges 1 x x Capture input source is channel 1 count clock Input capture at TCNT_1 count up count down 1 Legend x Don t care Not...

Page 554: ... match 1 0 0 Output disabled 1 Initial output is 1 output 0 output at compare match 1 0 Initial output is 1 output 1 output at compare match 1 Initial output is 1 output Toggle output at compare match 1 0 0 0 Capture input source is TIOCB1 pin Input capture at rising edge 1 Capture input source is TIOCB1 pin Input capture at falling edge 1 x Input capture register Capture input source is TIOCB1 pi...

Page 555: ...1 Initial output is 0 output Toggle output at compare match 1 0 0 Output disabled 1 Initial output is 1 output 0 output at compare match 1 0 Initial output is 1 output 1 output at compare match 1 Initial output is 1 output Toggle output at compare match 1 x 0 0 Capture input source is TIOCB2 pin Input capture at rising edge 1 Capture input source is TIOCB2 pin Input capture at falling edge 1 x Inp...

Page 556: ...pare match 1 0 Initial output is 1 output 1 output at compare match 1 Initial output is 1 output Toggle output at compare match 1 0 0 0 Capture input source is TIOCB3 pin Input capture at rising edge 1 Capture input source is TIOCB3 pin Input capture at falling edge 1 x Input capture register Capture input source is TIOCB3 pin Input capture at both edges 1 x x Capture input source is channel 4 cou...

Page 557: ...tput is 1 output Toggle output at compare match 1 0 0 0 Capture input source is TIOCD3 pin Input capture at rising edge 1 Capture input source is TIOCD3 pin Input capture at falling edge 1 x Input capture register 2 Capture input source is TIOCD3 pin Input capture at both edges 1 x x Capture input source is channel 4 count clock Input capture at TCNT_4 count up count down 1 Legend x Don t care Not...

Page 558: ... Output disabled 1 Initial output is 1 output 0 output at compare match 1 0 Initial output is 1 output 1 output at compare match 1 Initial output is 1 output Toggle output at compare match 1 0 0 0 Capture input source is TIOCB4 pin Input capture at rising edge 1 Capture input source is TIOCB4 pin Input capture at falling edge 1 x Input capture register Capture input source is TIOCB4 pin Input capt...

Page 559: ...1 Initial output is 0 output Toggle output at compare match 1 0 0 Output disabled 1 Initial output is 1 output 0 output at compare match 1 0 Initial output is 1 output 1 output at compare match 1 Initial output is 1 output Toggle output at compare match 1 x 0 0 Capture input source is TIOCB5 pin Input capture at rising edge 1 Capture input source is TIOCB5 pin Input capture at falling edge 1 x Inp...

Page 560: ...ompare match 1 0 0 Output disabled 1 Initial output is 1 output 0 output at compare match 1 0 Initial output is 1 output 1 output at compare match 1 Initial output is 1 output Toggle output at compare match 1 0 0 0 Capture input source is TIOCA0 pin Input capture at rising edge 1 Capture input source is TIOCA0 pin Input capture at falling edge 1 x Input capture register Capture input source is TIO...

Page 561: ...pare match 1 0 Initial output is 1 output 1 output at compare match 1 Initial output is 1 output Toggle output at compare match 1 0 0 0 Capture input source is TIOCC0 pin Input capture at rising edge 1 Capture input source is TIOCC0 pin Input capture at falling edge 1 x Input capture register Capture input source is TIOCC0 pin Input capture at both edges 1 x x Capture input source is channel 1 cou...

Page 562: ...ut disabled 1 Initial output is 1 output 0 output at compare match 1 0 Initial output is 1 output 1 output at compare match 1 Initial output is 1 output Toggle output at compare match 1 0 0 0 Capture input source is TIOCA1 pin Input capture at rising edge 1 Capture input source is TIOCA1 pin Input capture at falling edge 1 x Input capture register Capture input source is TIOCA1 pin Input capture a...

Page 563: ...1 Initial output is 0 output Toggle output at compare match 1 0 0 Output disabled 1 Initial output is 1 output 0 output at compare match 1 0 Initial output is 1 output 1 output at compare match 1 Initial output is 1 output Toggle output at compare match 1 x 0 0 Capture input source is TIOCA2 pin Input capture at rising edge 1 Capture input source is TIOCA2 pin Input capture at falling edge 1 x Inp...

Page 564: ...ompare match 1 0 0 Output disabled 1 Initial output is 1 output 0 output at compare match 1 0 Initial output is 1 output 1 output at compare match 1 Initial output is 1 output Toggle output at compare match 1 0 0 0 Capture input source is TIOCA3 pin Input capture at rising edge 1 Capture input source is TIOCA3 pin Input capture at falling edge 1 x Input capture register Capture input source is TIO...

Page 565: ...pare match 1 0 Initial output is 1 output 1 output at compare match 1 Initial output is 1 output Toggle output at compare match 1 0 0 0 Capture input source is TIOCC3 pin Input capture at rising edge 1 Capture input source is TIOCC3 pin Input capture at falling edge 1 x Input capture register Capture input source is TIOCC3 pin Input capture at both edges 1 x x Capture input source is channel 4 cou...

Page 566: ... Output disabled 1 Initial output is 1 output 0 output at compare match 1 0 Initial output is 1 output 1 output at compare match 1 Initial output is 1 output Toggle output at compare match 1 0 0 0 Capture input source is TIOCA4 pin Input capture at rising edge 1 Capture input source is TIOCA4 pin Input capture at falling edge 1 x Input capture register Capture input source is TIOCA4 pin Input capt...

Page 567: ...1 Initial output is 0 output Toggle output at compare match 1 0 0 Output disabled 1 Initial output is 1 output 0 output at compare match 1 0 Initial output is 1 output 1 output at compare match 1 Initial output is 1 output Toggle output at compare match 1 x 0 0 Input capture source is TIOCA5 pin Input capture at rising edge 1 Input capture source is TIOCA5 pin Input capture at falling edge 1 x Inp...

Page 568: ...interrupt requests TCIU by the TCFU flag when the TCFU flag in TSR is set to 1 in channels 1 2 4 and 5 In channels 0 and 3 bit 5 is reserved It is always read as 0 and cannot be modified 0 Interrupt requests TCIU by TCFU disabled 1 Interrupt requests TCIU by TCFU enabled 4 TCIEV 0 R W Overflow Interrupt Enable Enables or disables interrupt requests TCIV by the TCFV flag when the TCFV flag in TSR i...

Page 569: ...uests TGIC by TGFC bit disabled 1 Interrupt requests TGIC by TGFC bit enabled 1 TGIEB 0 R W TGR Interrupt Enable B Enables or disables interrupt requests TGIB by the TGFB bit when the TGFB bit in TSR is set to 1 0 Interrupt requests TGIB by TGFB bit disabled 1 Interrupt requests TGIB by TGFB bit enabled 0 TGIEA 0 R W TGR Interrupt Enable A Enables or disables interrupt requests TGIA by the TGFA bi...

Page 570: ...This bit is always read as 1 and cannot be modified 5 TCFU 0 R W Underflow Flag Status flag that indicates that TCNT underflow has occurred when channels 1 2 4 and 5 are set to phase counting mode In channels 0 and 3 bit 5 is reserved It is always read as 0 and cannot be modified Setting condition When the TCNT value underflows changes from H 0000 to H FFFF Clearing condition When 0 is written to ...

Page 571: ...ring conditions When DTC is activated by TGID interrupt while DISEL bit of MRB in DTC is 0 When 0 is written to TGFD after reading TGFD 1 2 TGFC 0 R W Input Capture Output Compare Flag C Status flag that indicates the occurrence of TGRC input capture or compare match in channels 0 and 3 In channels 1 2 4 and 5 bit 2 is reserved It is always read as 0 and cannot be modified Setting conditions When ...

Page 572: ...Flag A Status flag that indicates the occurrence of TGRA input capture or compare match Setting conditions When TCNT TGRA while TGRA is functioning as output compare register When TCNT value is transferred to TGRA by input capture signal while TGRA is functioning as input capture register Clearing conditions When DTC is activated by TGIA interrupt while DISEL bit of MRB in DTC is 0 When 0 is writt...

Page 573: ... selects operation stoppage for channels 0 to 5 When setting the operating mode in TMDR or setting the count clock in TCR first stop the TCNT counter Bit Bit Name Initial value R W Description 7 6 0 Reserved These bits should always be written with 0 5 4 3 2 1 0 CST5 CST4 CST3 CST2 CST1 CST0 0 0 0 0 0 0 R W R W R W R W R W R W Counter Start 5 to 0 These bits select operation or stoppage for TCNT I...

Page 574: ...se bits select whether operation is independent of or synchronized with other channels When synchronous operation is selected synchronous presetting of multiple channels and synchronous clearing through counter clearing on another channel are possible To set synchronous operation the SYNC bits for at least two channels must be set to 1 To set synchronous clearing in addition to the SYNC bit the TC...

Page 575: ...of the count operation setting procedure Select counter clock Operation selection Select counter clearing source Periodic counter Set period Start count Periodic counter 1 2 4 3 5 Free running counter Start count Free running counter 5 1 2 3 4 5 Select output compare register Select the counter clock with bits TPSC2 to TPSC0 in TCR At the same time select the input clock edge with bits CKEG1 and C...

Page 576: ...00 CST bit TCFV Time Figure 11 3 Free Running Counter Operation When compare match is selected as the TCNT clearing source the TCNT counter for the relevant channel performs periodic count operation The TGR register for setting the period is designated as an output compare register and counter clearing by compare match is selected by means of bits CCLR2 to CCLR0 in TCR After the settings have been...

Page 577: ...gure 11 5 shows an example of the setting procedure for waveform output by a compare match Select waveform output mode Output selection Set output timing Start count Waveform output 1 2 3 1 Select initial value 0 output or 1 output and compare match output value 0 output 1 output or toggle output by means of TIOR The set initial value is output at the TIOC pin until the first compare match occurs ...

Page 578: ... H FFFF H 0000 TIOCA TIOCB Time TGRA TGRB No change No change No change No change 1 output 0 output Figure 11 6 Example of 0 Output 1 Output Operation Figure 11 7 shows an example of toggle output In this example TCNT has been designated as a periodic counter with counter clearing performed by compare match B and settings have been made so that output is toggled by both compare match A and compare...

Page 579: ...re for input capture operation Figure 11 8 shows an example of the setting procedure for input capture operation Select input capture input Input selection Start count Input capture operation 1 2 1 Designate TGR as an input capture register by means of TIOR and select the input capture source and input signal edge rising edge falling edge or both edges 2 Set the CST bit in TSTR to 1 to start the c...

Page 580: ...es in multiple TCNT counters can be rewritten simultaneously synchronous presetting Also multiple of TCNT counters can be cleared simultaneously synchronous clearing by making the appropriate setting in TCR Synchronous operation enables TGR to be incremented with respect to a single time base Channels 0 to 5 can all be designated for synchronous operation Example of Synchronous Operation Setting P...

Page 581: ...CLR0 in TCR to designate synchronous clearing for the counter clearing source 5 Set to 1 the CST bits in TSTR for the relevant channels to start the count operation Set synchronous operation Figure 11 10 Example of Synchronous Operation Setting Procedure Example of Synchronous Operation Figure 11 11 shows an example of synchronous operation In this example synchronous operation and PWM mode 1 have...

Page 582: ...n differs depending on whether TGR has been designated as an input capture register or a compare match register Table 11 28 shows the register combinations used in buffer operation Table 11 28 Register Combinations in Buffer Operation Channel Timer General Register Buffer Register 0 TGRA_0 TGRC_0 TGRB_0 TGRD_0 3 TGRA_3 TGRC_3 TGRB_3 TGRD_3 When TGR is an output compare register When a compare matc...

Page 583: ...13 Buffer register Timer general register TCNT Input capture signal Figure 11 13 Input Capture Buffer Operation Example of Buffer Operation Setting Procedure Figure 11 14 shows an example of the buffer operation setting procedure Select TGR function Buffer operation Set buffer operation Start count Buffer operation 1 2 3 1 Designate TGR as an input capture register or output compare register by me...

Page 584: ... each time compare match A occurs For details on PWM modes see section 11 4 5 PWM Modes TCNT value TGRB_0 H 0000 TGRC_0 TGRA_0 H 0200 H 0520 TIOCA H 0200 H 0450 H 0520 H 0450 TGRA_0 H 0450 H 0200 Transfer Time Figure 11 15 Example of Buffer Operation 1 2 When TGR is an input capture register Figure 11 16 shows an operation example in which TGRA has been designated as an input capture register and ...

Page 585: ...l 1 channel 4 counter clock at overflow underflow of TCNT_2 TCNT_5 as set in bits TPSC2 to TPSC0 in TCR Underflow occurs only when the lower 16 bit TCNT is in phase counting mode Table 11 29 shows the register combinations used in cascaded operation Note When phase counting mode is set for channel 1 or 4 the counter clock setting is invalid and the counter operates independently in phase counting ...

Page 586: ... when counting upon TCNT_2 overflow underflow has been set for TCNT_1 TGRA_1 and TGRA_2 have been designated as input capture registers and the TIOC pin rising edge has been selected When a rising edge is input to the TIOCA1 and TIOCA2 pins simultaneously the upper 16 bits of the 32 bit data are transferred to TGRA_1 and the lower 16 bits to TGRA_2 TCNT_2 clock TCNT_2 H FFFF H 0000 H 0001 TIOCA1 T...

Page 587: ...n TIOR are output from the TIOCA and TIOCC pins at compare matches A and C respectively The outputs specified by bits IOB3 to IOB0 and IOD3 to IOD0 in TIOR are output at compare matches B and D respectively The initial output value is the value set in TGRA or TGRC If the set values of paired TGRs are identical the output value does not change when a compare match occurs In PWM mode 1 a maximum 8 p...

Page 588: ...B_0 TIOCB0 TGRC_0 TIOCC0 TIOCC0 TGRD_0 TIOCD0 1 TGRA_1 TIOCA1 TIOCA1 TGRB_1 TIOCB1 2 TGRA_2 TIOCA2 TIOCA2 TGRB_2 TIOCB2 3 TGRA_3 TIOCA3 TIOCA3 TGRB_3 TIOCB3 TGRC_3 TIOCC3 TIOCC3 TGRD_3 TIOCD3 4 TGRA_4 TIOCA4 TIOCA4 TGRB_4 TIOCB4 5 TGRA_5 TIOCA5 TIOCA5 TGRB_5 TIOCB5 Note In PWM mode 2 PWM output is not possible for the TGR register in which the cycle is set ...

Page 589: ... 3 Use TIOR to designate the TGR as an output compare register and select the initial value and output value 4 Set the cycle in the TGR selected in 2 and set the duty in the other TGRs 5 Select the PWM mode with bits MD3 to MD0 in TMDR 6 Set the CST bit in TSTR to 1 to start the count operation Figure 11 20 Example of PWM Mode Setting Procedure Examples of PWM Mode Operation Figure 11 21 shows an ...

Page 590: ...pare match is set as the TCNT clearing source and 0 is set for the initial output value and 1 for the output value of the other TGR registers TGRA_0 to TGRD_0 TGRA_1 to output a 5 phase PWM waveform In this case the value set in TGRB_1 is used as the cycle and the values set in the other TGRs as the duty TCNT value TGRB_1 H 0000 TIOCA0 Counter cleared by TGRB_1 compare match Time TGRA_1 TGRD_0 TGR...

Page 591: ...TGRA H 0000 TIOCA Time TGRB 100 duty TGRB rewritten TGRB rewritten TGRB rewritten Output does not change when cycle register and duty register compare matches occur simultaneously TCNT value TGRA H 0000 TIOCA Time TGRB 100 duty TGRB rewritten TGRB rewritten TGRB rewritten Output does not change when cycle register and duty register compare matches occur simultaneously 0 duty Figure 11 23 Example o...

Page 592: ...CFV flag in TSR is set when underflow occurs while TCNT is counting down the TCFU flag is set The TCFD bit in TSR is the count direction flag Reading the TCFD flag provides an indication of whether TCNT is counting up or down Table 11 31 shows the correspondence between external clock pins and channels Table 11 31 Clock Input Pins in Phase Counting Mode External Clock Pins Channels A Phase B Phase...

Page 593: ... 11 32 summarizes the TCNT up down count conditions TCNT value Time Down count Up count TCLKA channels 1 and 5 TCLKC channels 2 and 4 TCLKB channels 1 and 5 TCLKD channels 2 and 4 Figure 11 25 Example of Phase Counting Mode 1 Operation Table 11 32 Up Down Count Conditions in Phase Counting Mode 1 TCLKA Channels 1 and 5 TCLKC Channels 2 and 4 TCLKB Channels 1 and 5 TCLKD Channels 2 and 4 Operation ...

Page 594: ...LKB channels 1 and 5 TCLKD channels 2 and 4 Figure 11 26 Example of Phase Counting Mode 2 Operation Table 11 33 Up Down Count Conditions in Phase Counting Mode 2 TCLKA Channels 1 and 5 TCLKC Channels 2 and 4 TCLKB Channels 1 and 5 TCLKD Channels 2 and 4 Operation High level Don t care Low level Don t care Low level Don t care High level Up count High level Don t care Low level Don t care High leve...

Page 595: ...LKB channels 1 and 5 TCLKD channels 2 and 4 Figure 11 27 Example of Phase Counting Mode 3 Operation Table 11 34 Up Down Count Conditions in Phase Counting Mode 3 TCLKA Channels 1 and 5 TCLKC Channels 2 and 4 TCLKB Channels 1 and 5 TCLKD Channels 2 and 4 Operation High level Don t care Low level Don t care Low level Don t care High level Up count High level Down count Low level Don t care High leve...

Page 596: ...KC channels 2 and 4 TCLKB channels 1 and 5 TCLKD channels 2 and 4 Figure 11 28 Example of Phase Counting Mode 4 Operation Table 11 35 Up Down Count Conditions in Phase Counting Mode 4 TCLKA Channels 1 and 5 TCLKC Channels 2 and 4 TCLKB Channels 1 and 5 TCLKD Channels 2 and 4 Operation High level Up count Low level Low level Don t care High level High level Down count Low level High level Don t car...

Page 597: ...r input capture with TGRB_0 and TGRD_0 operating in buffer mode The channel 1 counter input clock is designated as the TGRB_0 input capture source and detection of the pulse width of 2 phase encoder 4 multiplication pulses is performed TGRA_1 and TGRB_1 for channel 1 are designated for input capture channel 0 TGRA_0 and TGRC_0 compare matches are selected as the input capture source and the up dow...

Page 598: ... or disabled individually When an interrupt request is generated the corresponding status flag in TSR is set to 1 If the corresponding enable disable bit in TIER is set to 1 at this time an interrupt is requested The interrupt request is cleared by clearing the status flag to 0 Relative channel priorities can be changed by the interrupt controller but the priority order within a channel is fixed F...

Page 599: ...verflow TCFV_2 Not possible Not possible TCI2U TCNT_2 underflow TCFU_2 Not possible Not possible 3 TGI3A TGRA_3 input capture compare match TGFA_3 Possible Possible TGI3B TGRB_3 input capture compare match TGFB_3 Possible Not possible TGI3C TGRC_3 input capture compare match TGFC_3 Possible Not possible TGI3D TGRD_3 input capture compare match TGFD_3 Possible Not possible TCI3V TCNT_3 overflow TCF...

Page 600: ...1 2 4 and 5 11 6 DTC Activation The DTC can be activated by the TGR input capture compare match interrupt for a channel For details see section 9 Data Transfer Controller A total of 16 TPU input capture compare match interrupts can be used as DTC activation sources four each for channels 0 and 3 and two each for channels 1 2 4 and 5 11 7 DMAC Activation The DMAC can be activated by the TGRA input ...

Page 601: ...k External clock φ N 1 N N 1 N 2 Falling edge Rising edge Falling edge Figure 11 31 Count Timing in External Clock Operation Output Compare Output Timing A compare match signal is generated in the final state in which TCNT and TGR match the point at which the count value matched by TCNT is updated When a compare match signal is generated the output value set in TIOR is output at the output compare...

Page 602: ...put capture signal timing TCNT Input capture input N N 1 N 2 N N 2 TGR Input capture signal φ Figure 11 33 Input Capture Input Signal Timing Timing for Counter Clearing by Compare Match Input Capture Figure 11 34 shows the timing when counter clearing by compare match occurrence is specified and figure 11 35 shows the timing when counter clearing by input capture occurrence is specified ...

Page 603: ...ing Compare Match TCNT Counter clear signal Input capture signal TGR N H 0000 N φ Figure 11 35 Counter Clear Timing Input Capture Buffer Operation Timing Figures 11 36 and 11 37 show the timings in buffer operation TGRA TGRB Compare match signal TCNT TGRC TGRD n N N n n 1 φ Figure 11 36 Buffer Operation Timing Compare Match ...

Page 604: ...8 shows the timing for setting of the TGF flag in TSR by compare match occurrence and the TGI interrupt request signal timing TGR TCNT TCNT input clock N N N 1 Compare match signal TGF flag TGI interrupt φ Figure 11 38 TGI Interrupt Timing Compare Match TGF Flag Setting Timing in Case of Input Capture Figure 11 39 shows the timing for setting of the TGF flag in TSR by input capture occurrence and ...

Page 605: ...shows the timing for setting of the TCFV flag in TSR by overflow occurrence and the TCIV interrupt request signal timing Figure 11 41 shows the timing for setting of the TCFU flag in TSR by underflow occurrence and the TCIU interrupt request signal timing Overflow signal TCNT overflow TCNT input clock H FFFF H 0000 TCFV flag TCIV interrupt φ Figure 11 40 TCIV Interrupt Setting Timing ...

Page 606: ...s read as 1 by the CPU it is cleared by writing 0 to it When the DTC or DMAC is activated the flag is cleared automatically Figure 11 42 shows the timing for status flag clearing by the CPU and figure 11 43 shows the timing for status flag clearing by the DTC or DMAC Status flag Write signal Address TSR address Interrupt request signal TSR write cycle T1 T2 φ Figure 11 42 Timing for Status Flag Cl...

Page 607: ...ation to be halted Register access is enabled by clearing module stop mode For details refer to section 22 Power Down Modes 11 10 2 Input Clock Restrictions The input clock pulse width must be at least 1 5 states in the case of single edge detection and at least 2 5 states in the case of both edge detection The TPU will not operate properly with a narrower pulse width In phase counting mode the ph...

Page 608: ... clearing by compare match is set TCNT is cleared in the final state in which it matches the TGR value the point at which the count value matched by TCNT is updated Consequently the actual counter frequency is given by the following formula f ø N 1 Where f Counter frequency ø Operating frequency N TGR set value 11 10 4 Contention between TCNT Write and Clear Operations If the counter clearing sign...

Page 609: ...1 10 5 Contention between TCNT Write and Increment Operations If incrementing occurs in the T2 state of a TCNT write cycle the TCNT write takes precedence and TCNT is not incremented Figure 11 46 shows the timing in this case TCNT input clock Write signal Address ø TCNT address TCNT TCNT write cycle T1 T2 N M TCNT write data Figure 11 46 Contention between TCNT Write and Increment Operations ...

Page 610: ...ritten Figure 11 47 shows the timing in this case Compare match signal Write signal Address ø TGR address TCNT TGR write cycle T1 T2 N M TGR write data TGR N N 1 Disabled Figure 11 47 Contention between TGR Write and Compare Match 11 10 7 Contention between Buffer Register Write and Compare Match If a compare match occurs in the T2 state of a TGR write cycle the data transferred to TGR by the buff...

Page 611: ...te and Compare Match 11 10 8 Contention between TGR Read and Input Capture If the input capture signal is generated in the T1 state of a TGR read cycle the data that is read will be the data after input capture transfer Figure 11 49 shows the timing in this case Input capture signal Read signal Address ø TGR address TGR TGR read cycle T1 T2 M Internal data bus X M Figure 11 49 Contention between T...

Page 612: ...the timing in this case Input capture signal Write signal Address ø TCNT TGR write cycle T1 T2 M TGR M TGR address Figure 11 50 Contention between TGR Write and Input Capture 11 10 10 Contention between Buffer Register Write and Input Capture If the input capture signal is generated in the T2 state of a buffer register write cycle the buffer operation takes precedence and the write to the buffer r...

Page 613: ...ion between Overflow Underflow and Counter Clearing If overflow underflow and counter clearing occur simultaneously the TCFV TCFU flag in TSR is not set and TCNT clearing takes precedence Figure 11 52 shows the operation timing when a TGR compare match is specified as the clearing source and H FFFF is set in TGR Counter clearing signal TCNT input clock ø TCNT TGF Disabled TCFV H FFFF H 0000 Figure...

Page 614: ...gure 11 53 Contention between TCNT Write and Overflow 11 10 13 Multiplexing of I O Pins In this LSI the TCLKA input pin is multiplexed with the TIOCC0 I O pin the TCLKB input pin with the TIOCD0 I O pin the TCLKC input pin with the TIOCB1 I O pin and the TCLKD input pin with the TIOCB2 I O pin When an external clock is input compare match output should not be performed from a multiplexed pin 11 10...

Page 615: ...lse outputs are divided into 4 bit groups groups 3 to 0 that can operate both simultaneously and independently The block diagram of PPG is shown in figure 12 1 12 1 Features 16 bit output data Four output groups Selectable output trigger signals Non overlap mode Can operate together with the data transfer controller DTC and the DMA controller DMAC Settable inverted output Module stop mode can be s...

Page 616: ...egister PPG output control register Next data enable register H Next data enable register L Next data register H Next data register L Output data register H Output data register L Internal data bus Pulse output pins group 3 Pulse output pins group 2 Pulse output pins group 1 Pulse output pins group 0 PODRH PODRL NDRH NDRL Control logic NDERH PMR NDERL PCR Figure 12 1 Block Diagram of PPG ...

Page 617: ...tput Group 2 pulse output PO7 Output PO6 Output PO5 Output PO4 Output Group 1 pulse output PO3 Output PO2 Output PO1 Output PO0 Output Group 0 pulse output 12 3 Register Descriptions The PPG has the following registers Next data enable register H NDERH Next data enable register L NDERL Output data register H PODRH Output data register L PODRL Next data register H NDRH Next data register L NDRL PPG...

Page 618: ...Data Enable 15 to 8 When a bit is set to 1 the value in the corresponding NDRH bit is transferred to the PODRH bit by the selected output trigger Values are not transferred from NDRH to PODRH for cleared bits NDERL Bit Bit Name Initial Value R W Description 7 6 5 4 3 2 1 0 NDER7 NDER6 NDER5 NDER4 NDER3 NDER2 NDER1 NDER0 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W Next Data Enable 7 to 0 When a...

Page 619: ... the output trigger transfers NDRH values to this register during PPG operation While NDERH is set to 1 the CPU cannot write to this register While NDERH is cleared the initial output value of the pulse can be set PODRL Bit Bit Name Initial Value R W Description 7 6 5 4 3 2 1 0 POD7 POD6 POD5 POD4 POD3 POD2 POD1 POD0 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W Output Data Register 7 to 0 For b...

Page 620: ... NDR14 NDR13 NDR12 NDR11 NDR10 NDR9 NDR8 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W Next Data Register 15 to 8 The register contents are transferred to the corresponding PODRH bits by the output trigger specified with PCR If pulse output groups 2 and 3 have different output triggers upper 4 bits and lower 4 bits are mapped to the different addresses as shown below Bit Bit Name Initial Value R...

Page 621: ...al Value R W Description 7 6 5 4 3 2 1 0 NDR7 NDR6 NDR5 NDR4 NDR3 NDR2 NDR1 NDR0 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W Next Data Register 7 to 0 The register contents are transferred to the corresponding PODRL bits by the output trigger specified with PCR If pulse output groups 0 and 1 have different output triggers upper 4 bits and lower 4 bits are mapped to the different addresses as s...

Page 622: ...tion 7 6 G3CMS1 G3CMS0 1 1 R W R W Group 3 Compare Match Select 1 and 0 Select output trigger of pulse output group 3 00 Compare match in TPU channel 0 01 Compare match in TPU channel 1 10 Compare match in TPU channel 2 11 Compare match in TPU channel 3 5 4 G2CMS1 G2CMS0 1 1 R W R W Group 2 Compare Match Select 1 and 0 Select output trigger of pulse output group 2 00 Compare match in TPU channel 0...

Page 623: ...ing operation is selected PPG updates its output values at compare match A or B of the TPU that becomes the output trigger For details refer to section 12 4 4 Non Overlapping Pulse Output Bit Bit Name Initial Value R W Description 7 G3INV 1 R W Group 3 Inversion Selects direct output or inverted output for pulse output group 3 0 Inverted output 1 Direct output 6 G2INV 1 R W Group 2 Inversion Selec...

Page 624: ...match A in the selected TPU channel 1 Non overlapping operation output values updated at compare match A or B in the selected TPU channel 1 G1NOV 0 R W Group 1 Non Overlap Selects normal or non overlapping operation for pulse output group 1 0 Normal operation output values updated at compare match A in the selected TPU channel 1 Non overlapping operation output values updated at compare match A or...

Page 625: ...ponding PODR initial setting When the compare match event specified by PCR occurs the corresponding NDR bit contents are transferred to PODR to update the output values Sequential output of data of up to 16 bits is possible by writing new output data to NDR before the next compare match Output trigger signal Pulse output pin Internal data bus Normal output inverted output C PODR Q D NDER Q NDR Q D...

Page 626: ...output when the specified compare match event occurs Figure 12 3 shows the timing of these operations for the case of normal output in groups 2 and 3 triggered by compare match A TCNT N N 1 ø TGRA N Compare match A signal NDRH m n PODRH PO8 to PO15 n m n Figure 12 3 Timing of Transfer and Output of NDR Contents Example ...

Page 627: ...put compare register with output disabled 2 Set the PPG output trigger period 3 Select the counter clock source with bits TPSC2 to TPSC0 in TCR Select the counter clear source with bits CCLR2 to CCLR0 4 Enable the TGIA interrupt in TIER The DTC or DMAC can also be set up to transfer data to NDR 5 Set the initial output values in PODR 6 Set the DDR and NDER bits for the pins to be used for pulse ou...

Page 628: ...A bit in TIER to 1 to enable the compare match input capture A TGIA interrupt 2 Write H F8 in P1DDR and NDERH and set the G3CMS1 G3CMS0 G2CMS1 and G2CMS0 bits in PCR to select compare match in the TPU channel set up in the previous step to be the output trigger Write output data H 80 in NDRH 3 The timer counter in the TPU channel starts When compare match A occurs the NDRH contents are transferred...

Page 629: ...pin Internal data bus Normal output inverted output C PODR Q D NDER Q NDR Q D DDR Figure 12 6 Non Overlapping Pulse Output Therefore 0 data can be transferred ahead of 1 data by making compare match B occur before compare match A The NDR contents should not be altered during the interval from compare match B to compare match A the non overlap margin This can be accomplished by having the TGIA inte...

Page 630: ...tput Set non overlapping groups 2 3 4 5 6 7 8 9 10 11 1 Set TIOR to make TGRA and TGRB an output compare registers with output disabled 2 Set the pulse output trigger period in TGRB and the non overlap period in TGRA 3 Select the counter clock source with bits TPSC2 to TPSC0 in TCR Select the counter clear source with bits CCLR2 to CCLR0 4 Enable the TGIA interrupt in TIER The DTC or DMAC can also...

Page 631: ...ed as the output trigger channel so that TGRA and TGRB are output compare registers Set the trigger period in TGRB and the non overlap margin in TGRA and set the counter to be cleared by compare match B Set the TGIEA bit in TIER to 1 to enable the TGIA interrupt 2 Write H FF in P1DDR and NDERH and set the G3CMS1 G3CMS0 G2CMS1 and G2CMS0 bits in PCR to select compare match in the TPU channel set up...

Page 632: ...tivation by the TGIA interrupt pulse output can be obtained without imposing a load on the CPU 12 4 7 Inverted Pulse Output If the G3INV G2INV G1INV and G0INV bits in PMR are cleared to 0 values that are the inverse of the PODR contents can be output Figure 12 10 shows the outputs when G3INV and G2INV are cleared to 0 in addition to the settings of figure 12 9 TCNT value TCNT TGRB TGRA H 0000 NDRH...

Page 633: ...Stop Mode Setting PPG operation can be disabled or enabled using the module stop control register The initial value is for PPG operation to be halted Register access is enabled by clearing module stop mode For details refer to section 22 Power Down Modes 12 5 2 Operation of Pulse Output Pins Pins PO0 to PO15 are also used for other peripheral functions such as the TPU When output by another periph...

Page 634: ...Rev 1 0 09 01 page 590 of 904 ...

Page 635: ...n of three ways to clear the counters The counters can be cleared on compare match A or B or by an external reset signal Timer output control by a combination of two compare match signals The timer output signal in each channel is controlled by a combination of two independent compare match signals enabling the timer to generate output waveforms with an arbitrary duty cycle or PWM output Provision...

Page 636: ..._0 TCSR_0 Timer control status register_0 TCR_0 Timer control register_0 TCORA_1 Time constant register A_1 TCORB_1 Time constant register B_1 TCNT_1 Timer counter_1 TCSR_1 Timer control status register_1 TCR_1 Timer control register_1 TMO0 TMRI0 Internal bus TCORA_0 Comparator A_0 Comparator B_0 TCORB_0 TCSR_0 TCR_0 TCORA_1 Comparator A_1 TCNT_1 Comparator B_1 TCORB_1 TCSR_1 TCR_1 TMCI0 TMCI1 TCN...

Page 637: ...ter refer to section 21 1 2 Module Stop Control Registers H L MSTPCRH MSTPCRL Timer counter_0 TCNT_0 Time constant register A_0 TCORA_0 Time constant register B_0 TCORB_0 Timer control register_0 TCR_0 Timer control status register_0 TCSR_0 Timer counter_1 TCNT_1 Time constant register A_1 TCORA_1 Time constant register B_1 TCORB_1 Timer control register_1 TCR_1 Timer control status register_1 TCS...

Page 638: ...gs of bits OS1 and OS0 in TCSR TCORA is initialized to H FF 13 3 3 Time Constant Register B TCORB TCORB is 8 bit readable writable register TCORB_0 and TCORB_1 comprise a single 16 bit register so they can be accessed together by a word transfer instruction TCORB is continually compared with the value in TCNT When a match is detected the corresponding CMFB flag in TCSR is set to 1 Note however tha...

Page 639: ...nterrupt requests CMIA are disabled 1 CMFA interrupt requests CMIA are enabled 5 OVIE 0 R W Timer Overflow Interrupt Enable Selects whether OVF interrupt requests OVI are enabled or disabled when the OVF flag in TCSR is set to 1 0 OVF interrupt requests OVI are disabled 1 OVF interrupt requests OVI are enabled 4 3 CCLR1 CCLR0 0 0 R W R W Counter Clear 1 and 0 These bits select the method by which ...

Page 640: ... 0 Count at TCNT_0 compare match A All 1 0 1 External clock counted at rising edge 1 0 External clock counted at falling edge 1 1 External clock counted at both rising and falling edges Note If the count input of TMR_0 is the TCNT_1 overflow signal and that of TMR_1 is the TCNT_0 compare match signal no incrementing clock is generated Do not use this setting 13 3 5 Timer Control Status Register TC...

Page 641: ...leared by reading OVF when OVF 1 then writing 0 to OVF 4 ADTE 0 R W A D Trigger Enable Selects enabling or disabling of A D converter start requests by compare match A 0 A D converter start requests by compare match A are disabled 1 A D converter start requests by compare match A are enabled 3 2 OS3 OS2 0 0 R W R W Output Select 3 and 2 These bits select a method of TMO pin output when compare mat...

Page 642: ...t Bit Name Initial Value R W Description 7 CMFB 0 R W Compare Match Flag B Setting condition Set when TCNT matches TCORB Clearing conditions Cleared by reading CMFB when CMFB 1 then writing 0 to CMFB When DTC is activated by CMIB interrupt while DISEL bit of MRB in DTC is 0 6 CMFA 0 R W Compare Match Flag A Setting condition Set when TCNT matches TCORA Clearing conditions Cleared by reading CMFA w...

Page 643: ...ch A occurs 01 0 is output when compare match A occurs 10 1 is output when compare match A occurs 11 Output is inverted when compare match A occurs toggle output Note Only 0 can be written to bits 7 to 5 to clear these flags 13 4 Operation 13 4 1 Pulse Output Figure 13 2 shows an example that the 8 bit timer is used to generate a pulse output with a selected duty cycle The control bits are set as ...

Page 644: ...ck input Figure 13 4 shows the count timing for external clock signal Note that the external clock pulse width must be at least 1 5 states for incrementation at a single edge and at least 2 5 states for incrementation at both edges The counter will not increment correctly if the pulse width is less than these values ø Internal clock Clock input to TCNT TCNT N 1 N N 1 Figure 13 3 Count Timing for I...

Page 645: ...nerated at the last state in which the match is true just before the timer counter is updated Therefore when TCOR and TCNT match the compare match signal is not generated until the next incrementation clock input Figure 13 5 shows this timing ø TCNT N N 1 TCOR N Compare match signal CMF Figure 13 5 Timing of CMF Setting 13 5 3 Timing of Timer Output when Compare Match Occurs When compare match A o...

Page 646: ...g of the CCLR1 and CCLR0 bits in TCR Figure 13 7 shows the timing of this operation ø N H 00 Compare match signal TCNT Figure 13 7 Timing of Compare Match Clear 13 5 5 Timing of TCNT External Reset TCNT is cleared at the rising edge of an external reset input depending on the settings of the CCLR1 and CCLR0 bits in TCR The clear pulse width must be at least 1 5 states Figure 13 8 shows the timing ...

Page 647: ...eration with Cascaded Connection If bits CKS2 to CKS0 in either TCR_0 or TCR_1 are set to B 100 the 8 bit timers of the two channels are cascaded With this configuration a single 16 bit timer could be used 16 bit counter mode or compare matches of the 8 bit channel 0 could be counted by the timer of channel 1 compare match count mode In this case the timer operates as below 13 6 1 16 Bit Counter M...

Page 648: ...ccordance with the 16 bit compare match conditions Control of output from the TMO1 pin by bits OS3 to OS0 in TCSR_1 is in accordance with the lower 8 bit compare match conditions 13 6 2 Compare Match Count Mode When bits CKS2 to CKS0 in TCR_1 are B 100 TCNT_1 counts compare match A s for channel 0 Channels 0 and 1 are controlled independently Conditions such as setting of the CMF flag generation o...

Page 649: ... Possible High CMIB1 TCORB_1 compare match CMFB Possible OVI1 TCNT_1 overflow OVF Not possible Low 13 7 2 A D Converter Activation The A D converter can be activated only by TMR_0 compare match A If the ADTE bit in TCSR0 is set to 1 when the CMFA flag is set to 1 by the occurrence of TMR_0 compare match A a request to start A D conversion is sent to the A D converter If the 8 bit timer conversion ...

Page 650: ...rite is not performed Figure 13 10 shows this operation ø Address TCNT address Internal write signal Counter clear signal TCNT N H 00 T1 T2 TCNT write cycle by CPU Figure 13 10 Contention between TCNT Write and Clear 13 8 2 Contention between TCNT Write and Increment If a timer counter clock pulse is generated during the T2 state of a TCNT write cycle the write takes priority and the counter is no...

Page 651: ... cycle by CPU Counter write data Figure 13 11 Contention between TCNT Write and Increment 13 8 3 Contention between TCOR Write and Compare Match During the T2 state of a TCOR write cycle the TCOR write has priority and the compare match signal is inhibited even if a compare match event occurs as shown in figure 13 12 ...

Page 652: ...tween TCOR Write and Compare Match 13 8 4 Contention between Compare Matches A and B If compare match events A and B occur at the same time the 8 bit timer operates in accordance with the priorities for the output statuses set for compare match A and compare match B as shown in table 13 4 Table 13 4 Timer Output Priorities Output Setting Priority Toggle output High 1 output 0 output No change Low ...

Page 653: ...g to the CKS1 and CKS0 bits and the TCNT operation When the TCNT clock is generated from an internal clock the falling edge of the internal clock pulse is detected If clock switching causes a change from high to low level as shown in case 3 in table 13 5 a TCNT clock pulse is generated on the assumption that the switchover is a falling edge This increments TCNT The erroneous incrementation can als...

Page 654: ...eration 1 Switching from low to low 1 Clock before switchover Clock after switchover TCNT clock TCNT CKS bit write N N 1 2 Switching from low to high 2 Clock before switchover Clock after switchover TCNT clock TCNT CKS bit write N N 1 N 2 3 Switching from high to low 3 Clock before switchover Clock after switchover TCNT clock TCNT CKS bit write N N 1 N 2 4 ...

Page 655: ...he switchover is a falling edge TCNT is incremented 13 8 6 Mode Setting with Cascaded Connection If 16 bit counter mode and compare match count mode are specified at the same time input clocks for TCNT_0 and TCNT_1 are not generated and the counter stops Do not specify 16 bit counter and compare match count modes simultaneously 13 8 7 Interrupts in Module Stop Mode If module stop mode is entered w...

Page 656: ...Rev 1 0 09 01 page 612 of 904 ...

Page 657: ... be used as an interval timer In interval timer operation an interval timer interrupt is generated each time the counter overflows The block diagram of the WDT is shown in figure 14 1 14 1 Features Selectable from eight counter input clocks Switchable between watchdog timer mode and interval timer mode In watchdog timer mode If the counter overflows the WDT outputs 729 It is possible to select whe...

Page 658: ...atus register WDT Legend Internal bus Figure 14 1 Block Diagram of WDT 14 2 Input Output Pin Table 14 1 describes the WDT output pin Table 14 1 WDT Pin Name Symbol I O Function Watchdog timer overflow 729 Output Outputs counter overflow signal in watchdog timer mode 14 3 Register Descriptions The WDT has the following three registers To prevent accidental overwriting TCSR TCNT and RSTCSR have to b...

Page 659: ...er Counter TCNT TCNT is an 8 bit readable writable up counter TCNT is initialized to H 00 when the TME bit in TCSR is cleared to 0 14 3 2 Timer Control Status Register TCSR TCSR selects the clock source to be input to TCNT and the timer mode ...

Page 660: ...val timer 0 Interval timer mode When TCNT overflows an interval timer interrupt WOVI is requested 1 Watchdog timer mode When TCNT overflows the 729 signal is output 5 TME 0 R W Timer Enable When this bit is set to 1 TCNT starts counting When this bit is cleared TCNT stops counting and is initialized to H 00 4 3 1 1 Reserved These bits are always read as 1 and cannot be modified 2 1 0 CKS2 CKS1 CKS...

Page 661: ...flows in watchdog timer mode This bit cannot be set in interval timer mode and only 0 can be written Setting condition Set when TCNT overflows changed from H FF to H 00 in watchdog timer mode Clearing condition Cleared by reading RSTCSR when WOVF 1 and then writing 0 to WOVF 6 RSTE 0 R W Reset Enable Specifies whether or not a reset signal is generated in the chip if TCNT overflows during watchdog...

Page 662: ...hip internally in watchdog timer mode If TCNT overflows when 1 is set in the RSTE bit in RSTCSR a signal that resets this LSI internally is generated at the same time as the 729 signal If a reset caused by a signal input to the 5 6 pin occurs at the same time as a reset caused by a WDT overflow the 5 6 pin reset has priority and the WOVF bit in RSTCSR is cleared to 0 The 729 signal is output for 1...

Page 663: ...and internal reset are generated WOVF 1 Timer mode select bit Timer enable bit Legend Figure 14 2 Operation in Watchdog Timer Mode 14 4 2 Interval Timer Mode To use the WDT as an interval timer set the WT 7 bit to 0 and TME bit in TCSR to 1 When the WDT is used as an interval timer an interval timer interrupt WOVI is generated each time the TCNT overflows Therefore an interrupt can be generated at...

Page 664: ... Interrupt Source Interrupt Flag DTC Activation WOVI TCNT overflow OVF Impossible 14 6 Usage Notes 14 6 1 Notes on Register Access The watchdog timer s TCNT TCSR and RSTCSR registers differ from other registers in being more difficult to write to The procedures for writing to and reading these registers are given below Writing to TCNT TCSR and RSTCSR TCNT and TCSR must be written to by a word tran...

Page 665: ...of the lower byte into the RSTE bit but has no effect on the WOVF bit TCNT write or Writing to RSTE bit in RSTCSR TCSR write Address H FFBC TCNT H FFBE RSTCSR 15 8 7 0 H 5A Write data Address H FFBC TCSR 15 8 7 0 H A5 Write data Writing 0 to WOVF bit in RSTCSR Address H FFBE RSTCSR 15 8 7 0 H A5 H 00 Figure 14 4 Writing to TCNT TCSR and RSTCSR Reading TCNT TCSR and RSTCSR These registers are read ...

Page 666: ...de and Interval Timer Mode If the mode is switched from watchdog timer to interval timer while the WDT is operating errors could occur in the incrementation Software must stop the watchdog timer by clearing the TME bit to 0 before switching the mode 14 6 5 Internal Reset in Watchdog Timer Mode This LSI is not reset internally if TCNT overflows while the RSTE bit is cleared to 0 during watchdog tim...

Page 667: ...chip will not be initialized correctly Make sure that the 729 signal is not input logically to the 5 6 pin To reset the entire system by means of the 729 signal use the circuit shown in figure 14 6 Reset input Reset signal to entire system This LSI RES WDTOVF Figure 14 6 Circuit for System Reset by 729 729 729 729 Signal Example ...

Page 668: ...Rev 1 0 09 01 page 624 of 904 ...

Page 669: ... clocked synchronous serial communication mode Full duplex communication capability The transmitter and receiver are mutually independent enabling transmission and reception to be executed simultaneously Double buffering is used in both the transmitter and the receiver enabling continuous transmission and continuous reception of serial data On chip baud rate generator allows any bit rate to be sel...

Page 670: ...on 115 196 460 784 or 720 kbps at 16 MHz operation 720 kbps at 32 MHz operation Clocked Synchronous mode Data length 8 bits Receive error detection Overrun errors detected Smart Card Interface Automatic transmission of error signal parity error in receive mode Error signal detection and automatic data retransmission in transmit mode Direct convention and inverse convention both supported ...

Page 671: ...sfer rate generator SCI_2 10 667 MHz operation 115 152 kbps 460 606 kbps 16 MHz operation 115 196 kbps 460 784 kbps 720 kbps 32 MHz operation 720 kbps Legend RSR Receive shift register RDR Receive data register TSR Transmit shift register TDR Transmit data register SMR Serial mode register SCR Serial control register SSR Serial status register SCMR Smart card mode register BRR Bit rate register SE...

Page 672: ...ceive data input 3 TxD3 Output Channel 3 transmit data output SCK4 I O Channel 4 clock input output RxD4 Input Channel 4 receive data input 4 TxD4 Output Channel 4 transmit data output Note Pin names SCK RxD and TxD are used in the text for all channels omitting the channel designation 15 3 Register Descriptions The SCI has the following registers The serial mode register SMR serial status registe...

Page 673: ..._2 Serial mode register_2 SMR_2 Serial control register_2 SCR_2 Serial status register_2 SSR_2 Smart card mode register_2 SCMR_2 Bit rate register_2 BRR_2 Serial extension mode register_2 SEMR_2 Receive shift register_3 RSR_3 Transmit shift register_3 TSR_3 Receive data register_3 RDR_3 Transmit data register_3 TDR_3 Serial mode register_3 SMR_3 Serial control register_3 SCR_3 Serial status regist...

Page 674: ...that stores transmit data When the SCI detects that TSR is empty it transfers the transmit data written in TDR to TSR and starts transmission The double buffered structures of TDR and TSR enable continuous serial transmission If the next transmit data has already been written to TDR during serial transmission the SCI transfers the written data to TSR to continue transmission Although TDR can be re...

Page 675: ... data before transmission and the parity bit is checked in reception For a multiprocessor format parity bit addition and checking are not performed regardless of the PE bit setting 4 O 0 R W Parity Mode enabled only when the PE bit is 1 in asynchronous mode 0 Selects even parity 1 Selects odd parity 3 STOP 0 R W Stop Bit Length enabled only in asynchronous mode Selects the stop bit length in trans...

Page 676: ...of the TEND setting is advanced by 11 0 etu Elementary Time Unit the time for transfer of one bit and clock output control mode addition is performed For details refer to section 15 7 8 Clock Output Control 6 BLK 0 R W When this bit is set to 1 the SCI operates in block transfer mode For details on block transfer mode refer to section 15 7 3 Block Transfer Mode 5 PE 0 R W Parity Enable enabled onl...

Page 677: ...lect 1 and 0 These bits select the clock source for the on chip baud rate generator 00 ø clock n 0 01 ø 4 clock n 1 10 ø 16 clock n 2 11 ø 64 clock n 3 For the relation between the bit rate register setting and the baud rate see section 15 3 9 Bit Rate Register BRR n is the decimal display of the value of n in BRR see section 15 3 9 Bit Rate Register BRR 15 3 6 Serial Control Register SCR SCR perf...

Page 678: ...E 0 R W Transmit Enable When this bit s set to 1 transmission is enabled In this state serial transmission is started when transmit data is written to TDR and the TDRE flag in SSR is cleared to 0 SMR setting must be performed to decide the transfer format before setting the TE bit to 1 The TDRE flag in SSR is fixed at 1 if transmission is disabled by clearing this bit to 0 4 RE 0 R W Receive Enabl...

Page 679: ... SSR i s sett o 1 t he M PI E bi ti s cl ear ed t o 0 aut om at i cal l y and gener at i on ofRXI and ERIi nt er r upt s when t he TI E and RI E bi t s i n SCR ar e sett o 1 and FER and O RER f l ag set t i ng i s enabl ed 2 TEIE 0 R W Transmit End Interrupt Enable When this bit is set to 1 TEI interrupt request is enabled TEIcancel l at i on can be per f or m ed by r eadi ng 1 f r om t he TDRE f ...

Page 680: ... serial transmission is started when transmit data is written to TDR and the TDRE flag in SSR is cleared to 0 SMR setting must be performed to decide the transfer format before setting the TE bit to 1 The TDRE flag in SSR is fixed at 1 if transmission is disabled by clearing this bit to 0 4 RE 0 R W Receive Enable When this bit is set to 1 reception is enabled Ser i alr ecept i on i s st ar t ed i...

Page 681: ... and 0 Enables or disables clock output from the SCK pin The clock output can be dynamically switched in GSM mode For details refer to section 15 7 8 Clock Output Control When the GM bit in SMR is 0 00 Output disabled SCK pin can be used as an I O port pin 01 Clock output 1X Reserved When the GM bit in SMR is 1 00 Output fixed low 01 Clock output 10 Output fixed high 11 Clock output Note X Don t c...

Page 682: ...sferred from TDR to TSR and data writing to TDR is enabled Clearing conditions When 0 is written to TDRE after reading TDRE 1 When the DMAC or DTC is activated by a TXI interrupt request and transfers data to TDR 6 RDRF 0 R W Receive Data Register Full Indicates that the received data is stored in RDR Setting condition When serial reception ends normally and receive data is transferred from RSR to...

Page 683: ...mpleted while RDRF 1 The receive data prior to the overrun error is retained in RDR and the data received subsequently is lost Also subsequent serial reception cannot be continued while the ORER flag is set to 1 In clocked synchronous mode serial transmission cannot be continued either Clearing condition When 0 is written to ORER after reading ORER 1 The ORER flag is not affected and retains its p...

Page 684: ... f ora val ue of0 t he second st op bi ti s not checked I fa f r am i ng er r oroccur s t he r ecei ve dat a i s t r ansf er r ed t o RDR butt he RDRF f l ag i s notset Al so subsequentser i alr ecept i on cannot be cont i nued whi l e t he FER f l ag i s sett o 1 I n cl ocked synchr onous m ode ser i alt r ansm i ssi on cannotbe cont i nued ei t her Cl ear i ng condi t i on When 0 is written to F...

Page 685: ... t her Clearing condition When 0 is written to PER after reading PER 1 The PER flag is not affected and retains its previous state when the RE bit in SCR is cleared to 0 2 TEND 1 R Transmit End Setting conditions When the TE bit in SCR is 0 When TDRE 1 at transmission of the last bit of a 1 byte serial transmit character Clearing conditions When 0 is written to TDRE after reading TDRE 1 When the D...

Page 686: ...XI interrupt request and transfers data to TDR 6 RDRF 0 R W Receive Data Register Full Indicates that the received data is stored in RDR Setting condition When serial reception ends normally and receive data is transferred from RSR to RDR Clearing conditions When 0 is written to RDRF after reading RDRF 1 When the DMAC or DTC is activated by an RXI interrupt and transferred data from RDR The RDRF f...

Page 687: ... and the data received subsequently is lost Also subsequent serial reception cannot be continued while the ORER flag is set to 1 In clocked synchronous mode serial transmission cannot be continued either Clearing condition When 0 is written to ORER after reading ORER 1 The ORER flag is not affected and retains its previous state when the RE bit in SCR is cleared to 0 4 ERS 0 R W Error Signal Statu...

Page 688: ...tbe cont i nued ei t her Clearing condition When 0 is written to PER after reading PER 1 The PER flag is not affected and retains its previous state when the RE bit in SCR is cleared to 0 2 TEND 1 R Transmit End This bit is set to 1 when no error signal has been sent back from the receiving end and the next transmit data is ready to be transferred to TDR Setting conditions When the TE bit in SCR i...

Page 689: ...tial Value R W Description 7 to 4 1 Reserved These bits are always read as 1 3 SDIR 0 R W Smart Card Data Transfer Direction Selects the serial parallel conversion format 0 LSB first in transfer 1 MSB first in transfer The bit setting is valid only when the transfer data format is 8 bits For 7 bit data LSB first is fixed 2 SINV 0 R W Smart Card Data Invert Specifies inversion of the data logic lev...

Page 690: ... BRR and bit rate B for normal asynchronous mode clocked synchronous mode and Smart Card interface mode The initial value of BRR is H FF and it can be read or written to by the CPU at all times Table 15 2 Relationships between N Setting in BRR and Bit Rate B Mode Bit Rate Error Asynchronous Mode B 64 2 2n 1 N 1 ø 106 Error B 64 2 2n 1 N 1 1 100 ø 106 Clocked Synchronous Mode B 8 2 2n 1 N 1 ø 106 S...

Page 691: ...ng Timing and Reception Margin Tables 15 5 and 15 7 show the maximum bit rates with external clock input Table 15 3 BRR Settings for Various Bit Rates Asynchronous Mode 1 Operating Frequency ø MHz 2 2 097152 2 4576 3 Bit Rate bit s n N Error n N Error n N Error n N Error 110 1 141 0 03 1 148 0 04 1 174 0 26 1 212 0 03 150 1 103 0 16 1 108 0 21 1 127 0 00 1 155 0 16 300 0 207 0 16 0 217 0 21 0 255 ...

Page 692: ...600 0 11 0 00 0 12 0 16 0 15 0 00 0 15 1 73 19200 0 5 0 00 0 7 0 00 0 7 1 73 31250 0 3 0 00 0 4 1 70 0 4 0 00 38400 0 2 0 00 0 3 0 00 0 3 1 73 Operating Frequency ø MHz 6 6 144 7 3728 8 Bit Rate bit s n N Error n N Error n N Error n N Error 110 2 106 0 44 2 108 0 08 2 130 0 07 2 141 0 03 150 2 77 0 16 2 79 0 00 2 95 0 00 2 103 0 16 300 1 155 0 16 1 159 0 00 1 191 0 00 1 207 0 16 600 1 77 0 16 1 79...

Page 693: ...38 0 16 0 39 0 00 19200 0 15 0 00 0 15 1 73 0 19 2 34 0 19 0 00 31250 0 9 1 70 0 9 0 00 0 11 0 00 0 11 2 40 38400 0 7 0 00 0 7 1 73 0 9 2 34 0 9 0 00 Operating Frequency ø MHz 14 14 7456 16 17 2032 Bit Rate bit s n N Error n N Error n N Error n N Error 110 2 248 0 17 3 64 0 70 3 70 0 03 3 75 0 48 150 2 181 0 16 2 191 0 00 2 207 0 16 2 223 0 00 300 2 90 0 16 2 95 0 00 2 103 0 16 2 111 0 00 600 1 18...

Page 694: ...5 2400 0 233 0 16 0 255 0 00 1 64 0 16 1 80 0 47 4800 0 116 0 16 0 127 0 00 0 129 0 16 0 162 0 15 9600 0 58 0 69 0 63 0 00 0 64 0 16 0 80 0 47 19200 0 28 1 02 0 31 0 00 0 32 1 36 0 40 0 76 31250 0 17 0 00 0 19 1 70 0 19 0 00 0 24 0 00 38400 0 14 2 34 0 15 0 00 0 15 1 73 0 19 1 73 Operating Frequency ø MHz 30 33 Bit Rate bit s n N Error n N Error 110 3 132 0 13 3 145 0 33 150 3 97 0 35 3 106 0 39 3...

Page 695: ...0000 0 0 30 937500 0 0 9 8304 307200 0 0 33 1031250 0 0 Table 15 5 Maximum Bit Rate with External Clock Input Asynchronous Mode ø MHz External Input Clock MHz Maximum Bit Rate bit s ø MHz External Input Clock MHz Maximum Bit Rate bit s 2 0 5000 31250 10 2 5000 156250 2 097152 0 5243 32768 12 3 0000 187500 2 4576 0 6144 38400 12 288 3 0720 192000 3 0 7500 46875 14 3 5000 218750 3 6864 0 9216 57600 ...

Page 696: ... 500 1 249 2 124 2 249 3 124 1 k 1 124 1 249 2 124 2 249 3 97 2 5 k 0 199 1 99 1 199 1 249 2 99 2 124 2 155 5 k 0 99 0 199 1 99 1 124 1 199 1 249 2 77 10 k 0 49 0 99 0 199 0 249 1 99 1 124 1 155 25 k 0 19 0 39 0 79 0 99 0 159 0 199 0 249 50 k 0 9 0 19 0 39 0 49 0 79 0 99 0 124 100 k 0 4 0 9 0 19 0 24 0 39 0 49 0 62 250 k 0 1 0 3 0 7 0 9 0 15 0 19 0 24 500 k 0 0 0 1 0 3 0 4 0 7 0 9 1 M 0 0 0 1 0 3 ...

Page 697: ...here will be a degree of error Continuous transfer is not possible Table 15 7 Maximum Bit Rate with External Clock Input Clocked Synchronous Mode ø MHz External Input Clock MHz Maximum Bit Rate bit s ø MHz External Input Clock MHz Maximum Bit Rate bit s 2 0 3333 333333 3 16 2 6667 2666666 7 4 0 6667 666666 7 18 3 0000 3000000 0 6 1 0000 1000000 0 20 3 3333 3333333 3 8 1 3333 1333333 3 25 4 1667 41...

Page 698: ...t s n N Error n N Error n N Error n N Error 9600 0 1 0 00 0 1 12 01 0 2 15 99 0 2 6 60 Operating Frequency ø MHz 25 00 30 00 33 00 Bit Rate bit s n N Error n N Error n N Error 9600 0 3 12 49 0 3 5 01 0 4 7 59 Table 15 9 Maximum Bit Rate at Various Frequencies Smart Card Interface Mode when S 372 ø MHz Maximum Bit Rate bit s n N ø MHz Maximum Bit Rate bit s n N 7 1424 9600 0 0 18 00 24194 0 0 10 00...

Page 699: ...D0 1 Pins TxD0 IrTxD and RxD0 IrRxD function as IrTxD and IrRxD 6 5 4 IrCKS2 IrCKS1 IrCKS0 0 0 0 R W R W R W IrDA Clock Select 2 to 0 Specifies the high pulse width in IrTxD output pulse encoding when the IrDA function is enabled 000 Pulse width B 3 16 3 16 of bit rate 001 Pulse width ø 2 010 Pulse width ø 4 011 Pulse width ø 8 100 Pulse width ø 16 101 Pulse width ø 32 110 Pulse width ø 64 111 Pul...

Page 700: ...ial Value R W Description 7 to 4 Undefined Reserved If these bits are read an undefined value will be returned and cannot be modified 3 ABCS 0 R W Asynchronous basic clock selection valid only in asynchronous mode Selects the basic clock for 1 bit period in asynchronous mode 0 Operates on a basic clock with a frequency of 16 times the transfer rate 1 Operates on a basic clock with a frequency of 8...

Page 701: ...10 667 MHz Operates on a basic clock with a frequency of 8 times the transfer rate 011 Selects 720 kbps which is the average transfer rate dedicated for φ 32 MHz Operates on a basic clock with a frequency of 16 times the transfer rate 100 Reserved 101 Selects 115 196 kbps which is the average transfer rate dedicated for φ 16 MHz Operates on a basic clock with a frequency of 16 times the transfer r...

Page 702: ...t and starts serial communication Inside the SCI the transmitter and receiver are independent units enabling full duplex communication Both the transmitter and the receiver also have a double buffered structure so that data can be read or written during transmission or reception enabling continuous data transfer LSB Start bit MSB Idle state mark state Stop bit s 0 Transmit receive data D0 D1 D2 D3...

Page 703: ...S 8 bit data MPB STOP S 8 bit data MPB STOP STOP S 7 bit data STOP MPB S 7 bit data STOP MPB STOP S 7 bit data STOP STOP CHR 0 0 0 0 1 1 1 1 0 0 1 1 MP 0 0 0 0 0 0 0 0 1 1 1 1 STOP 0 1 0 1 0 1 0 1 0 1 0 1 SMR Settings 1 2 3 4 5 6 7 8 9 10 11 12 Serial Transfer Format and Frame Length STOP S 8 bit data P STOP S 7 bit data STOP P STOP Legend S Start bit STOP Stop bit P Parity bit MPB Multiprocessor ...

Page 704: ... the reception margin in asynchronous mode is given by formula 1 below M 0 5 L 0 5 F 1 F 100 1 2N D 0 5 N Formula 1 Where M Reception Margin N Ratio of bit rate to clock N 16 D Clock duty D 0 5 to 1 0 L Frame length L 9 to 12 F Absolute value of clock rate deviation Assuming values of F 0 and D 0 5 in formula 1 a reception margin is given by formula below M 0 5 1 2 16 100 46 875 However this is on...

Page 705: ...lock is input at the SCK pin the clock frequency should be 16 times the bit rate used When the SCI is operated on an internal clock the clock can be output from the SCK pin The frequency of the clock output in this case is equal to the bit rate and the phase is such that the rising edge of the clock is in the middle of the transmit data as shown in figure 15 4 0 1 frame SCK TxD D0 D1 D2 D3 D4 D5 D...

Page 706: ... completed Start of initialization Set data transfer format in SMR and SCMR 1 Set CKE1 and CKE0 bits in SCR TE RE bits 0 No Yes Set value in BRR Clear TE and RE bits in SCR to 0 2 3 Set TE and RE bits in SCR to 1 and set RIE TIE TEIE and MPIE bits 4 1 bit interval elapsed 1 Set the clock selection in SCR Be sure to clear bits RIE TIE TEIE and MPIE and bits TE and RE to 0 When the clock is selected...

Page 707: ... multiprocessor bit may be omitted depending on the format and stop bit 4 The SCI checks the TDRE flag at the timing for sending the stop bit 5 If the TDRE flag is 0 the data is transferred from TDR to TSR the stop bit is sent and then serial transmission of the next frame is started 6 If the TDRE flag is 1 the TEND flag in SSR is set to 1 the stop bit is sent and then the mark state is entered in...

Page 708: ... data write Read SSR and check that the TDRE flag is set to 1 then write transmit data to TDR and clear the TDRE flag to 0 3 Serial transmission continuation procedure To continue serial transmission read 1 from the TDRE flag to confirm that writing is possible then write data to TDR and then clear the TDRE flag to 0 Checking and clearing of the TDRE flag is automatic when the DMAC or DTC is activ...

Page 709: ...1 and receive data is transferred to RDR If the RIE bit in SCR is set to 1 at this time an ERI interrupt request is generated 5 If reception finishes successfully the RDRF bit in SSR is set to 1 and receive data is transferred to RDR If the RIE bit in SCR is set to 1 at this time an RXI interrupt request is generated Because the RXI interrupt routine reads the receive data transferred to RDR befor...

Page 710: ...tus Flag RDRF ORER FER PER Receive Data Receive Error Type 1 1 0 0 Lost Overrun error 0 0 1 0 Transferred to RDR Framing error 0 0 0 1 Transferred to RDR Parity error 1 1 1 0 Lost Overrun error framing error 1 1 0 1 Lost Overrun error parity error 0 0 1 1 Transferred to RDR Framing error parity error 1 1 1 1 Lost Overrun error framing error parity error Note The RDRF flag retains its state before ...

Page 711: ...ER PER and FER flags are all cleared to 0 Reception cannot be resumed if any of these flags are set to 1 In the case of a framing error a break can be detected by reading the value of the input port corresponding to the RxD pin SCI status check and receive data read Read SSR and check that RDRF 1 then read the receive data in RDR and clear the RDRF flag to 0 Transition of the RDRF flag from 0 to 1...

Page 712: ...ndling Parity error handling Yes No Clear ORER PER and FER flags in SSR to 0 No Yes No Yes Framing error handling No Yes Overrun error handling ORER 1 FER 1 Break PER 1 Clear RE bit in SCR to 0 Figure 15 9 Sample Serial Reception Data Flowchart 2 ...

Page 713: ...tion first sends communication data with a 1 multiprocessor bit added to the ID code of the receiving station It then sends transmit data as data with a 0 multiprocessor bit added When data with a 1 multiprocessor bit is received the receiving station compares that data with its own ID The station whose ID matches then receives the data sent next Stations whose ID does not match continue to skip d...

Page 714: ...n D ID 04 Serial communication line Serial data ID transmission cycle receiving station specification Data transmission cycle data transmission to receiving station specified by ID MPB 1 MPB 0 H 01 H AA Legend MPB Multiprocessor bit Figure 15 10 Example of Communication Using Multiprocessor Format Transmission of Data H AA to Receiving Station A ...

Page 715: ...ows a sample flowchart for multiprocessor serial data transmission For an ID transmission cycle set the MPBT bit in SSR to 1 before transmission For a data transmission cycle clear the MPBT bit in SSR to 0 before transmission All other SCI operations are the same as those in asynchronous mode ...

Page 716: ...ead SSR and check that the TDRE flag is set to 1 then write transmit data to TDR Set the MPBT bit in SSR to 0 or 1 Finally clear the TDRE flag to 0 Serial transmission continuation procedure To continue serial transmission be sure to read 1 from the TDRE flag to confirm that writing is possible then write data to TDR and then clear the TDRE flag to 0 Checking and clearing of the TDRE flag is autom...

Page 717: ... request multiprocessor interrupt generated MPIE 0 Idle state mark state RDRF RDR data read and RDRF flag cleared to 0 in RXI interrupt handling routine If not this station s ID MPIE bit is set to 1 again RXI interrupt request is not generated and RDR retains its state ID1 a Data does not match station s ID MPIE RDR value 0 D0 D1 D7 1 1 0 D0 D1 D7 0 1 1 1 Data ID2 Start bit MPB Stop bit Start bit ...

Page 718: ...nd check that the RDRF flag is set to 1 then read the receive data in RDR and compare it with this station s ID If the data is not this station s ID set the MPIE bit to 1 again and clear the RDRF flag to 0 If the data is this station s ID clear the RDRF flag to 0 SCI status check and data reception Read SSR and check that the RDRF flag is set to 1 then read the data in RDR Receive error handling a...

Page 719: ...d Error handling Yes No Clear ORER PER and FER flags in SSR to 0 No Yes No Yes Framing error handling Overrun error handling ORER 1 FER 1 Break Clear RE bit in SCR to 0 5 Figure 15 13 Sample Multiprocessor Serial Reception Flowchart 2 ...

Page 720: ...pendent units enabling full duplex communication by use of a common clock Both the transmitter and the receiver also have a double buffered structure so that data can be read or written during transmission or reception enabling continuous data transfer Don t care Don t care One unit of transfer data character or frame Bit 0 Serial data Serial clock Bit 1 Bit 3 Bit 4 Bit 5 LSB MSB Bit 2 Bit 6 Bit 7...

Page 721: ...r format in SMR and SCMR No Yes Set value in BRR Clear TE and RE bits in SCR to 0 2 3 Set TE and RE bits in SCR to 1 and set RIE TIE TEIE and MPIE bits Note In simultaneous transmit and receive operations the TE and RE bits should both be cleared to 0 or set to 1 simultaneously 4 1 bit interval elapsed Set CKE1 and CKE0 bits in SCR TE RE bits 0 1 1 Set the clock selection in SCR Be sure to clear b...

Page 722: ...ent from the TxD pin synchronized with the output clock when output clock mode has been specified and synchronized with the input clock when use of an external clock has been specified 4 The SCI checks the TDRE flag at the timing for sending the MSB 5 If the TDRE flag is cleared to 0 data is transferred from TDR to TSR and serial transmission of the next frame is started 6 If the TDRE flag is set ...

Page 723: ... TEND Bit 1 Bit 7 Bit 0 Bit 1 Bit 7 Bit 6 Data written to TDR and TDRE flag cleared to 0 in TXI interrupt handling routine TEI interrupt request generated TXI interrupt request generated TXI interrupt request generated Figure 15 16 Sample SCI Transmission Operation in Clocked Synchronous Mode ...

Page 724: ...tatus check and transmit data write Read SSR and check that the TDRE flag is set to 1 then write transmit data to TDR and clear the TDRE flag to 0 3 Serial transmission continuation procedure To continue serial transmission be sure to read 1 from the TDRE flag to confirm that writing is possible then write data to TDR and then clear the TDRE flag to 0 Checking and clearing of the TDRE flag is auto...

Page 725: ...o 1 3 If reception finishes successfully the RDRF bit in SSR is set to 1 and receive data is transferred to RDR If the RIE bit in SCR is set to 1 at this time an RXI interrupt request is generated Because the RXI interrupt routine reads the receive data transferred to RDR before reception of the next receive data has finished continuous reception can be enabled Bit 7 Serial data Serial clock 1 fra...

Page 726: ...nsfer cannot be resumed if the ORER flag is set to 1 SCI status check and receive data read Read SSR and check that the RDRF flag is set to 1 then read the receive data in RDR and clear the RDRF flag to 0 Transition of the RDRF flag from 0 to 1 can also be identified by an RXI interrupt Serial reception continuation procedure To continue serial reception before the MSB bit 7 of the current frame i...

Page 727: ...zed To switch from transmit mode to simultaneous transmit and receive mode after checking that the SCI has finished transmission and the TDRE and TEND flags are set to 1 clear TE to 0 Then simultaneously set TE and RE to 1 with a single instruction To switch from receive mode to simultaneous transmit and receive mode after checking that the SCI has finished reception clear RE to 0 Then after check...

Page 728: ...ng If a receive error occurs read the ORER flag in SSR and after performing the appropriate error handling clear the ORER flag to 0 Transmission reception cannot be resumed if the ORER flag is set to 1 SCI status check and receive data read Read SSR and check that the RDRF flag is set to 1 then read the receive data in RDR and clear the RDRF flag to 0 Transition of the RDRF flag from 0 to 1 can al...

Page 729: ...n is possible enabling self diagnosis to be carried out When the clock generated on the SCI is used by an IC card the SCK pin output is input to the CLK pin of the IC card This LSI port output is used as the reset signal TxD RxD This LSI VCC I O Connected equipment IC card Data line CLK RST SCK Rx port Clock line Reset line Figure 15 21 Schematic Diagram of Smart Card Interface Pin Connections 15 ...

Page 730: ...level to state A and transfer is performed in LSB first order The start character data above is H 3B For the direct convention type clear the SDIR and SINV bits in SCMR to 0 According to the Smart Card regulations clear the O bit in SMR to 0 to select even parity mode Ds A Z Z A A A Z A A A Z Z State D7 D6 D5 D4 D3 D2 D1 D0 Dp Figure 15 24 Inverse Convention SDIR SINV O 1 With the inverse conventi...

Page 731: ...ng and Reception Margin Only the internal clock generated by the on chip baud rate generator is used as transmit receive clock in Smart Card interface In Smart Card interface mode the SCI operates on a basic clock with a frequency of 32 64 372 or 256 times the bit rate fixed at 16 times in normal asynchronous mode as determined by bits BCP1 and BCP0 In reception the SCI samples the falling edge of...

Page 732: ...1 the TxD and RxD pins are both switched from ports to SCI pins and are placed in the high impedance state 5 Set the value corresponding to the bit rate in BRR 6 Set the CKE0 and CKE1 bits in SCR Clear the TIE RIE TE RE MPIE and TEIE bits to 0 If the CKE0 bit is set to 1 the clock is output from the SCK pin 7 Wait at least one bit interval then set the TIE RIE TE and RE bits in SCR Do not set the ...

Page 733: ...owchart for transmission The sequence of transmit operations can be performed automatically by specifying the DTC or DMAC to be activated with a TXI interrupt source In a transmit operation the TDRE flag is also set to 1 at the same time as the TEND flag in SSR and a TXI interrupt will be generated if the TIE bit in SCR has been set to 1 If the TXI request is designated beforehand as a DTC or DMAC...

Page 734: ... TSR from TDR 7 9 8 Figure 15 26 Retransfer Operation in SCI Transmit Mode The timing for setting the TEND flag depends on the value of the GM bit in SMR The TEND flag generation timing is shown in figure 15 27 Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp I O data 12 5etu TXI TEND interrupt 11 0etu DE Guard time When GM 0 When GM 1 Start bit Data bits Parity bit Error signal Legend Ds D0 to D7 Dp DE Figure 15 27...

Page 735: ...ear TE bit to 0 Start transmission Start No No No Yes Yes Yes Yes No End Write data to TDR and clear TDRE flag in SSR to 0 Error processing Error processing TEND 1 All data transmitted TEND 1 ERS 0 ERS 0 Figure 15 28 Example of Transmission Processing Flow ...

Page 736: ...DMAC to be activated with an RXI interrupt source In a receive operation an RXI interrupt request is generated when the RDRF flag in SSR is set to 1 If the RXI request is designated beforehand as a DTC or DMAC activation source the DTC or DMAC will be activated by the RXI request and transfer of the receive data will be carried out The RDRF flag is cleared to 0 automatically when data transfer is ...

Page 737: ...w 15 7 8 Clock Output Control When the GM bit in SMR is set to 1 the clock output level can be fixed with bits CKE1 and CKE0 in SCR At this time the minimum clock pulse width can be made the specified width Figure 15 31 shows the timing for fixing the clock output level In this example GM is set to 1 CKE1 is cleared to 0 and the CKE0 bit is controlled Specified pulse width SCK CKE0 Specified pulse...

Page 738: ...e data register DR and data direction register DDR corresponding to the SCK pin to the value for the fixed output state in software standby mode 2 Write 0 to the TE bit and RE bit in the serial control register SCR to halt transmit receive operation At the same time set the CKE1 bit to the value for the fixed output state in software standby mode 3 Write 0 to the CKE0 bit in SCR to halt the clock ...

Page 739: ...varying the transfer rate automatically the transfer rate setting must be changed by software Figure 15 33 shows a block diagram of the IrDA function IrDA Pulse encoder Pulse decoder TxD0 IrTxD RxD0 IrRxD SCI0 TxD RxD IrCR Figure 15 33 Block Diagram of IrDA Transmission In transmission the output signal UART frame from the SCI is converted to an IR frame by the IrDA interface see figure 15 34 When...

Page 740: ...ta is converted to a UART frame by the IrDA interface and input to the SCI When a high pulse is detected 0 data is output and if there is no pulse during a one bit interval 1 data is output Note that a pulse shorter than the minimum pulse width of 1 41 µs will be identified as a 0 signal High Pulse Width Selection Table 15 12 shows possible settings for bits IrCKS2 to IrCKS0 minimum pulse width an...

Page 741: ... 5 011 011 011 011 011 011 6 100 100 100 100 100 100 6 144 100 100 100 100 100 100 7 3728 100 100 100 100 100 100 8 100 100 100 100 100 100 9 8304 100 100 100 100 100 100 10 100 100 100 100 100 100 12 101 101 101 101 101 101 12 288 101 101 101 101 101 101 14 101 101 101 101 101 101 14 7456 101 101 101 101 101 101 16 101 101 101 101 101 101 16 9344 101 101 101 101 101 101 17 2032 101 101 101 101 10...

Page 742: ...flag is cleared to 0 automatically when data transfer is performed by the DTC or DMAC When the RDRF flag in SSR is set to 1 an RXI interrupt request is generated When the ORER PER or FER flag in SSR is set to 1 an ERI interrupt request is generated An RXI interrupt request can activate the DTC or DMAC to perform data transfer The RDRF flag is cleared to 0 automatically when data transfer is perfor...

Page 743: ... Not possible Not possible RXI2 Receive Data Full RDRF Possible Not possible TXI2 Transmit Data Empty TDRE Possible Not possible 2 TEI2 Transmission End TEND Not possible Not possible ERI3 Receive Error ORER FER PER Not possible Not possible RXI3 Receive Data Full RDRF Possible Not possible TXI3 Transmit Data Empty TDRE Possible Not possible 3 TEI3 Transmission End TEND Not possible Not possible E...

Page 744: ...ed If the TXI request is designated beforehand as a DTC or DMAC activation source the DTC or DMAC will be activated by the TXI request and transfer of the transmit data will be carried out The TDRE and TEND flags are automatically cleared to 0 when data transfer is performed by the DTC or DMAC In the event of an error the SCI retransmits the same data automatically During this period the TEND flag...

Page 745: ...on input or output and level are determined by DR and DDR This can be used to set the TxD pin to mark state or send a break during serial data transmission To maintain the communication line at mark state until TE is set to 1 set both PCR and PDR to 1 Since TE is cleared to 0 at this point the TxD pin becomes an I O port and 1 is output from the TxD pin To send a break during serial transmission f...

Page 746: ...g on an external clock set t 4 clocks TDRE Figure 15 35 Example of Synchronous Transmission Using DTC 15 10 7 Operation in Case of Mode Transition Transmission Operation should be stopped by clearing TE TIE and TEIE to 0 before making a module stop mode or software standby mode transition TSR TDR and SSR are reset The output pin states in module stop mode or software standby mode depend on the por...

Page 747: ... set the TXI flag and start DTC transmission Reception Receive operation should be stopped by clearing RE to 0 before making a module stop mode or software standby mode transition RSR RDR and SSR are reset If a transition is made during reception the data being received will be invalid To continue receiving without changing the reception mode after the relevant mode is cleared set RE to 1 before s...

Page 748: ...Initialization Start of transmission 1 Data being transmitted is interrupted After exiting software standby mode normal CPU transmission is possible by setting TE to 1 reading SSR writing TDR and clearing TDRE to 0 but note that if the DTC has been activated the remaining data in DTCRAM will be transmitted when TE and TIE are set to 1 2 If TIE and TEIE are set to 1 clear them to 0 in the same way ...

Page 749: ...Figure 15 37 Port Pin States during Mode Transition Internal Clock Asynchronous Transmission Port input output Last TxD bit held High output Port input output Marking output Port input output SCI TxD output Port Port Note Initialized by software standby SCK output pin TE bit TxD output pin SCI TxD output Start of transmission End of transmission Transition to software standby Exit from software st...

Page 750: ...RDR Read RDRF flag in SSR Exit from software standby mode Change operating mode No RDRF 1 Yes Yes Reception No 1 2 RE 1 Initialization Start of reception 1 Receive data being received becomes invalid 2 Includes module stop mode Figure 15 39 Sample Flowchart for Mode Transition during Reception ...

Page 751: ...s interface2 Figure 21 2 shows an example of I O pin connections to external circuits 16 1 Features Continuous transmission reception Since the shift register transmit data register and receive data register are independent from each other the continuous transmission reception can be performed Start and stop conditions generated automatically in master mode Selection of acknowledge output levels w...

Page 752: ...ransmission reception control circuit ICCRB ICMR ICSR ICEIR ICDRR ICDRS ICDRT I2 C bus control register A I2 C bus control register B I2 C mode register I2 C status register I2 C interrupt permission register I2 C transmission data register I2 C reception data register I2 C bus shift register Slave address register Legend ICCRA ICCRB ICMR ICSR ICIER ICDRT ICDRR ICDRS SAR SAR SDA Internal data bus ...

Page 753: ...nput output Serial data SDA0 I O IIC2_0 serial data input output Serial clock SCL1 I O IIC2_1 serial clock input output Serial data SDA1 I O IIC2_1 serial data input output Note The pin symbols are represented as SCL and SDA channel numbers are omitted in this manual 16 3 Register Descriptions The I 2 C bus interface has the following registers For details on register addresses and register states...

Page 754: ...er_1 ICMR_1 I 2 C bus interrupt enable register_1 ICIER_1 I 2 C bus status register_1 ICSR_1 I 2 C bus slave address register_1 SAR_1 I 2 C bus transmit data register_1 ICDRT_1 I 2 C bus receive data register_1 ICDRR_1 I 2 C bus shift register_1 ICDRS_1 16 3 1 I 2 C Bus Control Register A ICCRA ICCRA is an 8 bit readable writable register that enables or disables the I 2 C bus interface controls t...

Page 755: ...lave Select Transmit Receive Select When arbitration is lost in master mode MST and TRS are both reset by hardware causing a transition to slave receive mode Modification of the TRS bit should be made between transfer frames Operating modes are described below according to MST and TRS combination 00 Slave receive mode 01 Slave transmit mode 10 Master receive mode 11 Master transmit mode 3 2 1 0 CK...

Page 756: ... φ 224 35 7kHz 44 6kHz 89 3kHz 112kHz 147kHz 1 1 1 1 φ 256 31 3kHz 39 1kHz 78 1kHz 97 7kHz 129kHz 16 3 2 I 2 C Bus Control Register B ICCRB ICCRB is an 8 bit readable writable register that issues start stop conditions manipulates the SDA pin monitors the SCL pin and controls reset in I 2 C control Bit Bit Name Initial Value R W Description 7 BBSY 0 R W Bus Busy This bit enables to confirm whether...

Page 757: ...ays be 1 4 1 R W Reserved The write value must always be 1 3 SCLO 1 R This bit monitors SCL output level When reading and SCLO is 1 SCL pin outputs high When reading and SCLO is 0 SCL pin outputs low 2 1 Reserved This bit is always read as 1 1 IICRST 0 R W IIC control part reset This bit resets control parts except for I 2 C registers If this bit is set to 1 when hang up is occurred because of com...

Page 758: ... low period is extended for two transfer clocks If WAIT is cleared to 0 data and acknowledge bits are transferred consecutively with no wait inserted The setting of this bit is invalid in slave mode 5 4 1 1 Reserved These bits are always read as 1 3 BCWP 1 R W BC Write Protect This bit controls the BC2 to BC0 modifications When modifying BC2 to BC0 this bit should be cleared to 0 and use the MOV i...

Page 759: ...101 6 110 7 111 8 16 3 4 I 2 C Bus Interrupt Enable Register ICIER ICIER is an 8 bit readable writable register that enables or disables interrupt sources and acknowledge bits sets acknowledge bits to be transferred and confirms acknowledge bits to be received Bit Bit Name Initial Value R W Description 7 TIE 0 R W Transmit Interrupt Enable When the TDRE bit in ICSR is set to 1 this bit enables or ...

Page 760: ...0 0 NACK receive interrupt request NAKI is disabled 1 NACK receive interrupt request NAKI is enabled 3 STIE 0 R W Stop condition detection interrupt enable 0 Stop condition detection interrupt request STPI is disabled 1 Stop condition detection interrupt request STPI is enabled 2 ACKE 0 R W Acknowledge Bit Judgement Select 0 The value of the acknowledge bit is ignored and continuous transfer is pe...

Page 761: ...W Receive Data Register Full Setting condition When a received data is transferred from ICDRS to ICDRR Clearing conditions When 0 is written in RDRF after reading RDRF 1 4 NACKF 0 R W No acknowledge detection flag Setting condition When no acknowledge is detected from the receive device in transmission while the ACKE bit in ICIER is 1 Clearing condition When 0 is written in NACKF after reading NAC...

Page 762: ...OVE 1 1 AAS 0 R W Slave Address Recognition Flag In slave receive mode this flag is set to 1 if the first frame following a start condition matches bits SVA6 to SVA0 in SAR Setting condition When the slave address is detected in slave receive mode When the general call address is detected in slave receive mode Clearing condition When 0 is written in AAS after reading AAS 1 0 ADZ 0 R W General Call...

Page 763: ...ansmit data When ICDRT detects the space in the I 2 C bus shift register ICDRS it transfers the transmit data which is written in ICDRT to ICDRS and starts transferring data If the next transfer data is written to ICDRT during transferring data of ICDRS continuous transfer is possible 16 3 8 I 2 C Bus Receive Data Register ICDRR ICDRR is an 8 bit register that stores the receive data When data of ...

Page 764: ... 1 1 n1 7 1 m1 S SLA R A DATA A P 1 1 1 n2 7 1 m2 1 1 1 A n1 and n2 transfer bit count n1 and n2 1 to 8 m1 and m2 transfer frame count m1 and m2 1 1 1 Figure 16 3 I 2 C Bus Formats SDA SCL S 1 7 SLA 8 R 9 A 1 7 DATA 8 9 1 7 8 9 A DATA P A Figure 16 4 I 2 C Bus Timing Legend S Start condition The master device drives SDA from high to low while SCL is high SLA Slave address R Indicates the direction...

Page 765: ...w the slave address and R to ICDRT After this when TDRE is cleared to 0 data is transferred from ICDRT to ICDRS TDRE is set again 4 When transmission of one byte data is completed while TDRE is 1 TEND in ICSR is set to 1 at the rise of the 9th transmit clock pulse Read the ACKBR bit in ICIER and confirm that the slave device has been selected Then write second byte data to ICDRT and clear TDRE and...

Page 766: ...it 7 Slave address Address R Data 1 Data 1 Data 2 Address R Bit 6 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 2 1 2 3 4 5 6 7 8 9 A R Figure 16 5 Master Transmit Mode Operation Timing 1 TDRE 6 Issue stop condition Clear TEND 7 Set slave receive mode TEND ICDRT ICDRS 1 9 2 3 4 5 6 7 8 9 A A SCL master output SDA master output SDA slave output Bit 7 Bit 6 Data n Data n Bit 5 Bit 4 Bit 3 Bit 2 Bi...

Page 767: ... specified by ACKBT in ICIER to SDA at the 9th receive clock pulse 3 After the reception of first frame data is completed the RDRF bit in ICST is set to 1 at the rise of 9th receive clock pulse At this time the received data is read by reading ICDRR 4 The continuous reception is performed by reading ICDRR and clearing RDRF to 0 every time RDRF is set If 8th receive clock pulse falls after reading ...

Page 768: ... 4 Bit 3 Bit 2 Bit 1 Bit 0 User processing Data 1 Data 1 Figure 16 7 Master Receive Mode Operation Timing 1 RDRF RCVD ICDRS ICDRR Data n 1 Data n Data n Data n 1 5 Read ICDRR and clear RDRF after setting RCVD 6 Issue stop condition 7 Read ICDRR clear RDRF and clear RCVD 8 Set slave receive mode 1 9 2 3 4 5 6 7 8 9 A A SCL master output SDA master output SDA slave output Bit 7 Bit 6 Bit 5 Bit 4 Bit...

Page 769: ...ve receive mode and wait until the slave address matches 2 When the slave address matches in the first frame following detection of the start condition the slave device outputs the level specified by ACKBT in ICIER to SDA at the rise of the 9th clock pulse At this time if the 8th bit data R is 1 the TRS in ICCRA and TDRE in ICSR are set to 1 and the mode changes to slave transmit mode automaticall...

Page 770: ...ode SDA master output SDA slave output SCL slave output Bit 7 Bit 7 Data 1 Data 1 Data 2 Data 3 Data 2 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 2 Write data to ICDRT data 1 and clear TDRE 2 Write data to ICDRT data 2 and clear TDRE 2 Write data to ICDRT data 3 and clear TDRE User processing Figure 16 9 Slave Transmit Mode Operation Timing 1 ...

Page 771: ...The reception procedure and operations in slave receive mode are described below 1 Set the ICE bit in ICCRA to 1 Set the MLS and WAIT bits in ICMR and the CKS3 to CKS0 bits in ICCRA to 1 Initial setting Set the MST and TRS bits in ICCRA to select slave receive mode and wait until the slave address matches 2 When the slave address matches in the first frame following detection of the start conditio...

Page 772: ...ut Bit 7 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 2 Read ICDRR dummy read and clear RDRF 2 Read ICDRR and clear RDRF User processing Figure 16 11 Slave Receive Mode Operation Timing 1 ICDRS ICDRR 1 2 3 4 5 6 7 8 9 9 A A RDRF SCL master output SDA master output SDA slave output SCL slave output User processing Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Data 1 3 Set ACKBT 3 Read ICDRR an...

Page 773: ...The SCL or SDA input signal is sampled on the system clock but is not passed forward to the next circuit unless the outputs of both latches agree If they do not agree the previous value is held C Q D March detector Internal SCL or SDA signal SCL or SDA input signal Sampling clock Sampling clock System clock period Latch Latch C Q D Figure 16 13 Block Diagram of Noise Conceler 16 4 7 Example of Use...

Page 774: ... 1 Test the status of the SCL and SDA lines 2 Select master transmit mode 3 Start condition issuance 4 Select transmit data for the first byte slave address R W and clear TDRE to 0 5 Wait for 1 byte to be transmitted 6 Test the acknowledge bit transferred from the specified slave device 7 Set transmit data for the second and subsequent data except for the final byte and clear TDRE and TEND to 0 8 ...

Page 775: ...ode and then clear TDRE 2 Set acknowledge to the transmitting device 3 Dummy read ICDDR 4 Wait for 1 byte to be received 5 Check if last receive 1 6 Read the receive data and clear RDRF to 0 7 Set acknowledge of the final byte Disable continuous receive RCVD 1 8 Read receive data of final byte 1 and clear RDRF to 0 9 Wait for the final byte to be received 10 Stop condition issuance 11 Wait for the...

Page 776: ...RR Clear TDRE in ICSR End 1 Clear the flag AAS 2 Set transmit data for ICDRT except for the last data and clear TDRE to 0 3 Wait the empty of ICDRT 4 Set the last byte of the transmit data and clear TDRE to 0 5 Wait the transmission end of the last byte 6 Clear the flag TEND 7 Set slave receive mode 8 Dummy read ICDRR to release the SCL line 9 Clear the flag TDRE No No Yes TEND 1 1 2 3 4 5 6 7 8 9...

Page 777: ...6 7 8 9 10 1 Clear the flag AAS 2 Set the acknowledge for the transmit device 3 Dummy read ICDRR 4 Wait the reception end of 1 byte 5 Judge the last receive 1 6 Read the received data and clear RDRF to 0 7 Set the acknowledge for the last byte 8 Read the received data of the last byte 1 and clear RDRF to 0 9 Wait the reception end of the last byte 10 Read the received data of the last byte and cle...

Page 778: ...TOP recognition and arbitration lost Table 16 3 shows the contents of each interrupt request Table 16 3 Interrupt Requests Interrupt Request Abbreviation Interrupt Condition Transmit Data Empty TXI TDRE 1 TIE 1 Transmit End TEI TEND 1 TEIE 1 Receive Data Full RXI RDRF 1 RIE 1 STOP Recognition STPI STOP 1 STIE 1 NACK Receive Arbitration Lost NAKI NACKF 1 AL 1 NAKIE 1 ...

Page 779: ...ort in the two states described above Therefore it monitors SCL and communicates by bit with synchronization Figure 16 18 shows the timing of the bit synchronous circuit and table 16 4 shows the time when SCL output changes from low to Hi Z then SCL is monitored SCL VIH SCL monitor timing reference clock Internal SCL Figure 16 18 Timing of the Bit Synchronous Circuit Table 16 4 Time for monitoring...

Page 780: ...Rev 1 0 09 01 page 736 of 904 ...

Page 781: ...ion Two kinds of operating modes Single mode Single channel A D conversion Scan mode Continuous A D conversion on 1 to 4 channels or 1 to 8 channels H8S 2378R Series Eight data registers Conversion results are held in a 16 bit data register for each channel Sample and hold function Three kinds of conversion start Conversion can be started by software 16 bit timer pulse unit TPU conversion start tr...

Page 782: ...ccessive approximations register Multiplexer Legend ADCR A D control register ADCSR A D control status register ADDRA A D data register A ADDRB A D data register B ADDRC A D data register C ADDRD A D data register D ADDRE A D data register E ADDRF A D data register F ADDRG A D data register G ADDRH A D data register H Figure 17 1 Block Diagram of A D Converter 17 2 Input Output Pins Table 17 1 sum...

Page 783: ... AN3 Input Analog input pin 4 AN4 Input Analog input pin 5 AN5 Input Analog input pin 6 AN6 Input Analog input pin 7 AN7 Input Analog input pin 8 AN12 Input Channel set 1 analog inputs Analog input pin 9 AN13 Input Analog input pin 10 AN14 Input Analog input pin 11 AN15 Input Analog input pin 12 AN12 Input Analog input pin 13 AN13 Input Analog input pin 14 AN14 Input Analog input pin 15 AN15 Input...

Page 784: ...esult for each channel are shown in table 17 2 The converted 10 bit data is stored to bits 15 to 6 The lower 6 bit data is always read as 0 The data bus between the CPU and the A D converter is 16 bit width The data can be read directly from the CPU Table 17 2 Analog Input Channels and Corresponding ADDR Registers Analog Input Channel Channel Set 0 CH3 0 Channel Set 1 CH3 1 A D Data Register which...

Page 785: ...d by an ADI interrupt and ADDR is read 6 ADIE 0 R W A D Interrupt Enable A D conversion end interrupt ADI request enabled when 1 is set 5 ADST 0 R W A D Start Clearing this bit to 0 stops A D conversion and the A D converter enters wait state Setting this bit to 1 starts an A D conversion In single mode cleared to 0 automatically when conversion on the specified channel ends In scan mode conversio...

Page 786: ...N7 1111 AN15 When SCANE 1 and SCANS 0 0000 AN0 1000 AN8 0001 AN0 and AN1 1001 AN8 and AN9 0010 AN0 to AN2 1010 AN8 to AN10 0011 AN0 to AN3 1011 AN8 to AN11 0100 AN4 1100 AN12 0101 AN4 and AN5 1101 AN12 and AN13 0110 AN4 to AN6 1110 AN12 to AN14 0111 AN4 to AN7 1111 AN12 to AN15 When SCANE 1 and SCANS 1 0000 AN0 1000 AN8 0001 AN0 and AN1 1001 AN8 and AN9 0010 AN0 to AN2 1010 AN8 to AN10 0011 AN0 to...

Page 787: ...version start by external trigger pin 75 is enabled 5 4 SCANE SCANS 0 0 R W R W Scan Mode Selects single mode or scan mode as the A D conversion operating mode 0x Single mode 10 Scan mode A D conversion is performed continuously for channels 1 to 4 11 Scan mode A D conversion is performed continuously for channels 1 to 8 3 2 CKS1 CKS0 0 0 R W R W Clock Select 1 to 0 Sets the A D conversion time On...

Page 788: ...it is cleared to 0 during A D conversion A D conversion stops and the A D converter enters wait state 17 4 2 Scan Mode In scan mode A D conversion is to be performed sequentially on the specified channels maximum four channels or maximum eight channels Operations are as follows 1 When the ADST bit in ADCSR is set to 1 by a software TPU or external trigger input A D conversion starts on the first c...

Page 789: ... 17 3 indicates the A D conversion time As indicated in figure 17 2 the A D conversion time tCONV includes tD and the input sampling time tSPL The length of tD varies depending on the timing of the write access to ADCSR The total conversion time therefore varies within the ranges indicated in tables 17 3 In scan mode the values given in tables 17 3 apply to the first conversion time The values giv...

Page 790: ...KS1 CKS0 Conversion Time State 0 512 Fixed 0 1 256 Fixed 0 128 Fixed 1 1 64 Fixed 17 4 4 External Trigger Input Timing A D conversion can be externally triggered When the TRGS1 and TRGS0 bits are set to 11 in ADCR external trigger input is enabled at the 75 pin A falling edge at the 75 pin sets the ADST bit to 1 in ADCSR starting A D conversion Other operations in both single and scan modes are th...

Page 791: ...umber of A D converter digital output codes Quantization error The deviation inherent in the A D converter given by 1 2 LSB see figure 17 4 Offset error The deviation of the analog input voltage value from the ideal A D conversion characteristic when the digital output changes from the minimum voltage value B 0000000000 H 000 to B 0000000001 H 001 see figure 17 5 Full scale error The deviation of ...

Page 792: ...al output Ideal A D conversion characteristic Analog input voltage Figure 17 4 A D Conversion Precision Definitions FS Digital output Ideal A D conversion characteristic Nonlinearity error Analog input voltage Offset error Actual A D conversion characteristic Full scale error Figure 17 5 A D Conversion Precision Definitions ...

Page 793: ... possible to guarantee the A D conversion precision However if a large capacitance is provided externally for conversion in single mode the input load will essentially comprise only the internal input resistance of 10 kΩ and the signal source impedance is ignored However since a low pass filter effect is obtained in this case it may not be possible to follow an analog signal with a large different...

Page 794: ...lt in incorrect operation of the analog circuitry due to inductance adversely affecting A D conversion values Also digital circuitry must be isolated from the analog input signals AN0 to AN15 analog reference power supply Vref and analog power supply AVcc by the analog ground AVss Also the analog ground AVss should be connected at one point to a stable digital ground Vss on the board 17 7 6 Notes ...

Page 795: ...00 0 1 µF 0 01 µF 10 µF Figure 17 7 Example of Analog Input Protection Circuit Table 17 6 Analog Pin Specifications Item Min Max Unit Analog input capacitance 20 pF Permissible signal source impedance 10 kΩ 20 pF To A D converter AN0 to AN15 10 k Note Values are reference values Figure 17 8 Analog Input Pin Equivalent Circuit ...

Page 796: ...Rev 1 0 09 01 page 752 of 904 ...

Page 797: ...e module stop mode Module data bus Internal data bus Vref AVCC DA5 DA4 DA3 DA2 DA1 DA0 AVSS 8 bit D A Control circuit DADR0 DADR1 DADR2 DADR3 Bus interface Legend DADR0 D A data register 0 DADR1 D A data register 1 DADR2 D A data register 2 DADR3 D A data register 3 DADR4 D A data register 4 DADR5 D A data register 5 DACR01 D A control register 01 DACR23 D A control register 23 DACR45 D A control ...

Page 798: ...utput pin 3 DA3 Output Channel 3 analog output Analog output pin 4 DA4 Output Channel 4 analog output Analog output pin 5 DA5 Output Channel 5 analog output 18 3 Register Description The D A converter has the following registers D A data register 0 DADR0 D A data register 1 DADR1 D A data register 2 DADR2 D A data register 3 DADR3 D A data register 4 DADR4 D A data register 5 DADR5 D A control reg...

Page 799: ...utput DA1 is enabled 6 DAOE0 0 R W D A Output Enable 0 Controls D A conversion and analog output 0 Analog output DA0 is disabled 1 Channel 0 D A conversion is enabled analog output DA0 is enabled 5 DAE 0 R W D A Enable Used together with the DAOE0 and DAOE1 bits to control D A conversion When the DAE bit is cleared to 0 channel 0 and 1 D A conversions are controlled independently When the DAE bit ...

Page 800: ...0 Description 0 0 0 D A conversion disabled 1 Channel 0 D A conversion enabled channel1 D A conversion disabled 1 0 Channel 1 D A conversion enabled channel0 D A conversion disabled 1 Channel 0 and 1 D A conversions enabled 1 0 0 D A conversion disabled 1 Channel 0 and 1 D A conversions enabled 1 0 1 ...

Page 801: ...led 1 Channel 2 D A conversion is enabled analog output DA2 is enabled 5 DAE 0 R W D A Enable Used together with the DAOE0 and DAOE1 bits to control D A conversion When the DAE bit is cleared to 0 channel 2 and 3 D A conversions are controlled independently When the DAE bit is set to 1 channel 2 and 3 D A conversions are controlled together Output of conversion results is always controlled indepen...

Page 802: ...2 Description 0 0 0 D A conversion disabled 1 Channel 2 D A conversion enabled channel3 D A conversion disabled 1 0 Channel 3 D A conversion enabled channel2 D A conversion disabled 1 Channel 2 and 3 D A conversions enabled 1 0 0 D A conversion disabled 1 Channel 2 and 3 D A conversions enabled 1 0 1 ...

Page 803: ...led 1 Channel 4 D A conversion is enabled analog output DA4 is enabled 5 DAE 0 R W D A Enable Used together with the DAOE0 and DAOE1 bits to control D A conversion When the DAE bit is cleared to 0 channel 4 and 5 D A conversions are controlled independently When the DAE bit is set to 1 channel 4 and 5 D A conversions are controlled together Output of conversion results is always controlled indepen...

Page 804: ...to 1 D A conversion is enabled and the conversion result is output The operation example concerns D A conversion on channel 0 Figure 18 2 shows the timing of this operation 1 Write the conversion data to DADR0 2 Set the DAOE0 bit in DACR01 to 1 D A conversion is started The conversion result is output from the analog output pin DA0 after the conversion time tDCONV has elapsed The conversion result...

Page 805: ...ter operation using the module stop control register the D A converter does not operate by the initial value of the register The register can be accessed by releasing the module stop mode For details see section 22 Power Down Modes 18 5 2 D A Output Hold Function in Software Standby Mode If D A conversion is enabled and this LSI enters software standby mode D A output is held and analog power supp...

Page 806: ...Rev 1 0 09 01 page 762 of 903 ...

Page 807: ...y means of the RAME bit in the system control register SYSCR For details on the system control register SYSCR refer to section 3 2 2 System Control Register SYSCR Product Type Name ROM Type RAM Capacitance RAM Address HD64F2377 Flash memory version 24 kbytes H FF6000 to H FFBFFF H8S 2378 Series HD64F2376 16 kbytes H FF8000 to H FFBFFF HD64F2377R Flash memory version 24 kbytes H FF6000 to H FFBFFF ...

Page 808: ...Rev 1 0 09 01 page 764 of 904 ...

Page 809: ...pability The flash memory can be reprogrammed up to 100 times Two on board programming modes Boot mode User program mode On board programming erasing can be done in boot mode in which the on chip boot program is started for erase or programming of the entire flash memory In normal user program mode individual blocks can be erased or programmed Programmer mode Flash memory can be programmed erased ...

Page 810: ...1 Erase block register 1 EBR2 Erase block register 2 RAMER RAM emulation register SYSCR System control register Figure 20 1 Block Diagram of Flash Memory 20 2 Mode Transitions When the mode pins are set in the reset state and a reset start is executed this LSI enters an operating mode as shown in figure 20 2 In user mode flash memory can be read but not programmed or erased The boot user program a...

Page 811: ...a transition between user mode and user program mode when the CPU is not accessing the flash memory 0 0 0 MD2 1 MD0 1 MD1 1 MD2 0 MD0 0 MD1 0 MD2 0 P50 0 P51 0 P52 1 Figure 20 2 Flash Memory State Transitions Table 20 1 Differences between Boot Mode and User Program Mode Boot Mode User Program Mode Total erase Yes Yes Block erase No Yes Programming control program Program program verify Erase eras...

Page 812: ...ogramming control program transfer When boot mode is entered the boot program in the chip originally incorporated in the chip is started and the programming control program in the host is transferred to RAM via SCI communication The boot program required for flash memory erasing is automatically transferred to the RAM boot program area 3 Flash memory initialization The erase program in the boot pr...

Page 813: ...e prepared in the host or in the flash memory 2 Programming erase control program transfer When user program mode is entered user software confirms this fact executes the transfer program in the flash memory and transfers the programming erase control program to RAM 3 Flash memory initialization The programming erase program in RAM is executed and the flash memory is initialized to H FF Erasing ca...

Page 814: ...cate erasing units the narrow lines indicate programming units and the values are addresses The 384 kbyte flash memory is divided into 64 kbytes 5 blocks 32 kbytes 1 block and 4 kbyte 8 blocks Erasing is performed in these divided units Programming is performed in 128 byte units starting from an address whose lower eight bits are H 00 or H 80 ...

Page 815: ...4000 H 004001 H 004002 H 007000 H 007001 H 007002 H 008000 H 008001 H 008002 H 010000 H 010001 H 010002 H 020000 H 020001 H 020002 H 030000 H 030001 H 030002 Programming unit 128 bytes Programming unit 128 bytes EB12 Erase unit 64 kbytes EB13 Erase unit 64 kbytes H 05FFFF H 04007F H 04FFFF H 05007F H 040000 H 040001 H 040002 H 050000 H 050001 H 050002 Programming unit 128 bytes Programming unit 12...

Page 816: ...xD1 Output Serial transmit data output RxD1 Input Serial receive data input 20 5 Register Descriptions The flash memory has the following registers For details on the system control register refer to section 3 2 2 System Control Register SYSCR Flash memory control register 1 FLMCR1 Flash memory control register 2 FLMCR2 Erase block register 1 EBR1 Erase block register 2 EBR2 RAM emulation register...

Page 817: ... it is cleared to 0 the program setup state is cancelled 3 EV 0 R W Erase Verify When this bit is set to 1 while SWE 1 the flash memory transits to erase verify mode When it is cleared to 0 erase verify mode is cancelled 2 PV 0 R W Program Verify When this bit is set to 1 while SWE 1 the flash memory transits to program verify mode When it is cleared to 0 program verify mode is cancelled 1 E 0 R W...

Page 818: ...scription 7 EB7 0 R W When this bit is set to 1 4 kbytes of EB7 are to be erased 6 EB6 0 R W When this bit is set to 1 4 kbytes of EB6 are to be erased 5 EB5 0 R W When this bit is set to 1 4 kbytes of EB5 are to be erased 4 EB4 0 R W When this bit is set to 1 4 kbytes of EB4 are to be erased 3 EB3 0 R W When this bit is set to 1 4 kbyte of EB3 is to be erased 2 EB2 0 R W When this bit is set to 1...

Page 819: ...ize Modes 3 4 and 7 Modes 5 and 6 EB0 4 kbytes H 000000 to H 000FFF H 100000 to H 100FFF EB1 4 kbytes H 001000 to H 001FFF H 101000 to H 101FFF EB2 4 kbytes H 002000 to H 002FFF H 102000 to H 102FFF EB3 4 kbytes H 003000 to H 003FFF H 103000 to H 103FFF EB4 4 kbytes H 004000 to H 004FFF H 104000 to H 104FFF EB5 4 kbytes H 005000 to H 005FFF H 105000 to H 105FFF EB6 4 kbytes H 006000 to H 006FFF H ...

Page 820: ...real time flash memory programming RAMER settings should be made in user mode or user program mode To ensure correct operation of the emulation function the ROM for which RAM emulation is performed should not be accessed immediately after this register has been modified Normal execution of an access immediately after register modification is not guaranteed ...

Page 821: ... 0 0 R W R W R W Flash Memory Area Selection When the RAMS bit is set to 1 selects one of the following flash memory areas to overlap the RAM area The areas correspond with 4 kbyte erase blocks Modes 3 4 and 7 000 H 000000 to H 000FFF EB0 001 H 001000 to H 001FFF EB1 010 H 002000 to H 002FFF EB2 011 H 003000 to H 003FFF EB3 100 H 004000 to H 004FFF EB4 101 H 005000 to H 005FFF EB5 110 H 006000 to ...

Page 822: ...ation expanded mode with on chip ROM enabled 0 1 1 20 6 1 Boot Mode Table 20 5 shows the boot mode operations between reset end and branching to the programming control program 1 When boot mode is used the flash memory programming control program must be prepared in the host beforehand Prepare a programming control program in accordance with the description in section 20 8 Flash Memory Programming...

Page 823: ... TE bits in SCR to 0 but the adjusted bit rate value remains set in BRR Therefore the programming control program can still use it for transfer of write data or verify data with the host The TxD pin is high The contents of the CPU general registers are undefined immediately after branching to the programming control program These registers must be initialized at the beginning of the programming co...

Page 824: ...nd starts execution Checks flash memory data erases all flash memory blocks in case of written data existing and transmits data H AA to host If erase could not be done transmits data H FF to host and aborts operation H FF Boot program erase error H AA Item Boot mode initiation Measures low level period of receive data H 00 Calculates bit rate and sets BRR in SCI_1 Transmits data H 00 to host as ad...

Page 825: ...annot be read during programming erasing transfer the program erase program to on chip RAM as like in boot mode Figure 20 6 shows a sample procedure for programming erasing in user program mode Prepare a program erase program in accordance with the description in section 20 8 Flash Memory Programming Erasing Yes No Program erase Transfer user program erase control program to RAM Reset start Branch...

Page 826: ...ing the overlapping RAM 3 After the program data has been confirmed the RAMS bit is cleared thus releasing RAM overlap 4 The data written in the overlapping RAM is written into the flash memory space EB0 Start of emulation program Set RAMER Write tuning data to overlap RAM Execute application program Tuning OK Clear RAMER Write to flash memory emulation block End of emulation program No Yes Figure...

Page 827: ...mode or erase mode 5 A RAM area cannot be erased by execution of software in accordance with the erase algorithm 6 Block area EB0 contains the vector table When performing RAM emulation the vector table is needed in the overlap RAM H 00000 H 01000 H 02000 H 03000 H 04000 H 05000 H 06000 H 07000 H 08000 H 5FFFF Flash memory EB8 to EB13 This area can be accessed from both the RAM area and flash memo...

Page 828: ...dy been performed 2 Programming should be carried out 128 bytes at a time A 128 byte data transfer must be performed even if programming fewer than 128 bytes In this case H FF data must be written to the extra addresses 3 Prepare the following data storage areas in RAM a 128 byte programming data area a 128 byte reprogramming data area and a 128 byte additional programming data area Perform reprog...

Page 829: ...99 1000 Write Time z µs z1 z1 z1 z1 z1 z1 z2 z2 z2 z2 z2 z2 z2 z2 z2 z2 Notes 1 Data transfer is performed by byte transfer The lower 8 bits of the first address written to must be H 00 or H 80 A 128 byte data transfer must be performed even if writing fewer than 128 bytes in this case H FF data must be written to the extra addresses 2 Verify data is read in 16 bit W units 3 The reprogram data is ...

Page 830: ... which a dummy write was performed 6 If the read data is unerased set erase mode again and repeat the erase erase verify sequence as before The maximum number of repetitions of the erase erase verify sequence N must not be exceeded 20 8 3 Interrupt Handling when Programming Erasing Flash Memory All interrupts including NMI input are disabled when flash memory is being programmed or erased and whil...

Page 831: ...it in FLMCR1 Clear SWE bit in FLMCR1 Disable WDT Halt erase 1 Verify data all 1 Last address of block End of erasing of all erase blocks Erase failure Clear SWE bit in FLMCR1 n N NG NG NG NG OK OK OK OK n n 1 Increment address Notes 1 Prewriting setting erase block data to all 0 is not necessary 2 The values of x y z α β γ ε η θ and N are shown in section 24 6 Flash Memory Characteristics 3 Verify...

Page 832: ...nsition to program mode or erase mode By setting the erase block register 1 EBR1 and erase block register 2 EBR2 erase protection can be set for individual blocks When EBR1 and EBR2 are set to H 00 erase protection is set for all blocks 20 9 3 Error Protection In error protection an error is detected when the CPU s runaway occurs during flash memory programming erasing or operation is not performe...

Page 833: ...of this LSI and the flash memory When the flash memory returns to normal operation from a standby state a power supply circuit stabilization period is needed When the flash memory returns to its normal operating state bits STS3 to STS0 in SBYCR must be set to provide a wait time of at least 100 µs even when the external clock is being used Table 20 7 Flash Memory Operating States Operating Mode Fl...

Page 834: ...ming erasing Also do not clear the SWE bit during programming erasing or verifying Similarly when using the RAM emulation function the SWE bit must be cleared before executing a program or reading data in flash memory However the RAM area overlapping flash memory space can be read and written to regardless of whether the SWE bit is set or cleared 5 Do not use interrupts while flash memory is being...

Page 835: ... programmed Execution of program in flash memory prohibited and data reads other than verify operations prohibited Notes 1 Except when switching modes the level of the mode pins MD2 to MD0 must be fixed until power off by pulling the pins up or down 2 See section 24 6 Flash Memory Characteristics 3 Mode programming setup time tMDS min 200 ns SWE set SWE cleared φ VCC tOSC1 MD2 to MD0 1 RES SWE bit...

Page 836: ...hich the RES pin input is low and therefore these pins should not be used as output signals during this time 2 When making a transition from boot mode to another mode a mode programming setup time tMDS min of 200 ns is necessary with respect to RES clearance timing 3 See section 24 6 Flash Memory Characteristics 4 Wait time 100 µs φ VCC tOSC1 tMDS tMDS Wait time x Programming erasing possible Wait...

Page 837: ...R PLL system control register SCKCR System clock control register Figure 21 1 Block Diagram of Clock Pulse Generator The frequency can be changed by means of the PLL circuit Frequency changes are made by software by means of settings in the PLL control register PLLCR and the system clock control register SCKCR 21 1 Register Description The clock pulse generator has the following registers System c...

Page 838: ...ll module clock stop mode 0 ø output 1 Fixed high 6 0 R W Reserved The initial value should not be changed 5 4 0 0 Reserved These bits are always read as 0 and cannot be modified 3 STCS 0 R W Frequency Multiplication Factor Switching Mode Select Selects the operation when the PLL circuit frequency multiplication factor is changed 0 Specified multiplication factor is valid after transition to softw...

Page 839: ...e PLL circuit Bit Bit Name Initial Value R W Description 7 to 4 0 Reserved These bits are always read as 0 and cannot be modified 3 0 R W Reserved The initial value should not be changed 2 0 R W Reserved This bit is always read as 0 and cannot be modified 1 0 STC1 STC0 0 0 R W R W Frequency Multiplication Factor The STC bits specify the frequency multiplication factor used by the PLL circuit 00 1 ...

Page 840: ...f the crystal oscillator Use a crystal oscillator that has the characteristics shown in table 21 2 EXTAL XTAL Rd CL2 CL1 CL1 CL2 10 to 22 pF Figure 21 2 Connection of Crystal Oscillator Example Table 21 1 Damping Resistance Value Frequency MHz 8 12 16 20 25 Rd Ω 200 0 0 0 0 XTAL CL AT cut parallel resonance type EXTAL C0 L Rs Figure 21 3 Crystal Oscillator Equivalent Circuit Table 21 2 Crystal Osc...

Page 841: ...parasitic capacitance is no more than 10 pF When the counter clock is input to the XTAL pin make sure that the external clock is held high in standby mode Table 21 3 shows the input conditions for the external clock EXTAL XTAL External clock input Open a XTAL pin left open EXTAL XTAL External clock input b Counter clock input at XTAL pin Figure 21 4 External Clock Input Examples ...

Page 842: ... from the oscillator by a factor of 1 2 or 4 The multiplication factor is set with the STC1 and the STC0 bits in PLLCR The phase of the rising edge of the internal clock is controlled so as to match that of the rising edge of the EXTAL pin When the multiplication factor of the PLL circuit is changed the operation varies according to the setting of the STCS bit in SCKCR When STCS 0 the setting beco...

Page 843: ... specified from 8 MHz min to 33 MHz max outside of this range must be prevented 2 All the on chip peripheral modules operate on the Therefore note that the time processing of modules such as a timer and SCI differ before and after changing the clock division ratio In addition wait time for clearing software standby mode differs by changing the clock division ratio See the description Setting Oscil...

Page 844: ... 21 6 CL2 Signal A Signal B CL1 This LSI XTAL EXTAL Avoid Figure 21 6 Note on Oscillator Board Design Figure 21 7 shows the external circuitry recommended for the PLL circuit Separate PLLVcc and PLLVss from the other Vcc and Vss lines at the board power supply source and be sure to insert bypass capacitors CPB and CB close to the pins PLLVCC PLLVSS VCC VSS Rp 200W CPB 0 1 µF CB 0 1 µF Values are p...

Page 845: ...h speed mode and six power down modes Clock division mode Sleep mode Module stop mode All module clock stop mode Software standby mode Hardware standby mode Sleep mode is a CPU state clock division mode is an on chip peripheral function including bus masters and the CPU state and module stop mode is an on chip peripheral function including bus masters other than the CPU state A combination of thes...

Page 846: ...set DTC Functions Functions Functions Halted Retained Halted Retained Halted Retained Halted Reset TPU Functions Functions Functions Halted Retained Halted Retained Halted Retained Halted Reset PPG Functions Functions Functions Halted Retained Halted Retained Halted Retained Halted Reset D A Functions Functions Functions Halted Retained Halted Retained Halted Retained Halted Reset A D Functions Fu...

Page 847: ...s 1 NMI to 8 bit timer interrupts watchdog timer interrupts 8 bit timer interrupts are valid when MSTP0 0 2 NMI to IRQ0 to IRQ15 are valid when the corresponding bit in SSIER is 1 When a transition is made between modes by means of an interrupt the transition cannot be made on interrupt source generation alone Ensure that interrupt handling is performed after accepting the interrupt request From a...

Page 848: ... R W Description 7 SSBY 0 R W Software Standby This bit specifies the transition mode after executing the SLEEP instruction 0 Shifts to sleep mode after the SLEEP instruction is executed 1 Shifts to software standby mode after the SLEEP instruction is executed This bit does not change when clearing the software standby mode by using external interrupts and shifting to normal operation This bit sho...

Page 849: ...circuit stabilization time is necessary Refer to table 22 2 to set the wait time When DRAM is used and self refreshing in the software standby state is selected note that the DRAM s tRAS self refresh RAS pulse width specification must be satisfied With the F ZTAT version a flash memory stabilization time must be provided 0000 Setting prohibited 0001 Setting prohibited 0010 Setting prohibited 0011 ...

Page 850: ...MR 0 All module clocks stop mode disabled 1 All module clocks stop mode enabled 14 MSTP14 0 R W EXDMA controller EXDMAC 13 MSTP13 0 R W DMA controller DMAC 12 MSTP12 0 R W Data transfer controller DTC 11 MSTP11 1 R W 16 bit timer pulse unit TPU 10 MSTP10 1 R W Programmable pulse generator PPG 9 MSTP9 1 R W D A converter channels 0 and 1 8 MSTP8 1 R W D A converter channels 2 and 3 MSTPCRL Bit Bit ...

Page 851: ...ise set EXMSTPCR to H FFFD EXMSTPCRH Bit Bit Name Initial Value R W Module 15 to 12 1 R W Reserved Read write is enabled 1 should be written in writing 11 MSTP27 1 R W 10 MSTP26 1 R W 9 MSTP25 1 R W 8 MSTP24 1 R W EXMSTPCRL Bit Bit Name Initial Value R W Module 7 MSTP23 1 R W 6 MSTP22 1 R W 5 MSTP21 1 R W 4 MSTP20 1 R W I 2 C bus interface 2_1 IIC2_1 3 MSTP19 1 R W I 2 C bus interface 2_0 IIC2_0 2...

Page 852: ...d When the 5 6 pin is driven low the reset state is entered and clock division mode is cleared The same applies to a reset caused by watchdog timer overflow When the 67 pin is driven low a transition is made to hardware standby mode 22 2 2 Sleep Mode Transition to Sleep Mode When the SLEEP instruction is executed when the SSBY bit is 0 in SBYCR the CPU enters the sleep mode In sleep mode CPU opera...

Page 853: ...o be used as software standby mode clearing sources Clearing with an Interrupt When an NMI or IRQ0 to IRQ15 interrupt request signal is input clock oscillation starts and after the elapse of the time set in bits STS3 to STS0 in SBYCR stable clocks are supplied to the entire LSI software standby mode is cleared and interrupt exception handling is started When clearing software standby mode with an ...

Page 854: ...0 0 0 Reserved µs 1 Reserved 1 0 Reserved 1 Reserved 1 0 0 Reserved 1 64 1 9 2 6 3 2 4 9 6 4 8 0 1 0 512 15 5 20 5 25 6 39 4 51 2 64 0 1 1024 31 0 41 0 51 2 78 8 102 4 128 0 1 0 0 0 2048 62 1 81 9 102 4 157 5 204 8 256 0 1 4096 0 12 0 16 0 20 0 32 0 41 0 51 ms 1 0 16384 0 50 0 66 0 82 1 26 1 64 2 05 1 32765 0 99 1 31 1 64 2 52 3 28 4 10 1 0 0 65536 1 99 2 62 3 28 5 04 6 55 8 19 1 131072 3 97 5 24 ...

Page 855: ...bilization time tOSC2 NMI exception handling Figure 22 2 Software Standby Mode Application Example 22 2 4 Hardware Standby Mode Transition to Hardware Standby Mode When the 67 pin is driven low a transition is made to hardware standby mode from any mode In hardware standby mode all functions enter the reset state and stop operation resulting in a significant reduction in power dissipation As long ...

Page 856: ...tion is made to hardware standby mode Hardware standby mode is cleared by driving the 67 pin high waiting for the oscillation stabilization time then changing the 5 6 pin from low to high Oscillator Oscillation stabilization time Reset exception handling Figure 22 3 Hardware Standby Mode Timing 22 2 5 Module Stop Mode Module stop mode can be set for individual on chip peripheral modules When the c...

Page 857: ...mal program execution state via the exception handling state All module clocks stop mode is not cleared if interrupts are disabled if interrupts other than NMI are masked by the CPU or if the relevant interrupt is designated as a DTC activation source When the 67 pin is driven low a transition is made to hardware standby mode 22 3 ø Clock Output Control Output of the ø clock can be controlled by m...

Page 858: ... be set to 1 Setting of the EXDMAC DMAC or DTC module stop mode should be carried out only when the respective module is not activated For details refer to section 8 EXDMA Controller EXDMAC section 7 DMA Controller DMAC and section 9 Data Transfer Controller DTC 22 4 4 On Chip Peripheral Module Interrupts Relevant interrupt operations cannot be performed in module stop mode Consequently if module ...

Page 859: ...ons of the registers are described in the same order as the register addresses Reserved bits are indicated by in the bit name column No entry in the bit name column indicates that the whole register is allocated as a counter or for holding data For the registers of 16 or 32 bits the MSB is described first 3 Register states in each operating mode Register states are described in the same order as t...

Page 860: ...IC2_1 8 2 I 2 C bus status register_1 ICSR_1 8 H FD64 IIC2_1 8 2 Slave address register_1 SAR_1 8 H FD65 IIC2_1 8 2 I 2 C transfer data register_1 ICDRT_1 8 H FD66 IIC2_1 8 2 I 2 C receive data register_1 ICDRR_1 8 H FD67 IIC2_1 8 2 Serial expansion mode register_2 SEMR_2 8 H FDA8 SCI_2 8 2 EXDMA source address register_2 EDSAR_2 32 H FDE0 EXDMAC_2 16 2 EXDMA destination address register_2 EDDAR_2...

Page 861: ... IRQ enable register SSIER 16 H FE18 INT 16 2 IRQ sense control register H ISCRH 16 H FE1A INT 16 2 IRQ sense control register L ISCRL 16 H FE1C INT 16 2 IrDA control register_0 IrCR_0 8 H FE1E IrDA_0 8 2 Port 1 data direction register P1DDR 8 H FE20 PORT 8 2 Port 2 data direction register P2DDR 8 H FE21 PORT 8 2 Port 3 data direction register P3DDR 8 H FE22 PORT 8 2 Port 5 data direction register...

Page 862: ...40 SCI_3 8 2 Bit rate register_3 BRR_3 8 H FE41 SCI_3 8 2 Serial control register_3 SCR_3 8 H FE42 SCI_3 8 2 Transmit data register_3 TDR_3 8 H FE43 SCI_3 8 2 Serial status register_3 SSR_3 8 H FE44 SCI_3 8 2 Slave data register_3 RDR_3 8 H FE45 SCI_3 8 2 Smart card mode register_3 SCMR_3 8 H FE46 SCI_3 8 2 Serial mode register_4 SMR_4 8 H FE48 SCI_4 8 2 Bit rate register_4 BRR_4 8 H FE49 SCI_4 8 ...

Page 863: ...6 2 Timer counter_4 TCNT_4 16 H FE96 TPU_4 16 2 Timer general register A_4 TGRA_4 16 H FE98 TPU_4 16 2 Timer general register B_4 TGRB_4 16 H FE9A TPU_4 16 2 Timer control register_5 TCR_5 8 H FEA0 TPU_5 16 2 Timer mode register_5 TMDR_5 8 H FEA1 TPU_5 16 2 Timer I O control register_5 TIOR_5 8 H FEA2 TPU_5 16 2 Timer interrupt enable register_5 TIER_5 8 H FEA4 TPU_5 16 2 Timer status register_5 T...

Page 864: ...ontrol register REFCR 16 H FED4 BSC 16 2 Refresh timer counter RTCNT 8 H FED6 BSC 16 2 Refresh time constant register RTCOR 8 H FED7 BSC 16 2 Memory address register 0AH MAR_0AH 16 H FEE0 DMAC 16 2 Memory address register 0AL MAR_0AL 16 H FEE2 DMAC 16 2 I O address register 0A IOAR_0A 16 H FEE4 DMAC 16 2 Transfer count register 0A ETCR_0A 16 H FEE6 DMAC 16 2 Memory address register 0BH MAR_0BH 16 ...

Page 865: ... DTCERA 8 H FF28 DTC 16 2 DTC enable register B DTCERB 8 H FF29 DTC 16 2 DTC enable register C DTCERC 8 H FF2A DTC 16 2 DTC enable register D DTCERD 8 H FF2B DTC 16 2 DTC enable register E DTCERE 8 H FF2C DTC 16 2 DTC enable register F DTCERF 8 H FF2D DTC 16 2 DTC enable register G DTCERG 8 H FF2E DTC 16 2 DTC enable register H DTCERH 8 H FF2F DTC 16 2 DTC vector register DTVECR 8 H FF30 DTC 16 2 ...

Page 866: ... PODRL 8 H FF4B PPG 8 2 Next data register H 1 NDRH 8 H FF4C PPG 8 2 Next data register L 1 NDRL 8 H FF4D PPG 8 2 Next data register H 1 NDRH 8 H FF4E PPG 8 2 Next data register L 1 NDRL 8 H FF4F PPG 8 2 Port 1 register PORT1 8 H FF50 PORT 8 2 Port 2 register PORT2 8 H FF51 PORT 8 2 Port 3 register PORT3 8 H FF52 PORT 8 2 Port 4 register PORT4 8 H FF53 PORT 8 2 Port 5 register PORT5 8 H FF54 PORT ...

Page 867: ...RT 8 2 Port F data register PFDR 8 H FF6E PORT 8 2 Port G data register PGDR 8 H FF6F PORT 8 2 Port H register PORTH 8 H FF70 PORT 8 2 Port H data register PHDR 8 H FF72 PORT 8 2 Port H data direction register PHDDR 8 H FF74 PORT 8 2 Serial mode register_0 SMR_0 8 H FF78 SCI_0 8 2 Bit rate register_0 BRR_0 8 H FF79 SCI_0 8 2 Serial control register_0 SCR_0 8 H FF7A SCI_0 8 2 Transmit data register...

Page 868: ... FF92 A D 16 2 A D data register C ADDRC 16 H FF94 A D 16 2 A D data register D ADDRD 16 H FF96 A D 16 2 A D data register E ADDRE 16 H FF98 A D 16 2 A D data register F ADDRF 16 H FF9A A D 16 2 A D data register G ADDRG 16 H FF9C A D 16 2 A D data register H ADDRH 16 H FF9E A D 16 2 A D control status register ADCSR 8 H FFA0 A D 16 2 A D control register ADCR 8 H FFA1 A D 16 2 D A data register 0...

Page 869: ... TMR_0 16 2 Timer counter 1 TCNT_1 8 H FFB9 TMR_1 16 2 Timer control status register TCSR 8 H FFBC 2 Write WDT 16 2 H FFBC Read Timer counter TCNT 8 H FFBC 2 Write WDT 16 2 H FFBD Read Reset control status register RSTCSR 8 H FFBE 2 Write WDT 16 2 H FFBF Read Timer start register TSTR 8 H FFC0 TPU 16 2 Timer synchronous register TSYR 8 H FFC1 TPU 16 2 Flash memory control register 1 FLMCR1 8 H FFC...

Page 870: ... A_1 TGRA_1 16 H FFE8 TPU_1 16 2 Timer general register B_1 TGRB_1 16 H FFEA TPU_1 16 2 Timer control register_2 TCR_2 8 H FFF0 TPU_2 16 2 Timer mode register_2 TMDR_2 8 H FFF1 TPU_2 16 2 Timer I O control register_2 TIOR_2 8 H FFF2 TPU_2 16 2 Timer interrupt enable register_2 TIER_2 8 H FFF4 TPU_2 16 2 Timer status rgister_2 TSR_2 8 H FFF5 TPU_2 16 2 Timer counter_2 TCNT_2 16 H FFF6 TPU_2 16 2 Ti...

Page 871: ...ACKF STOP AL AAS ADZ SAR_0 SVA6 SVA5 SVA4 SVA3 SVA2 SVA1 SVA0 ICDRT_0 ICDRT7 ICDRT6 ICDRT5 ICDRT4 ICDRT3 ICDRT2 ICDRT1 ICDRT0 ICDRR_0 ICDRR7 ICDRR6 ICDRR5 ICDRR4 ICDRR3 ICDRR2 ICDRR1 ICDRR0 IIC2_0 ICCRA_1 ICE RCVD MST TRS CKS3 CKS2 CKS1 CKS0 ICCRB_1 BBSY SCP SDAO SDAOP SCLO IICRST ICMR_1 WAIT BCWP BC2 BC1 BC0 ICIER_1 TIE TEIE RIE NAKIE STIE ACKE ACKE ACKBT ICSR_1 TDRE TEND RDRF NACKF STOP AL AAS A...

Page 872: ...CR_2 DAT1 DAT0 DARIE DARA4 DARA3 DARA2 DARA1 DARA0 EXDMAC_2 EDSAR_3 EDDAR_3 EDTCR_3 EDA BEF EDRAKE ETENDE EDREQS AMS MDS1 MDS0 EDMDR_3 EDIE IRF TCEIE SDIR DTSIZE BGUP SAT1 SAT0 SARIE SARA4 SARA3 SARA2 SARA1 SARA0 EDACR_3 DAT1 DAT0 DARIE DARA4 DARA3 DARA2 DARA1 DARA0 EXDMAC_3 IPRA14 IPRA13 IPRA12 IPRA10 IPRA9 IPRA8 IPRA IPRA6 IPRA5 IPRA4 IPRA2 IPRA1 IPRA0 IPRB14 IPRB13 IPRB12 IPRB10 IPRB9 IPRB8 IPR...

Page 873: ...IPRI6 IPRI5 IPRI4 IPRI2 IPRI1 IPRI0 IPRJ14 IPRJ13 IPRJ12 IPRJ10 IPRJ9 IPRJ8 IPRJ IPRJ6 IPRJ5 IPRJ4 IPRJ2 IPRJ1 IPRJ0 IPRK14 IPRK13 IPRK12 IPRK10 IPRK9 IPRK8 IPRK IPRK6 IPRK5 IPRK4 IPRK2 IPRK1 IPRK0 ITS15 ITS14 ITS13 ITS12 ITS11 ITS10 ITS9 ITS8 ITSR ITS7 ITS6 ITS5 ITS4 ITS3 ITS2 ITS1 ITS0 SSI15 SSI14 SSI13 SSI12 SSI11 SSI10 SSI9 SSI8 SSIER SSI7 SSI6 SSI5 SSI4 SSI3 SSI2 SSI1 SSI0 IRQ15SCB IRQ15SCA I...

Page 874: ...S5E CS4E CS3E CS2E CS1E CS0E PFCR1 A23E A22E A21E A20E A19E A18E A17E A16E PFCR2 ASOE LWROE OES DMACS PAPCR PA7PCR PA6PCR PA5PCR PA4PCR PA3PCR PA2PCR PA1PCR PA0PCR PBPCR PB7PCR PB6PCR PB5PCR PB4PCR PB3PCR PB2PCR PB1PCR PB0PCR PCPCR PC7PCR PC6PCR PC5PCR PC4PCR PC3PCR PC2PCR PC1PCR PC0PCR PDPCR PD7PCR PD6PCR PD5PCR PD4PCR PD3PCR PD2PCR PD1PCR PD0PCR PEPCR PE7PCR PE6PCR PE5PCR PE4PCR PE3PCR PE2PCR PE...

Page 875: ...OB0 IOA3 IOA2 IOA1 IOA0 TIORL_3 IOD3 IOD2 IOD1 IOD0 IOC3 IOC2 IOC1 IOC0 TIER_3 TTGE TCIEV TGIED TGIEC TGIEB TGIEA TSR_3 TCFV TGFD TGFC TGFB TGFA Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8 TCNT_3 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8 TGRA_3 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8 TGRB_3 Bit7 Bit6 Bit5 B...

Page 876: ... TGFA Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8 TCNT_5 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8 TGRA_5 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8 TGRB_5 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 TPU_5 ABWCR ABW7 ABW6 ABW5 ABW4 ABW3 ABW2 ABW1 ABW0 ASTCR AST7 AST6 AST5 AST4 AST3 AST2 AST1 AST0 WTCRAH W72 W71 W7...

Page 877: ..._0AH Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8 MAR_0AL Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8 IOAR_0A Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8 ETCR_0A Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 MAR_0BH Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Bit15 Bit14 Bit13 Bit12 B...

Page 878: ...Bit2 Bit1 Bit0 Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8 ETCR_1B Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 DMAWER WE1B WE1A WE0B WE0A DMATCR TEE1 TEE0 DMACR_0A 2 DTSZ DTID RPE DTDIR DTF3 DTF2 DTF1 DTF0 DMACR_0A 3 DTSZ SAID SAIDE BLKDIR BLKE DMACR_0B 2 DTSZ DTID RPE DTDIR DTF3 DTF2 DTF1 DTF0 DMACR_0B 3 DAID DAIDE DTF3 DTF2 DTF1 DTF0 DMAC2 DMACR_1A 2 DTSZ DTID RPE DTDIR DTF3 DTF2 DTF1 DTF0 DMACR_1...

Page 879: ...1E IRQ0E IRQ15F IRQ14F IRQ13F IRQ12F IRQ11F IRQ10F IRQ9F IRQ8F ISR IRQ7F IRQ6F IRQ5F IRQ4F IRQ3F IRQ2F IRQ1F IRQ0F INT SBYCR SSBY OPE STS3 STS2 STS1 STS0 SCKCR PSTOP STCS SCK2 SCK1 SCK0 SYSCR MACS FLSHE EXPE RAME MDCR MDS2 MDS1 MDS0 MSTPCRH ACSE MSTP14 MSTP13 MSTP12 MSTP11 MSTP10 MSTP9 MSTP8 MSTPCRL MSTP7 MSTP6 MSTP5 MSTP4 MSTP3 MSTP2 MSTP1 MSTP0 EXMSTPCRH MSTP27 MSTP26 MSTP25 MSTP24 EXMSTPCRL MST...

Page 880: ...A2 PA1 PA0 PORTB PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 PORTC PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 PORTD PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 PORTE PE7 PE6 PE5 PE4 PE3 PE2 PE1 PE0 PORTF PF7 PF6 PF5 PF4 PF3 PF2 PF1 PF0 PORTG PG6 PG5 PG4 PG3 PG2 PG1 PG0 P1DR P17DR P16DR P15DR P14DR P13DR P12DR P11DR P10DR P2DR P27DR P26DR P25DR P24DR P23DR P22DR P21DR P20DR P3DR P35DR P34DR P33DR P32DR P31DR P30DR P5DR P53DR P52DR P...

Page 881: ...MR_0 SDIR SINV SMIF SCI_0 Smart card interface_0 SMR_1 4 SMR_1 5 C GM CHR BLK PE PE O O STOP BCP1 MP BCP0 CKS1 OKS1 CKS0 OKS0 BRR_1 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SCR_1 TIE RIE TE RE MPIE TEIE CKE1 CKE0 TDR_1 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SSR_1 4 SSR_1 5 TDRE TDRE RDRF RDRF ORER ORER FER ERS PER PER TEND TEND MPB MPB MPBT MPBT RDR_1 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SCMR_1...

Page 882: ...it6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 DADR1 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 DACR01 DAOE1 DAOE0 DAE DADR2 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 DADR3 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 DACR23 DAOE1 DAOE0 DAE DADR4 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 DADR5 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 DACR45 DAOE1 DAOE0 DAE D A TCR_0 CMIEB CMIEA OVIE CCLR1 CCLR0 CKS2 CKS1 CKS0 TCR_1 CMIEB C...

Page 883: ...OB0 IOA3 IOA2 IOA1 IOA0 TIORL_0 IOD3 IOD2 IOD1 IOD0 IOC3 IOC2 IOC1 IOC0 TIER_0 TTGE TCIEV TGIED TGIEC TGIEB TGIEA TSR_0 TCFV TGFD TGFC TGFB TGFA Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8 TCNT_0 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8 TGRA_0 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8 TGRB_0 Bit7 Bit6 Bit5 B...

Page 884: ... MD2 MD1 MD0 TIOR_2 IOB3 IOB2 IOB1 IOB0 IOA3 IOA2 IOA1 IOA0 TIER_2 TTGE TCIEU TCIEV TGIEB TGIEA TSR_2 TCFD TCFU TCFV TGFB TGFA Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8 TCNT_2 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8 TGRA_2 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8 TGRB_2 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1...

Page 885: ...R_1 Initialized ICSR_1 Initialized SAR_1 Initialized ICDRT_0 Initialized ICDRR_0 Initialized IIC2_1 SEMR_2 Initialized Initialized Initialized Initialized Initialized SCI2 EDSAR_2 Initialized Initialized EDDAR_2 Initialized Initialized EDTCR_2 Initialized Initialized EDMDR_2 Initialized Initialized EDACR_2 Initialized Initialized EXDMAC_2 EDSAR_3 Initialized Initialized EDDAR_3 Initialized Initial...

Page 886: ...tialized ITSR Initialized Initialized SSIER Initialized Initialized ISCRH Initialized Initialized ISCRL Initialized Initialized INT IrCR_0 Initialized Initialized IrDA_0 P1DDR Initialized P2DDR Initialized P3DDR Initialized P5DDR Initialized P6DDR Initialized P7DDR Initialized P8DDR Initialized PADDR Initialized PBDDR Initialized PCDDR Initialized PDDDR Initialized PEDDR Initialized PFDDR Initiali...

Page 887: ...itialized Initialized BRR_4 Initialized Initialized Initialized Initialized Initialized SCR_4 Initialized Initialized Initialized Initialized Initialized TDR_4 Initialized Initialized Initialized Initialized Initialized SSR_4 Initialized Initialized Initialized Initialized Initialized RDR_4 Initialized Initialized Initialized Initialized Initialized SCMR_4 Initialized Initialized Initialized Initi...

Page 888: ...TPU_5 ABWCR Initialized Initialized ASTCR Initialized Initialized WTCRAH Initialized Initialized WTCRAL Initialized Initialized WTCRBH Initialized Initialized WTCRBL Initialized Initialized RDNCR Initialized Initialized CSACRH Initialized Initialized CSACRL Initialized Initialized BROMCRH Initialized Initialized BROMCRL Initialized Initialized BCR Initialized Initialized BSC RAMER Initialized Init...

Page 889: ...lized IOAR_1B Initialized Initialized ETCR_1B Initialized Initialized DMAWER Initialized Initialized DMATCR Initialized Initialized DMACR_0A Initialized Initialized DMACR_0B Initialized Initialized DMACR_1A Initialized Initialized DMACR_1B Initialized Initialized DMABCRH Initialized Initialized DMABCRL Initialized Initialized DMAC DTCERA Initialized Initialized DTCERB Initialized Initialized DTCER...

Page 890: ...itialized PLLCR Initialized Initialized SYSTEM PCR Initialized Initialized PMR Initialized Initialized NDERH Initialized Initialized NDERL Initialized Initialized PODRH Initialized Initialized PODRL Initialized Initialized NDRH Initialized Initialized NDRL Initialized Initialized NDRH Initialized Initialized NDRL Initialized Initialized PPG PORT1 Initialized PORT2 Initialized PORT3 Initialized POR...

Page 891: ...lized Initialized Initialized Initialized Initialized SSR_0 Initialized Initialized Initialized Initialized Initialized RDR_0 Initialized Initialized Initialized Initialized Initialized SCMR_0 Initialized Initialized Initialized Initialized Initialized SCI_0 SMR_1 Initialized Initialized Initialized Initialized Initialized BRR_1 Initialized Initialized Initialized Initialized Initialized SCR_1 Ini...

Page 892: ...d Initialized Initialized Initialized Initialized ADDRE Initialized Initialized Initialized Initialized Initialized ADDRF Initialized Initialized Initialized Initialized Initialized ADDRG Initialized Initialized Initialized Initialized Initialized ADDRH Initialized Initialized Initialized Initialized Initialized ADCSR Initialized Initialized Initialized Initialized Initialized ADCR Initialized Ini...

Page 893: ...MDR_0 Initialized Initialized TIORH_0 Initialized Initialized TIORL_0 Initialized Initialized TIER_0 Initialized Initialized TSR_0 Initialized Initialized TCNT_0 Initialized Initialized TGRA_0 Initialized Initialized TGRB_0 Initialized Initialized TGRC_0 Initialized Initialized TGRD_0 Initialized Initialized TPU_0 TCR_1 Initialized Initialized TMDR_1 Initialized Initialized TIOR_1 Initialized Init...

Page 894: ...eed Clock Division Sleep Module Stop All Module Clock Stop Software Standby Hardware Standby Module TIER_2 Initialized Initialized TSR_2 Initialized Initialized TCNT_2 Initialized Initialized TGRA_2 Initialized Initialized TGRB_2 Initialized Initialized TPU_2 ...

Page 895: ...C 0 3 V Reference power supply voltage Vref 0 3 to AVCC 0 3 V Analog power supply voltage AVCC 0 3 to 4 0 V Analog input voltage VAN 0 3 to AVCC 0 3 V Operating temperature Topr Regular specifications 20 to 75 C Wide range specifications 40 to 85 C Storage temperature Tstg 55 to 125 C Caution Permanent damage to the LSI may result if absolute maximum ratings are exceeded Note F ZTAT version Ranges...

Page 896: ...VIH VCC 0 9 VCC 0 3 V 5 6 NMI FWE VCC 0 9 VCC 0 3 V EXTAL VCC 0 7 VCC 0 3 V Port 3 P50 to P53 3 ports 6 and 8 3 ports A to H 3 VCC 0 7 VCC 0 3 V Port 4 Port 9 AVCC 0 7 AVCC 0 3 V Input low voltage 5 6 67 MD2 to MD0 FWE VIL 0 3 VCC 0 1 V NMI EXTAL 0 3 VCC 0 2 V Ports 3 to 6 Port 8 ports A to H 3 0 3 VCC 0 2 V Output high All output pins VOH VCC 0 5 V IOH 200 µA voltage VCC 1 0 V IOH 1 mA Output low...

Page 897: ... 6 and 8 ports A to H ITSI 1 0 µA Vin 0 5 to VCC 0 5 V Input pull up MOS current Ports A to E Ip 10 300 µA VCC 3 0 to 3 6 V Vin 0 V 5 6 Cin 30 pF Vin 0 V NMI 30 pF f 1 MHz Input capacitance All input pins except 5 6 and NMI 15 pF Ta 25 C Normal operation ICC 4 TBD 3 3 V TBD mA f 33 MHz Sleep mode TBD 3 3 V TBD mA f 33 MHz Standby mode 3 0 01 10 µA Ta 50 C 80 µA 50 C Ta Current dissipation 2 When a...

Page 898: ...ence Table 24 4 Permissible Output Currents Conditions VCC 3 0 V to 3 6 V AVCC 3 0 V to 3 6 V Vref 3 0 V to AVCC VSS AVSS 0 V Ta 20 C to 75 C regular specifications Ta 40 C to 85 C wide range specifications Item Symbol Min Typ Max Unit Permissible output low current per pin All output pins IOL 2 0 mA Permissible output low current total Total of all output pins ΣIOL 80 mA Permissible output high c...

Page 899: ...24 3 AC Characteristics LSI output pin C RH RL 3 V C 50 pF ports A to H C 30 pF ports 1 to 3 P50 to P53 ports 6 and 8 RL 2 4 kΩ RH 12 kΩ Input output timing measurement level 1 5 V VCC 3 0 V to 3 6 V Figure 24 1 Output Load Circuit ...

Page 900: ...width tCL 10 ns Clock rise time tCr 5 ns Clock fall time tCf 5 ns Reset oscillation stabilization time crystal tOSC1 10 ms Figure 24 4 1 Software standby oscillation stabilization time crystal tOSC2 10 ms Figure 24 4 2 External clock output delay stabilization time tDEXT 500 µs Figure 24 4 1 Clock phase difference tcdif TBD TBD ns Figure 24 3 Clock pulse high width SDRAMφ tSDCH TBD ns Figure 24 3 ...

Page 901: ...Rev 1 0 09 01 page 857 of 904 tcyc tCH tCf tCL tCr SDRAM tcdif tsdcf tsdcr tSDCH tSDCL Figure 24 3 SDRAMφ φ φ φ Timing EXTAL VCC ø tDEXT tOSC1 tDEXT tOSC1 Figure 24 4 1 Oscillation Stabilization Timing ...

Page 902: ...tions VCC 3 0 V to 3 6 V AVCC 3 0 V to 3 6 V Vref 3 0 V to AVCC VSS AVSS 0 V ø 8 MHz to 33 MHz Ta 20 C to 75 C regular specifications Ta 40 C to 85 C wide range specifications Item Symbol Min Max Unit Test Conditions 5 6 setup time tRESS 200 ns Figure 24 5 5 6 pulse width tRESW 20 tcyc NMI setup time tNMIS 150 ns Figure 24 6 NMI hold time tNMIH 10 NMI pulse width in recovery from software standby ...

Page 903: ... ø tRESS tRESS tRESW Figure 24 5 Reset Input Timing ø NMI i 0 to 15 edge input Note Necessary for SSIER setting to clear software standby mode tNMIS tNMIH tIRQS tIRQS tIRQH tNMIW tIRQW level input Figure 24 6 Interrupt Input Timing ...

Page 904: ...2 tCSD2 15 ns 6 delay time 3 tCSD3 20 ns 6 delay time TASD 15 ns 5 delay time 1 tRSD1 15 ns 5 delay time 2 tRSD2 15 ns Read data setup time 1 tRDS1 15 ns Read data setup time 2 tRDS2 15 ns Read data hold time 1 tRDH1 0 ns Read data hold time 2 tRDH2 0 ns Read data access time 1 TAC1 1 0 tcyc 20 ns Read data access time 2 TAC2 1 5 tcyc 20 ns Read data access time 3 TAC3 2 0 tcyc 20 ns Read data acc...

Page 905: ... time 3 tWDH3 1 5 tcyc 8 ns Write command setup time 1 tWCS1 0 5 tcyc 10 ns Write command setup time 2 tWCS2 1 0 tcyc 10 ns Write command hold time 1 tWCH1 0 5 tcyc 10 ns Write command hold time 2 tWCH2 1 0 tcyc 10 ns Read command setup time 1 tRCS1 1 5 tcyc 10 ns Read command setup time 2 tRCS2 2 0 tcyc 10 ns Read command hold time tRCH 0 5 tcyc 10 ns 6 delay time 1 tCASD1 15 ns 6 delay time 2 tC...

Page 906: ...CD 15 ns Bus floating time tBZD 40 ns 5 42 delay time tBRQOD 25 ns Figure 24 24 6 delay time tCSD4 TBD ns Figure 24 26 DQM delay time tDQMD TBD ns Figure 24 26 CKE delay time tCKED TBD ns Figure 24 27 Read data setup time tRDS3 TBD ns Figure 24 26 Read data hold time tRDH3 TBD ns Figure 24 26 Write data delay time tWDD TBD ns Figure 24 26 Write data hold time tWDH4 TBD ns Figure 24 26 ...

Page 907: ... D0 D15 to D0 Read RDNn 1 Read RDNn 0 Write tAD tCSD1 tAS1 tAS1 tAS1 tAS1 tRSD1 tRSD1 tAC5 tAA2 tRSD1 tWRD2 tWSW1 tWDH1 tWDD tWRD2 tAH1 tAC2 tRDS2 tAA3 tRSD2 tRDS1 tRDH1 tAH1 tASD tASD to tDACD1 tDACD2 tEDACD1 tEDACD2 tRDH2 Figure 24 7 Basic Bus Timing Two State Access ...

Page 908: ...o D0 T2 T3 Read RDNn 1 Read RDNn 0 Write tAD tAS1 tAH1 tRSD1 tRDS1 tRDH1 tRSD2 tRDS2 tRDH2 tASD tASD tRSD1 tRSD1 tAC6 tAC4 tAA5 tAS2 tWSW2 tWDS1 tWRD1 tWRD2 tAH1 tAA4 tAS1 tAS1 tCSD1 to tDACD1 tDACD2 tEDACD1 tEDACD2 tWDH1 tWDD Figure 24 8 Basic Bus Timing Three State Access ...

Page 909: ...Rev 1 0 09 01 page 865 of 904 T1 ø A23 to A0 to D15 to D0 D15 to D0 D15 to D0 tWTS tWTH tWTS tWTH T2 Tw T3 Read RDNn 1 Read RDNn 0 Write Figure 24 9 Basic Bus Timing Three State Access One Wait ...

Page 910: ...tWDH3 tWSW1 tWDS2 tWDD tAS3 tWRD2 tWRD2 tRSD2 tRSD1 tAC2 tRDS2 tRDH2 tAS3 tRSD1 tAH3 tAH1 tASD ø A23 to A0 to D15 to D0 D15 to D0 D15 to D0 T1 T2 Tt Read RDNn 1 Read RDNn 0 Write to tDACD1 tDACD2 tEDACD1 tEDACD2 Figure 24 10 Basic Bus Timing Two State Access 6 6 6 6 Assertion Period Extended ...

Page 911: ...3 tWDH3 tWSW2 tWDS3 tAS4 tAS3 tRSD1 tWRD2 tWRD1 tAC4 tRDH2 tRSD2 tAC6 tRDH1 T1 T2 T3 Tt ø A23 to A0 to D15 to D0 D15 to D0 D15 to D0 Read RDNn 1 Read RDNn 0 Write to tDACD1 tDACD2 tEDACD1 tEDACD2 tRDS2 tWDD tRDS1 Figure 24 11 Basic Bus Timing Three State Access 6 6 6 6 Assertion Period Extended ...

Page 912: ...Rev 1 0 09 01 page 868 of 904 T1 ø A23 to A6 A0 A5 to A1 to D15 to D0 T2 T1 tAD tRSD2 tAA1 tRDS2 tRDH2 T1 Read Figure 24 12 Burst ROM Access Timing One State Burst Access ...

Page 913: ...Rev 1 0 09 01 page 869 of 904 T1 ø A23 to A6 A0 A5 to A1 to D15 to D0 T2 T3 T1 tAD tAS1 tASD tAA3 tRSD2 tRDS2 tRDH2 tASD tAH1 T2 Read Figure 24 13 Burst ROM Access Timing Two State Burst Access ...

Page 914: ...AC4 tWCS1 tWCH1 tWRD2 tWDD tWDS1 tWDH2 tRDS2 tRDH2 tAH2 tCSD3 tCASD1 tCASD1 tCASW1 tAD ø A23 to A0 to D15 to D0 D15 to D0 Tr Tc1 Tc2 Read Write to tDACD1 tDACD2 tEDACD1 tEDACD2 Note and timing when DDS 0 and EDDS 0 timing when RAST 0 tWRD2 Figure 24 14 DRAM Access Timing Two State Access ...

Page 915: ... D15 to D0 tWTS tWTH tWTS tWTH D15 to D0 Read Write Tcw Wait cycle inserted by programmable wait function Tcwp Wait cycle inserted by pin wait function to and timing when DDS 0 and EDDS 0 timing when RAST 0 Note Figure 24 15 DRAM Access Timing Two State Access One Wait ...

Page 916: ...p ø A23 to A0 to D15 to D0 D15 to D0 Tr Tc1 tCPW1 tAC3 tRCH tRCS1 Tc2 Tc1 Tc2 Read Write and timing when DDS 0 and EDDS 0 timing when RAST 0 Note to tDACD1 tDACD2 tEDACD1 tEDACD2 Figure 24 16 DRAM Access Timing Two State Burst Access ...

Page 917: ...tCASW2 tAC2 tAA5 tAC7 tWRD2 tWDD tWDS2 tWDH3 tWCS2 tWCH2 tRDH2 tOED2 tOED1 ø A23 to A0 to D15 to D0 D15 to D0 Tr Tc1 Tc2 Tc3 Write Read and timing when DDS 0 and EDDS 0 timing when RAST 0 Note to tDACD1 tDACD2 tEDACD1 tEDACD2 tWRD2 tRDS2 Figure 24 17 DRAM Access Timing Three State Access RAST 1 ...

Page 918: ...4 of 904 Tp Tr Tc1 Tc2 Tc3 Tc1 Tc2 Tc3 ø A23 to A0 to D15 to D0 tRCH tRCS2 tAC8 tCPW2 D15 to D0 Read Write and timing when DDS 1 and EDDS 1 timing when RAST 1 Note to Figure 24 18 DRAM Access Timing Three State Burst Access ...

Page 919: ...S Refresh Timing TRp ø to TRrw tCSD2 tCSR2 tCASD1 tCSD1 tCASD1 TRr TRc1 TRcw TRc2 Figure 24 20 CAS Before RAS Refresh Timing with Wait Cycle Insertion TRp ø to TRr tCSD2 tCASD1 tCSD2 tCASD1 tRPS2 TRc TRc Tpsr Tp Tr DRAM access Self refresh Figure 24 21 Self Refresh Timing Return from Software Standby Mode RAST 0 ...

Page 920: ... tCASD1 tCSD2 tCASD1 tRPS1 TRc TRc Tpsr Tp Tr DRAM access Self refresh Figure 24 22 Self Refresh Timing Return from Software Standby Mode RAST 1 ø tBREQS tBREQS tBACD tBZD tBACD tBZD A23 to A0 to to D15 to D0 Figure 24 23 External Bus Release Timing ...

Page 921: ...Rev 1 0 09 01 page 877 of 904 ø tBRQOD tBRQOD Figure 24 24 External Bus Request Output Timing ...

Page 922: ... Precharge sel DQMU DQML Data bus DQMU DQML Tr Tc1 Tw Tc2 Write Read tCSD4 tDQMD tRDS3 tRDH3 tCSD4 tCSD4 tCSD4 tCSD4 tCSD4 tCSD4 tCSD4 tDQMD tCSD4 tCSD4 tCSD4 tCSD4 tDQMD tDQMD tWDD tWDH4 tCSD4 tCSD4 High High Figure 24 25 Synchronous DRAM Basic Access Timing CAS Latency 2 ...

Page 923: ...Rev 1 0 09 01 page 879 of 904 TRp SDRAM Address bus Precharge sel CKE TRr TRr2 tCKED tCKED Software standby Figure 24 26 Synchronous DRAM Self Refresh Timing ...

Page 924: ...Rev 1 0 09 01 page 880 of 904 Tp φ SDRAMφ or Address bus Data bus Precharge sel CKE DQMU DQML Tr Tc1 Tc2 TRr Ttp2 tCKED tCKED Figure 24 27 Read Data Two State Expansion CAS Latency 2 ...

Page 925: ...ide range specifications Item Symbol Min Max Unit Test Conditions 5 4 setup time tDRQS 25 ns Figure 24 31 5 4 hold time tDRQH 10 7 1 delay time tTED 18 ns Figure 24 30 delay time 1 tDACD1 18 Figures 24 28 and 24 29 delay time 2 tDACD2 18 5 4 setup time tEDRQS 25 ns Figure 24 31 5 4 hold time tEDRQH 10 7 1 delay time tETED 18 ns Figure 24 30 delay time 1 tEDACD1 18 Figure 24 28 and 24 29 delay time...

Page 926: ...Rev 1 0 09 01 page 882 of 904 T1 ø A23 to A0 to tDACD1 tDACD2 tEDACD1 tEDACD2 read D15 to D0 read write D15 to D0 write to T2 Figure 24 28 DMAC and EXDMAC Single Address Transfer Timing Two State Access ...

Page 927: ... 1 0 09 01 page 883 of 904 T1 tDACD1 tEDACD1 tDACD2 tEDACD2 ø A23 to A0 to read D15 to D0 read write D15 to D0 write to T2 T3 Figure 24 29 DMAC and EXDMAC Single Address Transfer Timing Three State Access ...

Page 928: ... ø to T2 or T3 Figure 24 30 DMAC and EXDMAC 7 1 7 1 7 1 7 1 7 1 7 1 7 1 7 1 Output Timing ø tDRQS tEDRQS tDRQH tDERQH to Figure 24 31 DMAC and EXDMAC 5 4 5 4 5 4 5 4 5 4 5 4 5 4 5 4 Input Timing ø to tEDRKD tEDRKD Figure 24 32 EXDMAC 5 5 5 5 Output Timing ...

Page 929: ...ns Figure 24 36 Timer clock pulse width Single edge specification tTCKWH 1 5 tcyc Both edge specification tTCKWL 2 5 tcyc 8 bit timer Timer output delay time tTMOD 40 ns Figure 24 37 Timer reset input setup time tTMRS 25 ns Figure 24 39 Timer clock input setup time tTMCS 25 ns Figure 24 38 Timer clock pulse width Single edge specification tTMCWH 1 5 tcyc Both edge specification tTMCWL 2 5 tcyc WDT...

Page 930: ...DA input bus free time tBUF 5tCYC ns Start condition input hold time tSTAH 3tCYC ns Retransmit start condition input setup time tSTAS 3tCYC ns Stop condition input setup time tSTOS 1tCYC 20 ns Data input setup time tSDAS 0 ns Data input hold time tSDAH 0 ns SCL SDA capacitive load Cb 400 pF SCL SDA fall time tSf 300 ns T1 tPRS tPRH tPWD T2 ø Ports 1 to 8 A to H read Ports 1 to 3 6 to 8 P53 to P50 ...

Page 931: ...CA5 TIOCB0 to TIOCB5 TIOCC0 TIOCC3 TIOCD0 TIOCD3 Figure 24 35 TPU Input Output Timing ø TCLKA to TCLKD tTCKWL tTCKWH tTCKS tTCKS Figure 24 36 TPU Clock Input Timing ø TMO0 TMO1 tTMOD Figure 24 37 8 Bit Timer Output Timing ø TMCI0 TMCI1 tTMCWL tTMCWH tTMCS tTMCS Figure 24 38 8 Bit Timer Clock Input Timing ...

Page 932: ...er Reset Input Timing ø tWOVD tWOVD Figure 24 40 WDT Output Timing SCK0 to SCK2 tSCKW tSCKr tSCKf tScyc Figure 24 41 SCK Clock Input Timing SCK0 to SCK2 tTXD tRXS tRXH TxD0 to TxD2 transmit data RxD0 to RxD2 receive data Figure 24 42 SCI Input Output Timing Synchronous Mode ...

Page 933: ... Timing tBUF tSTAH tSTAS tSP tSTOS tSCLH tSCLL tSf tSr tSCL tSDAH tSDAS P S Sr VIH VIL SDA0 to SDA1 SCL0 to SCL1 Note S P and Sr represent the following conditions S Start condition P Stop condition Sr Retransmit start condition Figure 24 44 I 2 C Bus Interface Input Output Timing Option ...

Page 934: ...ble signal source impedance 5 kΩ Nonlinearity error 7 5 LSB Offset error 7 5 LSB Full scale error 7 5 LSB Quantization error 0 5 LSB Absolute accuracy 8 0 LSB 24 5 D A Conversion Characteristics Table 24 12 D A Conversion Characteristics Conditions VCC 3 0 V to 3 6 V AVCC 3 0 V to 3 6 V Vref 3 0 V to AVCC VSS AVSS 0 V ø 8 MHz to 33 MHz Ta 20 C to 75 C regular specifications Ta 40 C to 85 C wide ra...

Page 935: ...ming time 1 2 4 tP 10 200 ms 128 bytes Erase time 1 3 6 tE 50 1000 ms 128 bytes Rewrite times NWEC 100 Times Wait time after SWE bit setting 1 x 1 µs Wait time after PSU bit setting 1 y 50 µs z1 30 µs 1 n 6 z2 200 µs 7 n 1000 Wait time after P bit setting 1 4 z z3 10 µs Additional program ming wait Wait time after P bit clearing 1 α 5 µs Wait time after PSU bit clearing 1 β 5 µs Wait time after PV...

Page 936: ...it is set in flash memory control register 1 FLMCR1 Does not include the program verify time 3 Time to erase one block Indicates the time during which the E bit is set in FLMCR1 Does not include the erase verify time 4 Maximum programming time tP max Σ wait time after P bit setting z N i 1 5 The maximum number of writes N should be set as shown below according to the actual set value of z so as no...

Page 937: ...ectrical characteristic values operating margins noise margins and other properties may vary due to differences in manufacturing process on chip ROM layout patterns and so on When system evaluation testing is carried out using the F ZTAT version the same evaluation testing should also be conducted for the mask ROM version when changing over to that version ...

Page 938: ...Rev 1 0 09 01 page 894 of 904 ...

Page 939: ... Keep I O port P35 1 to 7 T T OPE 0 2 CKE 2 output T OPE 1 2 output H Other than the above Keep 2 CKE 2 output T Other than the above Keep 2 output 2 CKE 2 Other than the above I O port P47 DA1 1 to 7 T T DAOE1 1 Keep DAOE1 0 T Keep Input port P46 DA0 1 to 7 T T DAOE0 1 Keep DAOE0 0 T Keep Input port P45 to P40 1 to 7 T T T T Input port P53 to P50 1 to 7 T T Keep Keep I O port Port 6 1 to 7 T T Ke...

Page 940: ...T DAOE3 1 Keep DAOE3 0 T Keep Input port P94 DA2 1 to 7 T T DAOE2 1 Keep DAOE2 0 T Keep Input port P93 P90 1 to 7 T T T T Input port PA7 A23 PA6 A22 PA5 A21 1 to 7 T T OPE 0 address output T OPE 1 address output Keep Other than the above Keep Address output T Other than the above Keep Address output A23 to A21 Other than the above I O port PA4 A20 PA3 A19 PA2 A18 PA1 A17 PA0 A16 1 2 5 6 L T OPE 0 ...

Page 941: ...ss output A20 to A16 Other than the above I O port Port B 1 2 5 6 L T OPE 0 T OPE 1 Keep T Address output A15 to A8 4 T T OPE 0 address output T OPE 1 address output Keep Other than the above Keep Address output T Other than the above Keep Address output A15 to A8 Other than the above I O port 3 7 T T OPE 0 address output T OPE 1 address output Keep Other than the above Keep Address output T Other...

Page 942: ...tput T OPE 1 address output Keep Other than the above Keep Address output T Other than the above Keep Address output A7 to A0 Other than the above I O port Port D 1 2 4 to 6 T T T T D15 toD8 3 7 T T Data bus T Other than the above Keep Data bus T Other than the above Keep Data bus D15 to D8 Other than the above I O port Port E 1 2 4 to 6 8 bit bus T T Keep Keep I O port 16 bit bus T T T T D7 to D0...

Page 943: ...Input port 1 2 4 to 6 H PF6 6 3 7 T T OPE 0 6 output T OPE 1 6 output H Other than the above Keep 6 output T Other than the above Keep 6 output 6 Other than the above I O port 1 2 4 to 6 H OPE 0 T OPE 1 H T 5 5 PF5 5 PF4 5 3 7 T T OPE 0 5 5 output T OPE 1 5 5 output H Other than the above Keep 5 5 output T Other than the above Keep 5 5 output 5 5 Other than the above I O port 1 2 4 to 6 H PF3 5 3 ...

Page 944: ...ve Keep 6 40 output 6 40 Other than the above I O port PF1 8 6 408 1 to 7 T T OPE 0 8 6 408 output T OPE 1 8 6 408 output H Other than the above Keep 8 6 408 output T Other than the above Keep 8 6 408 output 8 6 Other than the above I O port PF0 7 1 to 7 T T 7 input T Other than the above Keep 7 input T Other than the above Keep 7 input 7 Other than the above I O port PG6 5 4 1 to 7 T T 5 4 input ...

Page 945: ...T 5 42 output 5 42 Other than the above Keep 5 42 output 5 42 Other than the above Keep 5 42 output 5 42 Other than the above I O port PG3 66 PG2 65 PG1 64 1 to 7 T T OPE 0 6 output T OPE 1 6 output H Other than the above Keep 6 output T Other than the above Keep 6 output 6 Other than the above I O port 1 2 5 6 H 3 4 7 T PG0 63 T OPE 0 6 output T OPE 1 6 output H Other than the above Keep 6 output...

Page 946: ...utput T Other than the above Keep 2 output 2 6 output 6 Other than the above I O port PH2 69 PH1 68 PH0 67 1 to 7 T T OPE 0 6 output T OPE 1 6 output H Other than the above Keep 6 output T Other than the above Keep 6 output 6 Other than the above I O port Legend L Low level H High level Keep Input port becomes high impedance output port retains state T High impedance DDR Data direction register OP...

Page 947: ... HD64F2377R 144 pin QFP FP 144H HD64F2376 HD64F2376 144 pin QFP FP 144H HD64F2376R HD64F2376R 144 pin QFP FP 144H Note The above products include those under development or being planned For the status of each product contact a Hitachi sales office When using the optional functions for the F ZTAT version which has the common type name contact a Hitachi sales office ...

Page 948: ...Hitachi Code JEDEC JEITA Mass reference value FP 144H Conforms 1 4 g Dimension including the plating thickness Base material dimension 0 08 0 10 0 5 20 22 0 0 3 108 73 109 72 37 144 1 36 22 0 0 3 1 0 0 5 0 1 1 70 Max 1 45 0 12 0 08 0 8 M 0 17 0 05 0 22 0 05 1 25 0 20 0 04 0 15 0 04 As of July 2001 Unit mm Figure C 1 Package Dimensions FP 144H ...

Page 949: ...ate 1st Edition September 2001 Published by Customer Service Division Semiconductor Integrated Circuits Hitachi Ltd Edited by Technical Documentation Group Hitachi Kodaira Semiconductor Co Ltd Copyright Hitachi Ltd 2001 All rights reserved Printed in Japan ...

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