Hitachi H8/3660, Hardware Manual

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348
Bit 7—Trigger Enable (TRGE): Enables or disables starting of A/D conversion by an external
trigger.
Bit 7: TRGE Description
0 Starting of A/D conversion by an external trigger is disabled (Initial value)
1 A/D conversion is started at the falling edge and the rising edge of the external
trigger signal (
ADTRG
)
Note: The selection between the falling edge and rising edge of the external trigger pin (
ADTRG
)
conforms to the setting of the interrupt edge select register 2 (IEGR2).
Bits 6 to 1—Reserved: These bits cannot be modified and are always read as 1.
Bit 0—Reserved: This bit can be read or written, but must not be set to 1.
16.3 CPU Interface
ADDRA to ADDRD are 16-bit registers, but they are connected to the CPU by an 8-bit data bus.
Therefore, although the upper byte can be be accessed directly by the CPU, the lower byte is read
through an 8-bit temporary register (TEMP).
An A/D data register is read as follows. When the upper byte is read, the upper-byte value is
transferred directly to the CPU and the lower-byte value is transferred into TEMP. Next, when the
lower byte is read, the TEMP contents are transferred to the CPU.
When reading an A/D data register, always read the upper byte before the lower byte. It is possible
to read only the upper byte, but if only the lower byte is read, incorrect data may be obtained.
Figure 16.2 shows the data flow for access to an A/D data register.