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Hitachi H8/3660 Hardware Manual Download Page 249

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Contention between General Register Write and Input Capture: If a capturing signal is
generated in the T2 state of a general register write cycle, writing to GR takes priority and input
capture (data transfer from TCNT to GR) is not performed. Figure 12.38 shows this timing.

Input capture 
signal

Write signal

Address

φ

GR address

GR

GR write cycle

T1

T2

X

TCNT

N

X+1

M (GR write data)

Figure 12.38   Contention between General Register Write and Input Capture

Summary of Contents for H8/3660

Page 1: ...ingle Chip Microcomputer H8 3664 Series H8 3664 HD6433664 H8 3663 HD6433663 H8 3662 HD6433662 H8 3661 HD6433661 H8 3660 HD6433660 H8 3664F ZTAT HD64F3664 Hardware Manual ADE 602 202A Rev 2 0 9 25 00 Hitachi Ltd ...

Page 2: ...of bodily injury such as aerospace aeronautics nuclear power combustion control transportation traffic safety equipment or medical equipment for life support 4 Design your application so that the product is used within the ranges guaranteed by Hitachi particularly for maximum rating operating supply voltage range heat radiation characteristics installation conditions and other characteristics Hita...

Page 3: ...rogramming Manual Notes When using an on chip emulator E10T for H8 3664 program development and debugging the following restrictions must be noted 1 The NMI pin is reserved for the E10T and cannot be used 2 Pins P85 P86 and P87 cannot be used In order to use these pins additional hardware must be provided on the user board 3 Area H 7000 to H 7FFF is used by the E10T and is not available to the use...

Page 4: ......

Page 5: ...gure No amended 322 Figure 15 5 I2 C Bus Timing R W is amended to R W 322 to 324 15 3 2 Master Transmit Operation Figure 15 6 Example of Master Transmit Mode Operation Timing MLS WAIT 0 Description changed Figure amended 324 to 326 15 3 3 Master Receive Operation Figure 15 7 Example of Master Receive Mode Operation Timing 1 NLS ACKB 0 WAIT 1 Figure 15 7 Example of Master Receive Mode Operation Tim...

Page 6: ...2 DC Characteristics 2 Conditions changed 370 Table 18 4 I2 C Bus Interface Timing Symbol in SCL and SDA output fall time amended 372 373 Table 18 6 A D Converter Characteristics Min Value in AVcc amended Test Condition of Conversion time single mode amended 373 Table 18 7 Watchdog Timer Characteristics Unit amended 376 to 388 18 3 Electrical Characteristics Mask ROM Version Added 411 to 417 A 3 N...

Page 7: ...2 2 5 2 Basic Instruction Formats 32 2 6 Addressing Modes and Effective Address Calculation 33 2 6 1 Addressing Modes 33 2 6 2 Effective Address Calculation 35 2 7 Basic Bus Cycle 39 2 7 1 Access to On Chip Memory RAM ROM 39 2 7 2 Access to On Chip Peripheral Modules 40 2 8 CPU States 41 2 8 1 Overview 41 2 9 Application Notes 42 2 9 1 Notes on Data Access to Empty Areas 42 2 9 2 Notes on Bit Mani...

Page 8: ...n Stack Area Use 62 3 7 2 Notes on Rewriting Port Mode Registers 63 Section 4 Address Break 67 4 1 Overview 67 4 1 1 Block Diagram 67 4 1 2 Register Configuration 68 4 2 Register Descriptions 68 4 2 1 Address Break Control Register ABRKCR 68 4 2 2 Address Break Status Register ABRKSR 70 4 2 3 Break Address Registers BARH BARL 71 4 2 4 Break Data Registers BDRH BDRL 72 4 3 Operation 72 Section 5 Cl...

Page 9: ...he Subactive Mode 93 6 8 Active Mode 94 6 8 1 Transition to the Active Mode 94 6 8 2 Transition from the Active Mode to Other Modes 94 6 8 3 Operating Frequency in the Active Mode 94 6 9 Direct Transition 95 6 9 1 Direct Transition Time 95 6 10 Module Standby Mode 96 Section 7 ROM 97 7 1 Features 97 7 2 Overview 98 7 2 1 Block Diagram 98 7 2 2 On board Programming Mode 99 7 2 3 Block Configuration...

Page 10: ... 7 10 3 Memory Read Mode 126 7 10 4 Auto Program Mode 129 7 10 5 Auto Erase Mode 131 7 10 6 Status Read Mode 133 7 10 7 Status Polling 134 7 10 8 Programmer Mode Transition Time 134 7 10 9 Notes on Memory Programming 135 Section 8 RAM 137 8 1 Overview 137 8 1 1 Block Diagram 137 Section 9 I O Ports 139 9 1 Overview 139 9 2 Port 1 140 9 2 1 Overview 140 9 2 2 Register Configuration and Description ...

Page 11: ...56 9 6 1 Overview 156 9 6 2 Register Configuration and Description 156 9 6 3 Port Data Register 8 PDR8 157 9 6 4 Port Control Register 8 PCR8 157 9 6 5 Pin Functions 158 9 7 Port B 161 9 7 1 Overview 161 9 7 2 Register Configuration and Description 161 9 7 3 Port Data Register B PDRB 161 9 7 4 Pin Functions 162 Section 10 Timer A 163 10 1 Overview 163 10 1 1 Features 163 10 1 2 Block Diagram 164 1...

Page 12: ...les 183 11 3 4 Application Notes 185 Section 12 Timer W 191 12 1 Overview 191 12 1 1 Features 191 12 1 2 Block Diagrams 193 12 1 3 Input Output Pins 194 12 1 4 Register Configuration 195 12 2 Register Description 196 12 2 1 Timer Mode Register W TMRW 196 12 2 2 Timer Control Register W TCRW 197 12 2 3 Timer Interrupt Enable Register W TIERW 199 12 2 4 Timer Status Register W TSRW 201 12 2 5 Timer ...

Page 13: ...14 2 2 Receive Data Register RDR 249 14 2 3 Transmit Shift Register TSR 250 14 2 4 Transmit Data Register TDR 250 14 2 5 Serial Mode Register SMR 251 14 2 6 Serial Control Register 3 SCR3 253 14 2 7 Serial Status Register SSR 256 14 2 8 Bit Rate Register BRR 260 14 3 Operation 267 14 3 1 Asynchronous Mode 267 14 3 2 Synchronous Mode 267 14 3 3 Interrupts and Continuous Transmission Reception 269 1...

Page 14: ...d Slave Address Register SARX 307 15 2 4 I2 C Bus Mode Register ICMR 307 15 2 5 I2 C Bus Control Register ICCR 310 15 2 6 I2 C Bus Status Register ICSR 316 15 2 7 Timer Serial Control Register TSCR 320 15 3 Operation 321 15 3 1 I2 C Bus Data Format 321 15 3 2 Master Transmit Operation 322 15 3 3 Master Receive Operation 324 15 3 4 Slave Receive Operation 326 15 3 5 Slave Transmit Operation 328 15 ...

Page 15: ...s 361 18 2 2 DC Characteristics 363 18 2 3 AC Characteristics 368 18 2 4 A D Converter Characteristics 372 18 2 5 Watchdog Timer 373 18 2 6 Flash Memory Characteristics Preliminary 374 18 3 Electrical Characteristics Mask ROM Version 376 18 3 1 Power Supply Voltage and Operating Ranges 376 18 3 2 DC Characteristics 378 18 3 3 AC Characteristics 383 18 3 4 A D Converter Characteristics 387 18 3 5 W...

Page 16: ...x Appendix D Port States in the Different Processing States 442 Appendix E Model Names 443 Appendix F Package Dimensions 444 ...

Page 17: ...tic and logic instructions Signed and unsigned multiply instructions 8 bits 8 bits 16 bits 16 bits Signed and unsigned divide instructions 16 bits 8 bits 32 bits 16 bits Bit accumulator function Bit manipulation instructions with register indirect specification of bit positions Interrupts 11 external interrupt sources NMI IRQ3 to IRQ0 WKP5 to WKP0 20 internal interrupt sources Clock pulse generato...

Page 18: ...tch sub clock Timer V 8 bit timer Count up timer with selection of six internal clock signals or event input from external pin Compare match waveform output Externally triggerable Timer W 16 bit timer Counts any of four internal clock signals or external events Maximum of four types of pulses can be input or output and processed Output compare input capture 4 output pins Output compare input captu...

Page 19: ...mode and slave mode Supports two slave addresses A D converter 10 bit resolution 8 channel analog input pins selectable between single mode and scan mode Conversion time 7 µs Sample and hold function Package Code Body Size Pin Pitch QFP 64 FP 64E 10 0 10 0 mm 0 5 mm QFP 64 FP 64A 14 0 14 0 mm 0 8 mm SDIP 42 DP 42S 14 0 37 3 mm 1 78 mm ...

Page 20: ...RES TEST NMI AV CC P20 SCK3 P21 RXD P22 TXD P87 P86 P85 P84 FTIOD P83 FTIOC P82 FTIOB P81 FTIOA P80 FTCI P76 TMOV P75 TMCIV P74 TMRIV OSC1 OSC2 X1 X2 Port 1 Data bus upper CPU H8 300H ROM RAM Data bus lower Timer W I2 C bus interface Timer A SCI3 Watchdog timer Timer V A D converter Port B CMOS large current port I OL 20 mA V OL 1 5 V Subclock generator System clock generator Port 2 Port 5 Address...

Page 21: ...TIOB P81 FTIOA P80 FTCI NMI NC NC 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 NC NC P14 IRQ0 P15 IRQ1 P16 IRQ2 P17 IRQ3 TRGV PB4 AN4 PB5 AN5 PB6 AN6 PB7 AN7 PB3 AN3 PB2 AN2 PB1 AN1 PB0 AN0 NC NC NC NC P76 TMOV P75 TMCIV P74 TMRIV P57 SCL P56 SDA P12 P11 P10 TMOW P55 WKP5 ADTRG P54 WKP4 P53 WKP3 P52 WKP2 NC NC H8 3664 Series Top view Note Do not c...

Page 22: ...16 17 18 19 20 21 P17 IRQ3 TRGV P16 IRQ2 P15 IRQ1 P14 IRQ0 P22 TXD P21 RXD P20 SCK3 P87 P86 P85 P84 FTI0D P83 FTI0C P82 FTI0B P81 FTI0A P80 FTCI NMI P76 TMOV P75 TMCIV P74 TMRIV P57 SCL P56 SDA 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 H8 3664 Series Top view Note DP 42S has no P11 P12 PB4 AN4 PB5 AN5 PB6 AN6 and PB7 AN7 pins Figure 1 3 Pin Arrangement DP 42S ...

Page 23: ...ep down power supply Connect a capacitor of around 0 1 µF between this pin and the VSS pin for stabilization Clock pins OSC1 11 13 Input System clock These pins connect to a crystal or ceramic oscillator or can be used to input an external clock OSC2 10 12 Output See section 5 Clock Pulse Generators for a typical connection diagram X1 5 7 Input Subclock These pins connect to a 32 768 kHz crystal o...

Page 24: ...uit Timer V TMOV 30 26 Output Timer V output This is an output pin for waveforms generated by the timer V output compare function TMCIV 29 25 Input Timer V event input This is an event input pin for input to the timer V counter TMRIV 28 24 Input Timer V counter reset This is a counter reset input pin for timer V TRGV 54 42 Input Timer V counter trigger input This is a trigger input pin for the tim...

Page 25: ...onverter ADTRG 22 20 Input A D converter trigger input This is the external trigger input pin to the A D converter I O ports PB7 to PB0 55 to 62 1 to 4 Input Port B This is an 8 bit input port P17 to P14 P12 to P10 51 to 54 23 to 25 39 to 42 21 I O Port 1 This is a 7 bit I O port P22 to P20 44 to 46 36 to 38 I O Port 2 This is a 3 bit I O port P57 to P50 13 14 19 to 22 26 27 15 to 20 22 23 I O Por...

Page 26: ...10 ...

Page 27: ...it registers or eight 32 bit registers Sixty two basic instructions 8 16 32 bit data transfer and arithmetic and logic instructions Multiply and divide instructions Powerful bit manipulation instructions Eight addressing modes Register direct Rn Register indirect ERn Register indirect with displacement d 16 ERn or d 24 ERn Register indirect with post increment or pre decrement ERn or ERn Absolute ...

Page 28: ...register divide 22 states Low power mode Transition to low power state by SLEEP instruction 2 2 Address Space and Memory Map The address space of the H8 3664 Series CPU is 64 kbytes which includes the program area and the data area Figures 2 1 and 2 2 show the memory map ...

Page 29: ...rsion HD6433660 Mask ROM version HD6433661 Mask ROM version Interrupt vector On chip ROM 8 kbytes Not used On chip RAM 512 bytes Internal I O register H 0000 H 0033 H 0034 H FD80 H FF7F H FF80 H FFFF H 1FFF Interrupt vector On chip ROM 12 kbytes Not used On chip RAM 512 bytes Internal I O register H 0000 H 0033 H 0034 H FD80 H FF7F H FF80 H FFFF H 2FFF 1 kbyte user area On chip RAM 2 kbytes Figure...

Page 30: ...ask ROM version HD6433662 Mask ROM version H FD80 Interrupt vector On chip ROM 24 kbytes Not used Not used On chip RAM 1 kbyte Internal I O register H 0000 H 0033 H 0034 H 5FFF H FB80 H FF7F H FF80 H FFFF Interrupt vector On chip ROM 32 kbytes Not used On chip RAM 1 kbyte Internal I O register H 0000 H 0033 H 0034 H 7FFF H FB80 H FF7F H FF80 H FFFF Figure 2 2 Memory Map 2 ...

Page 31: ...ER2 ER3 ER4 ER5 ER6 ER7 E0 E1 E2 E3 E4 E5 E6 E7 R0H R1H R2H R3H R4H R5H R6H R7H R0L R1L R2L R3L R4L R5L R6L R7L 0 7 0 7 0 15 SP 23 0 PC 7 CCR 6 5 4 3 2 1 0 I UI H U N Z V C General Registers ERn Control Registers CR Legend SP PC CCR I UI H U N Z V C Stack pointer Program counter Condition code register Interrupt mask bit User bit or interrupt mask bit Half carry flag User bit Negative flag Zero fl...

Page 32: ...to E7 and R R0 to R7 These registers are functionally equivalent providing a maximum sixteen 16 bit registers The E registers E0 to E7 are also referred to as extended registers The R registers divide into 8 bit general registers designated by the letters RH R0H to R7H and RL R0L to R7L These registers are functionally equivalent providing a maximum of sixteen 8 bit registers Figure 2 4 illustrate...

Page 33: ... 8 bit register contains internal CPU status information including the interrupt mask bit I and half carry H negative N zero Z overflow V and carry C flags The I bit is initialized to 1 by reset exception handling sequence but other bits are not initialized Bit 7 Interrupt Mask Bit I Masks interrupts other than NMI when set to 1 NMI is accepted regardless of the I bit setting Bit 6 User Bit UI Can...

Page 34: ...g C Set to 1 when a carry occurs and cleared to 0 otherwise Used by Add instructions to indicate a carry Subtract instructions to indicate a borrow Shift and rotate instructions to store the value shifted out of the end bit The carry flag is also used as a bit accumulator by bit manipulation instructions Some instructions leave flag bits unchanged Operations can be performed on CCR by the LDC STC ...

Page 35: ... of 4 bit BCD data 2 4 1 General Register Data Formats Figures 2 6 and 2 7 show the data formats in general registers 7 RnH RnL RnH RnL RnH RnL 1 bit data 1 bit data 4 bit BCD data 4 bit BCD data Byte data Byte data 6 5 4 3 2 1 0 7 0 Don t care 7 6 5 4 3 2 1 0 7 0 Don t care Don t care 7 0 4 3 Lower digit Upper digit 7 4 3 Lower digit Upper digit Don t care 0 7 0 Don t care MSB LSB Don t care 7 0 ...

Page 36: ...ster Data Type Data Format 15 0 MSB LSB 31 16 MSB 15 0 LSB Notation ERn En Rn RnH RnL MSB LSB General register General register E General register R General register RH General register RL Most significant bit Least significant bit Figure 2 7 General Register Data Formats 2 ...

Page 37: ...east significant bit of the address is regarded as 0 so the access starts at the preceding address This also applies to instruction fetches When ER7 SP is used as an address register to access the stack the operand size should be word size or longword size 7 6 5 4 3 2 1 0 Address L Address L LSB MSB MSB LSB 7 0 MSB LSB 1 bit data Byte data Word data Longword data Address Data Type Data Format Addr...

Page 38: ...ster or address register EAd Destination operand EAs Source operand CCR Condition code register N N negative flag of CCR Z Z zero flag of CCR V V overflow flag of CCR C C carry flag of CCR PC Program counter SP Stack pointer IMM Immediate data disp Displacement Addition Subtraction Multiplication Division AND logical OR logical Exclusive OR logical Move NOT logical complement 3 8 16 24 3 8 16 or 2...

Page 39: ... Cannot be used in the H8 3664 Series MOVTPE B Rs EAs Cannot be used in the H8 3664 Series POP W L SP Rn Pops a general register from the stack POP W Rn is identical to MOV W SP Rn Similarly POP L ERn is identical to MOV L SP ERn PUSH W L Rn SP Pushes a general register onto the stack PUSH W Rn is identical to MOV W Rn SP Similarly PUSH L ERn is identical to MOV L ERn SP Note Size refers to the op...

Page 40: ...AS B Rd decimal adjust Rd Decimal adjusts an addition or subtraction result in a general register by referring to CCR to produce 4 bit BCD data MULXU B W Rd Rs Rd Performs unsigned multiplication on data in two general registers either 8 bits 8 bits 16 bits or 16 bits 16 bits 32 bits MULXS B W Rd Rs Rd Performs signed multiplication on data in two general registers either 8 bits 8 bits 16 bits or ...

Page 41: ...16 bit register to word data or extends word data in the lower 16 bits of a 32 bit register to longword data by extending the sign bit EXTU W L Rd zero extension Rd Extends byte data in the lower 8 bits of a 16 bit register to word data or extends word data in the lower 16 bits of a 32 bit register to longword data by padding with zeros Note Size refers to the operand size B Byte W Word L Longword...

Page 42: ...ter and another general register or immediate data NOT B W L Rd Rd Takes the one s complement of general register contents Note Size refers to the operand size B Byte W Word L Longword Table 2 4 Shift Instructions Instruction Size Function SHAL SHAR B W L Rd shift Rd Performs an arithmetic shift on general register contents SHLL SHLR B W L Rd shift Rd Performs a logical shift on general register c...

Page 43: ...neral register or memory operand and sets or clears the Z flag accordingly The bit number is specified by 3 bit immediate data or the lower 3 bits of a general register BAND B C bit No of EAd C ANDs the carry flag with a specified bit in a general register or memory operand and stores the result in the carry flag BIAND B C bit No of EAd C ANDs the carry flag with the inverse of a specified bit in ...

Page 44: ... B bit No of EAd C Transfers a specified bit in a general register or memory operand to the carry flag BILD B bit No of EAd C Transfers the inverse of a specified bit in a general register or memory operand to the carry flag The bit number is specified by 3 bit immediate data BST B C bit No of EAd Transfers the carry flag value to a specified bit in a general register or memory operand BIST B C bi...

Page 45: ...ar high or same C 0 BCS BLO Carry set low C 1 BNE Not equal Z 0 BEQ Equal Z 1 BVC Overflow clear V 0 BVS Overflow set V 1 BPL Plus N 0 BMI Minus N 1 BGE Greater or equal N V 0 BLT Less than N V 1 BGT Greater than Z N V 0 BLE Less or equal Z N V 1 JMP Branches unconditionally to a specified address BSR Branches to a subroutine at a specified address JSR Branches to a subroutine at a specified addre...

Page 46: ...m memory data is read by word access STC B W CCR EAd Transfers the CCR contents to a destination location The condition code register size is one byte but in transfer to memory data is written by word access ANDC B CCR IMM CCR Logically ANDs the condition code register with immediate data ORC B CCR IMM CCR Logically ORs the condition code register with immediate data XORC B CCR IMM CCR Logically e...

Page 47: ...next EEPMOV W if R4 0 then repeat ER5 ER6 R4 1 R4 until R4 0 else next Transfers a data block according to parameters set in general registers R4L or R4 ER5 and ER6 R4L or R4 Size of block bytes ER5 Starting source address ER6 Starting destination address Execution of the next instruction begins as soon as the transfer is completed ...

Page 48: ...cified by 3 bits data registers by 3 bits or 4 bits Some instructions have two register fields Some have no register field Effective Address Extension 8 16 or 32 bits specifying immediate data an absolute address or a displacement A 24 bit address or displacement is treated as 32 bit data in which the first 8 bits are 0 H 00 Condition Field Specifies the branching condition of Bcc instructions Fig...

Page 49: ...ect and immediate modes Data transfer instructions can use all addressing modes except program counter relative and memory indirect Bit manipulation instructions use register direct register indirect or absolute aa 8 addressing mode to specify an operand and register direct BSET BCLR BNOT and BTST instructions or immediate 3 bit addressing mode to specify a bit number in the operand Table 2 9 Addr...

Page 50: ...r 4 is added to the address register contents 32 bits and the sum is stored in the address register The value added is 1 for byte access 2 for word access or 4 for longword access For word or longword access the register value should be even Register indirect with pre decrement ERn The value 1 2 or 4 is subtracted from an address register ERn specified by the register field in the instruction code...

Page 51: ...o 128 bytes 63 to 64 words or 32766 to 32768 bytes 16383 to 16384 words from the branch instruction The resulting value should be an even number 8 Memory Indirect aa 8 This mode can be used by the JMP and JSR instructions The instruction code contains an 8 bit absolute address specifying a memory operand This memory operand contains a branch address The memory operand is accessed by longword acces...

Page 52: ...ents 31 0 0 r op 23 3 Register indirect with displacement d 16 ERn d 24 ERn General register contents Sign extension disp 31 0 23 0 op r disp 4 Register indirect with post increment or pre decrement Register indirect with post increment ERn General register contents 1 2 or 4 31 0 0 r op 23 Register indirect with pre decrement ERn General register contents 1 for a byte operand 2 for a word operand ...

Page 53: ...ive Address 5 Absolute address aa 8 aa 8 aa 16 aa 24 0 8 7 0 16 15 0 op abs op abs op abs H FFFF 23 23 23 Sign exten sion 6 Immediate xx 8 xx 16 or xx 32 op IMM Operand is immediate data 7 Program counter relative d 8 PC or d 16 PC 0 23 disp 0 23 op disp PC contents Sign exten sion ...

Page 54: ... Address 8 Memory indirect aa 8 0 0 23 8 7 0 15 H 0000 op abs abs Memory contents 0 16 15 23 H 00 Legend r rm rn Register field op Operation field disp Displacement IMM Immediate data abs Absolute address Note In the H8 3664 Series the upper 8 bits of the calculation result are ignored ...

Page 55: ...depending on whether access is to on chip memory or to on chip peripheral modules 2 7 1 Access to On Chip Memory RAM ROM Access to on chip memory takes place in two states The data bus width is 16 bits allowing access in byte or word size Figure 2 11 shows the on chip memory access cycle T1 state Bus cycle T2 state Internal address bus Internal read signal Internal data bus read access Internal wr...

Page 56: ...an be accessed by byte or word size When a register with 8 bit data bus width is accessed by word size access is completed in two cycles In two state access the operation timing is the same as that for on chip memory Figure 2 12 shows the operation timing in the case of three state access to an on chip peripheral module T1 state Bus cycle Internal address bus Internal read signal Internal data bus...

Page 57: ... section 3 Exception Handling CPU state Reset state Program execution state Program halt state Exception handling state Active high speed mode Subactive mode Sleep mode Subsleep mode Power down modes The CPU executes successive program instructions at high speed synchronized by the system clock The CPU executes successive program instructions at reduced speed synchronized by the subclock A state i...

Page 58: ...tes 2 9 1 Notes on Data Access to Empty Areas The address space of the H8 3664 Series CPU includes empty areas in addition to the RAM registers and ROM areas available to the user If these empty areas are mistakenly accessed by an application program the following results will occur Data transfer from CPU to empty area The transferred data will be lost This action may also cause the CPU to misoper...

Page 59: ...nd C It does not apply to the H8 3664 Series Figure 2 15 shows an example in which two timer registers share the same address When a bit manipulation instruction accesses the timer load register and timer counter of a reloadable timer since these two registers share the same address the following operations take place Order of Operation Operation 1 Read Timer counter data is read one byte 2 Modify...

Page 60: ...fter executing BSET P57 P56 P55 P54 P53 P52 P51 P50 Input output Input Input Output Output Output Output Output Output Pin state Low level High level Low level Low level Low level Low level Low level High level PCR5 0 0 1 1 1 1 1 1 PDR5 0 1 0 0 0 0 0 1 D Explanation of how BSET operates When the BSET instruction is executed first the CPU reads port 5 Since P57 and P56 are input pins the CPU reads ...

Page 61: ...t Pin state Low level High level Low level Low level Low level Low level Low level Low level PCR5 0 0 1 1 1 1 1 1 PDR5 1 0 0 0 0 0 0 0 RAM0 1 0 0 0 0 0 0 0 B BSET instruction executed BSET 0 RAM0 The BSET instruction is executed designating the PDR5 work area RAM0 C After executing BSET MOV B RAM0 R0L MOV B R0L PDR5 The work area RAM0 value is written to PDR5 P57 P56 P55 P54 P53 P52 P51 P50 Input ...

Page 62: ...1 1 1 1 1 1 PDR5 1 0 0 0 0 0 0 0 B BCLR instruction executed BCLR 0 PCR5 The BCLR instruction is executed designating PCR5 C After executing BCLR P57 P56 P55 P54 P53 P52 P51 P50 Input output Output Output Output Output Output Output Output Input Pin state Low level High level Low level Low level Low level Low level Low level High level PCR5 1 1 1 1 1 1 1 0 PDR5 1 0 0 0 0 0 0 0 D Explanation of how...

Page 63: ...t Pin state Low level High level Low level Low level Low level Low level Low level Low level PCR5 0 0 1 1 1 1 1 1 PDR5 1 0 0 0 0 0 0 0 RAM0 0 0 1 1 1 1 1 1 B BCLR instruction executed BCLR 0 RAM0 The BCLR instruction is executed designating the PCR5 work area RAM0 C After executing BCLR MOV B RAM0 R0L MOV B R0L PCR5 The work area RAM0 value is written to PCR5 P57 P56 P55 P54 P53 P52 P51 P50 Input ...

Page 64: ...ytes specified by R4L from the address specified by R5 to the address specified by R6 R6 R6 R4L R5 R5 R4L When setting R4L and R6 make sure that the final destination address R6 R4L does not exceed H FFFF The value in R6 must not change from H FFFF to H 0000 during execution of the instruction H FFFF Not allowed R6 R6 R4L R5 R5 R4L ...

Page 65: ...cessing is stopped and the chip enters the reset state The internal state of the CPU and the registers of the on chip peripheral modules are initialized by the reset To make sure the chip is reset properly when turning the power on the RES pin should be held at low until the clock pulse generator output stabilizes When resetting during operation the RES pin should be held at low for at least 10 sy...

Page 66: ...the stack correctly resulting in control over the program being lost To prevent this immediately after reset exception handling all interrupts including NMI are masked For this reason the initial program instruction is always executed immediately after a reset This instruction should initialize the stack pointer e g MOV W xx 16 SP Vector fetch ø Internal address bus Internal read signal Internal w...

Page 67: ...orities and Their Vector Addresses Interrupt Source Interrupt Vector Number Vector Address Priority RES Watchdog timer Reset 0 H 0000 to H 0001 High Reserved by Reserved by system 1 H 0002 to H 0003 system 2 H 0004 to H 0005 3 H 0006 to H 0007 4 H 0008 to H 0009 5 H 000A to H 000B 6 H 000C to H 000D External pin NMI 7 H 000E to H 000F Trap instruction Trap instruction 0 8 H 0010 to H 0011 executed...

Page 68: ...apture D compare match D Timer W overflow 21 H 002A to H 002B Timer V Timer V compare match A Timer V compare match B Timer V overflow 22 H 002C to H 002D SCI3 SCI3 transmit end SCI3 transmit data empty SCI3 receive data full SCI3 overrun error SCI3 framing error SCI3 parity error 23 H 002E to H 002F IIC Data transfer end Address inequality Stop conditions detected 24 H 0030 to H 0031 A D converte...

Page 69: ...G IEG3 IEG2 IEG1 IEG0 Initial value 0 1 1 1 0 0 0 0 Read Write R W R W R W R W R W IEGR1 is an 8 bit read write register used to designate whether pins NMI and IRQ3 to IRQ0 are set to rising edge sensing or falling edge sensing Upon reset IEGR1 is initialized to H 70 Bit 7 NMI Edge Select NMIEG Bit 7 selects the input sensing of pin NMI Bit 7 NMIEG Description 0 Falling edge of NMI pin input is de...

Page 70: ...etected initial value 1 Rising edge of IRQ0 pin input is detected 3 4 2 Interrupt Edge Select Register 2 IEGR2 Bit 7 6 5 4 3 2 1 0 WPEG5 WPEG4 WPEG3 WPEG2 WPEG1 WPEG0 Initial value 1 1 0 0 0 0 0 0 Read Write R W R W R W R W R W R W IEGR2 is an 8 bit read write register used to designate whether pins WKP5 to WKP0 are set to rising edge sensing or falling edge sensing Upon reset IEGR2 is initialized...

Page 71: ...ENR1 is initialized to H 10 Bit 7 Direct Transfer Interrupt Enable IENDT Bit 7 enables or disables direct transfer interrupt requests Bit 7 IENDT Description 0 Disables direct transfer interrupt requests initial value 1 Enables direct transfer interrupt requests Bit 6 Timer A Interrupt Enable IENTA Bit 6 enables or disables timer A overflow interrupt requests Bit 6 IENTA Description 0 Disables tim...

Page 72: ...a corresponding flag is set to 1 when a direct transfer a timer A or IRQ3 to IRQ0 interrupt is requested The flags are not cleared automatically when an interrupt is accepted It is necessary to write 0 to clear each flag Upon reset IRR1 is initialized to H 30 Bit 7 Direct Transfer Interrupt Request Flag IRRDT Bit 7 IRRDT Description 0 Clearing conditions initial value When IRRDT 1 it is cleared by...

Page 73: ...3 IWPF2 IWPF1 IWPF0 Initial value 1 1 0 0 0 0 0 0 Read Write R W R W R W R W R W R W IWPR is an 8 bit read write register in which a corresponding flag is set to 1 when the designated signal edge is input at pin WKP5 to WKP0 The flags are not cleared automatically when an interrupt is accepted It is necessary to write 0 to clear each flag Upon reset IWPR is initialized to H C0 Bits 7 and 6 Bits 7 ...

Page 74: ... to IEN0 in IENR1 WKP5 to WKP0 Interrupts WKP5 to WKP0 interrupts are requested by input signals to pins WKP5 to WKP0 These six interrupts have the same vector addresses and are detected individually by either rising edge sensing or falling edge sensing depending on the settings of bits WPEG5 to WPEG0 in IEGR2 When pins WKP5 to WKP0 are designated for interrupt input in PMR5 and the designated sig...

Page 75: ... this time is shown in figure 3 2 The PC value pushed onto the stack is the address of the first instruction to be executed upon return from interrupt handling 5 Then the I bit of CCR is set to 1 masking further interrupts excluding the NMI and address break Upon return from interrupt handling the values of I bit and other bits in CCR will be restored and returned to the values prior to the start ...

Page 76: ...ter PC Lower 8 bits of program counter PC Condition code register Stack pointer Notes CCR CCR 3 PCH PCL 1 2 PC shows the address of the first instruction to be executed upon return from the interrupt handling routine Register contents must always be saved and restored by word length starting from an even numbered address 3 Ignored when returning from the interrupt handling routine Figure 3 2 Stack...

Page 77: ...is saved as PC contents becoming return address 2 4 Instruction code not executed 3 Instruction prefetch address Instruction is not executed 5 SP 2 6 SP 4 7 CCR 8 Vector address 9 Starting address of interrupt handling routine contents of vector 10 First instruction of interrupt handling routine 3 9 8 6 5 4 1 7 10 Stack access Internal processing Instruction prefetch Interrupt level decision and w...

Page 78: ...n When a TRAP instruction is executed trap instruction exception handling starts up A TRAP instruction generates vector addresses corresponding to the vector numbers 0 to 3 designated in the instruction code 3 7 Application Notes 3 7 1 Notes on Stack Area Use When word data is accessed in the H8 3664 Series the least significant bit of the address is regarded as 0 Access to the stack always takes ...

Page 79: ... lower bytes of word data are saved to the stack on return the even address contents are restored to CCR while the odd address contents are ignored 3 7 2 Notes on Rewriting Port Mode Registers When a port mode register is rewritten to switch the functions of external interrupt pins the following points should be observed When an external interrupt pin function is switched by rewriting the port mod...

Page 80: ... changed from 0 to 1 while pin WKP5 is low and bit WPEG5 in IEGR2 0 When bit WKP5 in PMR5 is changed from 1 to 0 while pin WKP5 is low and bit WPEG5 in IEGR2 1 IWPF4 When bit WKP4 in PMR5 is changed from 0 to 1 while pin WKP4 is low and bit WPEG4 in IEGR2 0 When bit WKP4 in PMR5 is changed from 1 to 0 while pin WKP4 is low and bit WPEG4 in IEGR2 1 IWPF3 When bit WKP3 in PMR5 is changed from 0 to 1...

Page 81: ...truction the flag will not be cleared An alternative method to avoid the setting of interrupt request flags when pin functions are switched is to keep the pins at the high level so that the conditions in table 3 5 do not occur CCR I bit 1 Set port mode register bit Execute NOP instruction Interrupts masked Another possibility is to disable the relevant interrupt in interrupt enable register 1 Afte...

Page 82: ...66 ...

Page 83: ...ic address With the address break function the execution start point of a program containing a bug is detected and execution is branched to the correcting program 4 1 1 Block Diagram Figure 4 1 shows a block diagram of the address break BARH BARL BDRH BDRL ABRKCR ABRKSR Internal address bus Comparator Interrupt generation control circuit Internal data bus Comparator Interrupt Notation BARH BARL Br...

Page 84: ...ak data register L BDRL R W Undefined H FFCD 4 2 Register Descriptions 4 2 1 Address Break Control Register ABRKCR Bit 7 6 5 4 3 2 1 0 RTINTE CSEL1 CSEL0 ACMP2 ACMP1 ACMP0 DCMP1 DCMP0 Initial value 1 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W ABRKCR is an 8 bit read write register that sets address break conditions Bit 7 RTE Interrupt Enable RTINTE Bit 7 enables or disables an interr...

Page 85: ...mpare 16 bit addresses Initial value 1 Compares upper 12 bit addresses 1 0 Compares upper 8 bit addresses 1 Compares upper 4 bit addresses 1 Reserved Note Don t care Bits 1 and 0 Data Compare Condition Select DCMP1 DCMP0 Bits 1 and 0 set the comparison condition between the data set in BDR and the internal data bus Bit 1 DCMP1 Bit 0 DCMP0 Description 0 0 No data comparison Initial value 1 Compares...

Page 86: ... FF8F is accessed by word byte access occurs twice 4 2 2 Address Break Status Register ABRKSR Bit 7 6 5 4 3 2 1 0 ABIF ABIE Initial value 0 0 1 1 1 1 1 1 Read Write R W R W ABRKSR is an 8 bit read write register that consists of the address break interrupt flag and the address break interrupt enable bit Bit 7 Address Break Interrupt Flag ABIF Bit 7 indicates an address break interrupt Bit 7 ABIF D...

Page 87: ...ddress Registers BARH BARL Bit 7 6 5 4 3 2 1 0 BARH7 BARH6 BARH5 BARH4 BARH3 BARH2 BARH1 BARH0 Initial value 1 1 1 1 1 1 1 1 Read Write R W R W R W R W R W R W R W R W Bit 7 6 5 4 3 2 1 0 BARL7 BARL6 BARL5 BARL4 BARL3 BARL2 BARL1 BARL0 Initial value 1 1 1 1 1 1 1 1 Read Write R W R W R W R W R W R W R W R W BAR BARH BARL is a 16 bit read write register that sets the address for generating an addre...

Page 88: ... is compared with the lower 8 bit data bus When memory or registers are accessed by byte the upper 8 bit data bus is used for even and odd addresses in the data transmission Therefore comparison data must be set in BDRH for byte access For word access the data bus used depends on the address See section 4 2 1 Address Break Control Register for details 4 3 Operation When the ABIE bit in ABRKSR is s...

Page 89: ...en the address break is specified in instruction execution cycle Figure 4 2 Address Break Interrupt Operation Example 1 MOV instruc tion 1 prefetch Register setting ABRKCR H A0 BAR H 025A Program 0258 025A 025C 0260 0262 NOP NOP MOV W H 025A R0 NOP NOP 025C Address bus φ Interrupt request 025E 0260 025A 0262 0264 SP 2 MOV instruc tion 2 prefetch NOP instruc tion prefetch MOV instruc tion execution...

Page 90: ...OP instruc tion prefetch Stack resumption Internal processing MOV instruc tion execution 025A Interrupt acceptance 0262 SP 2 SP 4 XXXX NOP instruc tion prefetch Vector fetch Internal processing Stack restore Internal processing 039A 039C 039E NOP RTE NOP Interrupt Interrupt Underline indicates the address to be stacked When the interrupt acceptance is prohibited after the RTE RTB instruction Addre...

Page 91: ...lock divider Prescaler S 13 bits Prescaler W 5 bits OSC1 OSC2 X1 X2 System clock pulse generator øOSC fOSC øOSC fOSC øW fW øW 2 øW 4 øSUB ø 2 to ø 8192 øW 8 ø øOSC 8 øOSC øOSC 16 øOSC 32 øOSC 64 øW 8 to øW 128 Subclock pulse generator Figure 5 1 Block Diagram of Clock Pulse Generators 5 1 2 System Clock and Subclock The basic clock signals that drive the CPU and on chip peripheral modules are ø an...

Page 92: ...lel resonance crystal resonator should be used 1 2 C1 C2 OSC OSC C C 12 pF 20 1 2 Figure 5 2 Typical Connection to Crystal Oscillator Figure 5 3 shows the equivalent circuit of a crystal oscillator An oscillator having the characteristics given in table 5 1 should be used CS C0 RS OSC1 OSC2 LS Figure 5 3 Equivalent Circuit of Crystal Oscillator Table 5 1 Crystal Oscillator Parameters Frequency 2 M...

Page 93: ...ning signal lines close to the oscillator circuit since the oscillator may be adversely affected by induction currents See figure 5 5 The board should be designed so that the oscillator and load capacitors are located as close as possible to pins OSC1 and OSC2 OSC1 OSC2 C1 C2 Signal A To be avoided Signal B Figure 5 5 Board Design of Oscillator Circuit External Clock Input Method Connect an extern...

Page 94: ...al oscillator as shown in figure 5 7 Follow the same precautions as noted under 5 2 Notes on Board Design X X C1 C2 1 2 C C 15 pF typ 1 2 Figure 5 7 Typical Connection to 32 768 kHz Crystal Oscillator Figure 5 8 shows the equivalent circuit of the 32 768 kHz crystal oscillator X1 X2 LS CS CO CO 1 5 pF typ RS 14 kΩ typ fW 32 768 kHz RS Note Constants are reference values Figure 5 8 Equivalent Circu...

Page 95: ... clock It is incremented once per clock period Prescaler S is initialized to H 0000 by a reset and starts counting on exit from the reset state In standby mode subactive mode and subsleep mode the system clock pulse generator stops Prescaler S also stops and is initialized to H 0000 The CPU cannot read or write prescaler S The output from prescaler S is shared by the on chip peripheral modules The...

Page 96: ... element stray capacitance in its interconnecting circuit and other factors Suitable constants should be determined in consultation with the oscillator element manufacturer Design the circuit so that the oscillator element never receives voltages exceeding its maximum rating 5 5 2 Notes on Board Design When using a crystal resonator ceramic resonator place the resonator and its load capacitors as ...

Page 97: ...heral modules are operable on the subclock The subclock frequency can be selected from øw 2 øw 4 and øw 8 Sleep mode The CPU halts On chip peripheral functions are operable on the system clock Subsleep mode The CPU halts On chip peripheral functions are operable on the subclock Standby mode The CPU and all on chip peripheral modules halt When the clock time base function is selcted timer A is oper...

Page 98: ...value 1 When a SLEEP instruction is executed in the active mode a transition is made to the standby mode Bits 6 to 4 Standby Timer Select 2 to 0 STS2 to STS0 These bits designate the time the CPU and peripheral modules wait for stable clock operation after exiting from the standby mode subactive mode or subsleep mode to the active mode or sleep mode due to an interrupt The designation should be ma...

Page 99: ...R W R W R W R W R W R W SYSCR2 is an 8 bit read write register for power down mode control Upon reset SYSCR2 is initialized to H 00 Bit 7 Sleep Mode Selection SMSEL This bit chooses the transition to the sleep mode or subsleep mode when the SLEEP instruction is executed The transition after the SLEEP instruction is executed depends on a combination of this and other control bits Bit 7 SMSEL Descri...

Page 100: ...active mode if LSON 0 or to subactive mode if LSON 1 Bits 4 to 2 Active Mode Clock Select MA2 to MA0 These bits select the operating clock frequency in the active and sleep modes The operating clock frequency changes to the set frequency after the SLEEP instruction is executed Bit 4 MA2 Bit 3 MA1 Bit 2 MA0 Description 0 øosc Initial value 1 0 0 øosc 8 1 øosc 16 1 0 øosc 32 1 øosc 64 Note Don t car...

Page 101: ...e standby state Bit 5 SCI3 Module Standby MSTS3 This bit enables SCI3 to enter the standby state Bit 5 MSTS3 Description 0 The SCI3 operates normally Initial value 1 The SCI3 enters the standby state Bit 4 A D Converter Module Standby MSTAD This bit enables the A D converter to enter the standby state Bit 4 MSTAD Description 0 The A D converter operates normally Initial value 1 The A D converter e...

Page 102: ...by state Bit 1 Timer V Module Standby MSTTV This bit enables timer V to enter the standby state Bit 1 MSTTV Description 0 Timer V operates normally Initial value 1 Timer V enters the standby state Bit 0 Timer A Module Standby MSTTA This bit enables timer A to enter the standby state Bit 0 MSTTA Description 0 Timer A operates normally Initial value 1 Timer A enters the standby state ...

Page 103: ...rupt SSBY 1 LSON 1 Direct transition interrupt SMSEL 1 LSON 0 Direct transition interrupt SMSEL 0 Notes 1 A transition between different modes cannot be made to occur simply because an interrupt request is generated Make sure that interrupt handling is performed after the interrupt is accepted 2 Details on the mode transition conditions are given in the explanation of each mode in sections 6 4 to ...

Page 104: ...rrupt 0 0 0 0 Sleep mode Active mode 1 Subactive mode 1 0 Subsleep mode Active mode 1 Subactive mode 1 Standby mode Active mode 1 0 1 0 Active mode 1 Subactive mode Notes Don t care 1 When state transition is performed while SMSEL is 1 timer V SCI3 and the A D converter are reset and all registers are set to their initial values To use these after entering active mode reset the registers ...

Page 105: ...ions 2 Functions 2 Functions 2 functions 3 Timer V Reset Reset Reset Timer W Retained 4 6 Retained 4 Retained Watchdog timer Retained 5 6 Retained 5 Retained 5 SCI3 Reset Reset Reset IIC Retained 6 Retained Retained A D converter Reset Reset Reset Notes 1 Register contents are retained but output is the high impedance state 2 Functions if the timekeeping time base function is selected and retained...

Page 106: ...ested interrupt is disabled in the interrupt enable register After the sleep mode is cleared a transition is made to active mode when the LSON bit in SYSCR2 is 0 and a transition is made to subactive mode when the bit is 1 When the RES pin goes low the CPU goes into the reset state and the sleep mode is cleared 6 5 Standby Mode 6 5 1 Transition to the Standby Mode The system goes from the active m...

Page 107: ...s the system clock pulse generator starts functioning the RES pin must be kept low until the pulse generator output stabilizes 6 5 3 Oscillator Settling Time after the Standby Mode is Cleared When a crystal oscillator is used Table 6 5 lists the settings for various operating frequencies Bits STS2 to STS0 in SYSCR1 must be set so that the waiting time is longer than the oscillator settling time Ta...

Page 108: ...y an interrupt or by input at the RES pin Clearing by interrupt When an interrupt is requested the subsleep mode is cleared and interrupt exception handling starts The subsleep mode is not cleared if the I bit of CCR is set to 1 or the requested interrupt is disabled in the interrupt enable register After the subsleep mode is cleared a transition is made to the active mode when the LSON bit in SYS...

Page 109: ...struction is executed in the subactive mode the subactive mode is cleared and another mode is entered If the SSBY bit in SYSCR1 and the DTON and SMSEL bits in SYSCR2 are cleared to 0 the sleep mode is entered if the SSBY bit in SYSCR1 the DTON bit in SYSCR2 are cleared to 0 and the SMSEL bit is set to 1 the subsleep mode is entered if the SSBY bit in SYSCR1 is set to 1 and the DTON bit in SYSCR2 i...

Page 110: ...nd MA0 bits in SYSCR2 6 8 2 Transition from the Active Mode to Other Modes A transition from the active mode to the standby mode takes place if the SLEEP instruction is executed while the SSBY bit in SYSCR1 is set to 1 and the DTON bit in SYSCR1 is cleared to 0 If the SLEEP instruction is executed while SSBY is cleared to 0 and the DTON and SMSEL bits in SYSCR2 are cleared to 0 the sleep mode is e...

Page 111: ...on is made to the subactive mode Direct transition from the subactive mode to the active mode When a SLEEP instruction is executed in the subactive mode while the DTON bit in SYSCR2 is set to 1 and the LSON bit in SYSCR2 is cleared to 0 a direct transition is made to the active mode after the waiting time set in SYSCR1 bits STS2 to STS0 has elapsed 6 9 1 Direct Transition Time Direct transition fr...

Page 112: ...interrupt exception handling states tcyc after transition 2 Example Direct transition time 2 1 8tw 8192 14 tosc 24tw 8206tosc when the CPU operating clock of øw 8 øosc and a waiting time of 8192 states are selected Symbols tosc OSC clock cycle time tw watch clock cycle time tcyc system clock ø cycle time tsubcyc subclock øSUB cycle time 6 10 Module Standby Mode The module standby mode can be set t...

Page 113: ...imes On board programming modes There are two modes in which flash memory can be programmed erased verified on board Boot mode User program mode Automatic bit rate adjustment With data transfer in boot mode the LSI s bit rate can be automatically adjusted to match the transfer bit rate of the host Protect modes The software protect mode is available in which protected status is designated for flas...

Page 114: ...R2 Internal address bus Internal data bus 16 bits Mode pin EBR1 FLER FLPWCR FLMCR1 Flash memory control register 1 Flash memory control register 2 Erase block register 1 Flash memory enable register Flash memory power control register Notation FLMCR1 FLMCR2 EBR1 FLER FLPWCR Figure 7 1 Block Diagram of Flash Memory ...

Page 115: ...epending on the state of the TEST pin the NMI pin and the port input level as shown in figure 7 2 The input level of the TEST pin and NMI pin must be stabilized at least four states before reset cancellation Boot mode On board programming mode User program mode User mode Reset state Programmer mode RES 0 SWE 1 SWE 0 Note Only make a transition between user mode and user program mode when the CPU i...

Page 116: ...tion of the programming control program is started Prepare the programming control program according to section 7 6 Programming erasing Flash Memory Program In user program mode control branches from the user mode to the programming control program prepared by the user desired blocks can be erased and programmed in this mode The user must set the branch condition and prepare the means for providin...

Page 117: ...program transfer When boot mode is entered the boot program in the H8 3664 originally incorporated in the chip is started and the programming control program in the host is transferred to RAM via SCI communication The boot program required for flash memory erasing is automatically transferred to the RAM boot program area 3 Flash memory initialization The erase program in the boot program area in R...

Page 118: ...am should be prepared in the host or in the flash memory 2 Programming erase control program transfer When user program mode is entered user software confirms this fact executes transfer program in the flash memory and transfers the programming erase control program to RAM 3 Flash memory initialization The programming erase program in RAM is executed and the flash memory is initialized to H FF Era...

Page 119: ...Configuration The flash memory is controlled by means of the pins shown in table 7 1 Table 7 1 Pin Configuration Pin Name Abbreviation I O Function Reset RES Input Reset Mode TEST Input Sets LSI operating mode Port PB0 PB0 Input Sets LSI operating mode when TEST 1 Port PB1 PB1 Input Sets LSI operating mode when TEST 1 Port PB2 PB2 Input Sets LSI operating mode when TEST 1 Transmit data TxD Output ...

Page 120: ...ry Control Register 1 FLMCR1 FLMCR1 is an 8 bit register used for flash memory operating mode control Program verify mode or erase verify mode is entered by setting the SWE bit to 1 then setting the PV or EV bit Program mode is entered by setting the SWE bit to 1 then setting the PSU bit and finally setting the P bit Erase mode is entered by setting the SWE bit to 1 then setting the ESU bit and fi...

Page 121: ...r P bit at the same time Bit 4 PSU Description 0 Program setup cleared Initial value 1 Program setup Setting condition When SWE 1 Bit 3 Erase Verify EV Selects erase verify mode transition or clearing Do not set the SWE ESU PSU PV E or P bit at the same time Bit 3 EV Description 0 Erase verify mode cleared Initial value 1 Transition to erase verify mode Setting condition When SWE 1 Bit 2 Program V...

Page 122: ... Transition to program mode Setting condition When SWE 1 and PSU 1 7 3 2 Flash Memory Control Register 2 FLMCR2 FLMCR2 is an 8 bit register used for indicating flash memory program erase status FLMCR2 is initialized to H 00 by a power on reset or is initialized in standby mode Bit 7 6 5 4 3 2 1 0 FLER Initial value 0 0 0 0 0 0 0 0 Read Write R R R R R R R R Note FLMCR2 is a read only register and ...

Page 123: ...he flash memory erase area block by block EBR1 is initialized to H 00 by a power on reset or in standby mode or when the SWE bit in FLMCR1 is 0 When a bit in EBR1 is set to 1 the corresponding block can be erased Other blocks are erase protected Do not set more than one bit as this will cause all the bits in EBR1 to be automatically cleared to 0 The flash memory erase blocks are shown in table 7 3...

Page 124: ...emory Enable Register FENR Bit 7 6 5 4 3 2 1 0 FLSHE Initial value 0 0 0 0 0 0 0 0 Read Write R W FENR is an 8 bit readable writable register that controls on chip flash memory FENR is initialized to H 00 by a reset or in standby mode Bit 7 Flash Memory Control Register Enable FLSHE Controls CPU access to the flash memory control registers FLMCR1 FLMCR2 EBR1 and FLPWCR Setting the FLSHE bit to 1 e...

Page 125: ...rogramming control program is started When the control branches to the programming control program SCI3 terminates the transmission receive operation RE and TE of SCR are 0 However since the bit rate of SCI3 that has been set is retained SCI3 can be used continuously for transmission receive of programming data or verify data The TxD pin is in the high level output state PCR22 PDR22 1 The values o...

Page 126: ... to host as verify data echo back Host transmits programming control program sequentially in byte units H8 3664 transmits received programming control program to host as verify data echo back Transfer received programming control program to on chip RAM End of transmission Check flash memory data and if data has already been written erase all blocks After confirming that all flash memory data has b...

Page 127: ...peat the above operations Depending on the host s transmission bit rate and the LSI s system clock frequency there will be a discrepancy between the bit rates of the host and the LSI Set the host transfer bit rate and the system clock frequencies within the range shown in Table 7 4 Table 7 4 shows host transfer bit rates and system clock frequencies for which automatic adjustment of the LSI bit ra...

Page 128: ...waiting at least 20 states then setting the TEST pin and NMI pin and executing reset release Boot mode can also be cleared by a WDT overflow reset 4 If the TEST pin input levels are changed for example from low to high during a reset the state of ports will change according to the change in the microcomputer s operating mode Therefore care must be taken to make pin settings to prevent these pins f...

Page 129: ...Write the transfer program and the program erase control program if necessary beforehand Figure 7 8 User Program Mode Execution Procedure 7 6 Programming Erasing Flash Memory A software method using the CPU is employed to program and erase flash memory in the on board programming modes There are flash memory operating modes program mode program verify mode erase mode and erase verify mode Transiti...

Page 130: ...e a 128 byte program data area 128 byte reprogram data area and 128 byte additional program data area in RAM Refer to tables 7 5 and 7 6 for reprogram data and additional program data computation 4 Write 128 bytes successively in byte units from the reprogram data area or additional program data area to flash memory The program address and 128 byte data are latched in the flash memory The lower 8 ...

Page 131: ...sively write 128 byte reprogram data from reprogram data area in RAM to flash memory Write pulse application Store 128 bytes of program data in program data area and reprogram data area Verify address block start address PV bit 0 Wait 2 µs Reprogram data computation Successively write 128 byte data from additional program data area in RAM to flash memory n n 1 n 1000 End PSU bit 1 Enable WDT P bit...

Page 132: ... 7 6 Additional Program Data Computation Table Reprogram Data Verify Data Additional Program Data Comments 0 0 0 Additional program bit 0 1 1 No additional programming 1 0 1 No additional programming 1 1 1 No additional programming Table 7 7 Programming Time n Number of Writes Programming Time In Additional Programming Comments 1 to 6 30 10 7 to 1 000 200 Note Time shown in µs ...

Page 133: ...d format from the address on which the dummy write was executed 6 If the read data is unerased set erase mode again and repeat the erase erase verify sequence as before However ensure that this sequence is not repeated more than 100 times 7 6 3 Interrupts during Flash Memory Programming Erasing For the following reasons all interrupts including NMI should be disabled when flash memory is being pro...

Page 134: ...address of block Erase failure Wait 100 µs SWE bit 0 SWE bit 0 No No No Yes Yes Yes Yes No n n 1 Wait 100 µs E bit 1 Wait 10 ms E bit 0 Wait 10 µs ESU bit 0 Wait 10 µs Disable WDT EV bit 1 Wait 20 µs Verify address block start address H FF dummy write to verify address End of erasing of all erase blocks Increment address ESU bit 1 n 100 Figure 7 10 Erase Erase Verify Flowchart ...

Page 135: ...ntrol register 2 FLMCR2 and erase block register 1 EBR1 Table 7 8 Hardware Protection Functions Item Description Program Erase Reset standby protection In a power on reset including a WDT power on reset and in standby mode FLMCR1 FLMCR2 and EBR1 are initialized and the program erase protected state is entered In a reset via the RES pin the reset state is not entered unless the RES pin is held low ...

Page 136: ...ccurs during flash memory programming erasing or operation is not performed in accordance with the program erase algorithm and the program erase operation is forcibly aborted Aborting the program erase operation prevents damage to the flash memory due to overprogramming or overerasing If the CPU malfunctions during flash memory programming erasing the FLER bit is set to 1 in FLMCR2 and the error p...

Page 137: ... 11 Flash Memory State Transitions 7 8 Interrupt Handling when Programming Erasing Flash Memory All interrupts including NMI interrupt is disabled when flash memory is being programmed or erased when the P or E bit is set in FLMCR1 and while the boot program is executing There are three reasons for this 1 Interrupt during programming or erasing might cause a violation of the programming or erasing...

Page 138: ...tabilization period must be provided when returning to normal operation When the flash memory returns to its normal operating state from a power down state bits STS2 to STS0 in SBYCR must be set to provide a wait time of at least 20 µs including when using an external clock Table 7 10 Flash Memory Operating States Flash Memory Operating State LSI Operating State When PDWND 0 Initial value When PDW...

Page 139: ...ngs Mode pins TEST High level input to TEST Mode setting pins PB2 PB1 PB0 Low level input to PB2 PB1 and PB0 RES pin Power on reset circuit OSC2 OSC1 Oscillator circuit 7 10 1 Socket Adapter Pin Correspondence Diagram Connect the socket adapter to the chip as shown in figure 7 12 This will enable conversion to a 32 pin arrangement The on chip ROM memory map is shown in figure 7 12 and the socket a...

Page 140: ... OPEN HN28F101 32 Pins Pin No Pin Name 1 26 2 3 31 13 14 15 17 18 19 20 21 12 11 10 9 8 7 6 5 27 24 23 25 4 28 29 22 32 16 FWE A9 A16 A15 WE I O0 I O1 I O2 I O3 I O4 I O5 I O6 I O7 A0 A1 A2 A3 A4 A5 A6 A7 A8 OE A10 A11 A12 A13 A14 CE VCC VSS 21 30 44 36 37 38 39 40 41 42 43 23 51 52 53 54 13 14 19 20 45 22 26 27 28 29 46 8 35 59 3 12 5 9 6 60 61 62 10 11 7 Power on reset circuit Oscillator circuit...

Page 141: ...g of the entire flash memory Status polling is used to confirm the end of auto programming Status Read Mode Status polling is used for auto programming and auto erasing and normal termination can be confirmed by reading the I O6 signal In status read mode error information is output if an error occurs Table 7 12 Settings for Various Operating Modes In Programmer Mode Pin Names Mode CE OE WE I O7 I...

Page 142: ...read operations a transition is made to the command wait state When reading memory contents a transition to memory read mode must first be made with a command write after which the memory contents are read 2 In memory read mode command writes can be performed in the same way as in the command wait state 3 Once memory read mode has been entered consecutive reads can be performed 4 After powering on...

Page 143: ...ry Read after Memory Write Table 7 15 AC Characteristics in Transition from Memory Read Mode to Another Mode Conditions VCC 5 0 V 0 5 V VSS 0 V Ta 25 C 5 C Item Symbol Min Max Unit Notes Command write cycle tnxtc 20 µs Figure 7 15 CE hold time tceh 0 ns CE setup time tces 0 ns Data hold time tdh 50 ns Data setup time tds 50 ns Write pulse width twep 70 ns WE rise time tr 30 ns WE fall time tf 30 n...

Page 144: ...r Mode Table 7 16 AC Characteristics in Memory Read Mode Conditions VCC 5 0 V 0 5 V VSS 0 V Ta 25 C 5 C Item Symbol Min Max Unit Notes Access time tacc 20 µs Figure 7 16 CE output delay time tce 150 ns Figure 7 17 OE output delay time toe 150 ns Output disable delay time tdf 100 ns Data output hold time toh 5 ns CE A15 A0 OE WE I O7 I O0 tacc tacc toh toh Address stable Address stable Figure 7 16 ...

Page 145: ...bits of the transfer address must be low If a value other than an effective address is input processing will switch to a memory write operation but a write error will be flagged 6 Memory address transfer is performed in the second cycle figure 7 18 Do not perform transfer after the third cycle 7 Do not perform a command write during a programming operation 8 Perform one auto program operation for ...

Page 146: ...twep 70 ns Status polling start time twsts 1 ms Status polling access time tspa 150 ns Address setup time tas 0 ns Address hold time tah 60 ns Memory write time twrite 1 3000 ms WE rise time tr 30 ns WE fall time tf 30 ns CE A15 A0 OE WE I O7 I O6 I O5 I O0 twep tds tdh tf tr tas tah twsts twrite tspa tces tceh tnxtc tnxtc Address stable H 40 H 00 Data transfer 1 to 128 bytes Write operation end d...

Page 147: ...ntil the next command write As long as the next command write has not been performed reading is possible by enabling CE and OE Table 7 18 AC Characteristics in Auto Erase Mode Conditions VCC 5 0 V 0 5 V VSS 0 V Ta 25 C 5 C Item Symbol Min Max Unit Notes Command write cycle tnxtc 20 µs Figure 7 19 CE hold time tceh 0 ns CE setup time tces 0 ns Data hold time tdh 50 ns Data setup time tds 50 ns Writ...

Page 148: ...15 A0 OE WE I O7 I O6 I O5 I O0 twep tds tdh tf tr tests terase tspa tces tceh tnxtc tnxtc H 20 H 20 H 00 Erase end decision signal Erase normal end decision signal Figure 7 19 Auto Erase Mode Timing Waveforms ...

Page 149: ...0 V Ta 25 C 5 C Item Symbol Min Max Unit Notes Read time after command write tnxtc 20 µs Figure 7 20 CE hold time tceh 0 ns CE setup time tces 0 ns Data hold time tdh 50 ns Data setup time tds 50 ns Write pulse width twep 70 ns OE output delay time toe 150 ns Disable delay time tdf 100 ns CE output delay time tce 150 ns WE rise time tr 30 ns WE fall time tf 30 ns CE A15 A0 OE WE I O7 I O0 twep tf ...

Page 150: ...tatus in auto program auto erase mode 2 The I O6 status polling flag indicates a normal or abnormal end in auto program auto erase mode Table 7 21 Status Polling Output Truth Table Pin Name During Internal Operation Abnormal End Normal End I O7 0 1 0 1 I O6 0 0 1 1 I O0 I O5 0 0 0 0 7 10 8 Programmer Mode Transition Time Commands cannot be accepted during the oscillation stabilization period or th...

Page 151: ...de on a chip that has been programmed erased in an on board programming mode auto erasing is recommended before carrying out auto programming Notes 1 The flash memory is initially in the erased state when the device is shipped by Hitachi For other chips for which the erasure history is unknown it is recommended that auto erasing be executed to check and supplement the initialization erase level 2 ...

Page 152: ...136 ...

Page 153: ...a bus allowing high speed 2 state access for both byte data and word data 8 1 1 Block Diagram Figure 8 1 shows a block diagram of the on chip RAM H FF7E H FF7F Internal data bus upper 8 bits Internal data bus lower 8 bits Even numbered address Odd numbered address H FF7E H FB82 H FB80 H FB80 H FB82 H FB81 H FB83 On chip RAM Figure 8 1 RAM Block Diagram ...

Page 154: ...138 ...

Page 155: ...ontrol register PCR that controls input and output and a port data register PDR for storing output data Input or output can be assigned to individual bits See section 2 9 2 Notes on Bit Manipulation for information on executing bit manipulation instructions to write data in PCR or PDR Pin states in each operation mode are given in Appendix D Port States in the Different Processing State ...

Page 156: ...9 1 Port 1 Pin Configuration 9 2 2 Register Configuration and Description Table 9 1 shows the port 1 register configuration Table 9 1 Port 1 Registers Name Abbrev R W Initial Value Address Port data register 1 PDR1 R W H 08 H FFD4 Port control register 1 PCR1 W H 00 H FFE4 Port pull up control register 1 PUCR1 R W H 08 H FFD0 Port mode register 1 PMR1 R W H 0C H FFE0 ...

Page 157: ...15 PCR14 PCR12 PCR11 PCR10 Initial value 0 0 0 0 0 0 0 0 Read Write W W W W W W W PCR1 is an 8 bit register for controlling whether each of the port 1 pins P17 to P14 and P12 to P10 functions as an input pin or output pin Setting a PCR1 bit to 1 makes the corresponding pin an output pin while clearing the bit to 0 makes the pin an input pin The settings in PCR1 and in PDR1 are valid only when the ...

Page 158: ...ons for ports 1 and 2 pins Upon reset PMR1 is initialized to H 0C Bit 7 P17 IRQ3 TRGV Pin Function Switch IRQ3 This bit selects whether pin P17 IRQ3 TRGV is used as P17 or as IRQ3 TRGV Bit 7 IRQ3 Description 0 Functions as P17 I O pin Initial value 1 Functions as IRQ3 TRGV input pin Note Rising or falling edge sensing can be designated for IRQ3 Rising falling or both edge sensing can be designated...

Page 159: ... I O pin Initial value 1 Functions as IRQ0 output pin Bit 3 Reserved Bit Bit 3 is reserved it is always read as 1 and cannot be modified Bit 2 Reserved Bit Bit 2 is reserved it is always read as 1 and cannot be modified Bit 1 P22 TXD Pin Function Switch TXD This bit selects whether pin P22 TXD is used as P22 or as TXD Bit 1 TXD Description 0 Functions as P22 I O pin Initial value 1 Functions as TX...

Page 160: ... input pin P16 IRQ2 P15 IRQ1 P14 IRQ0 The pin function depends on bits IRQ2 and IRQ1 in PMR1 and bit PCR1n in IRQ0 and PCR1 m n 4 n 6 5 4 IRQm 0 1 PCR1n 0 1 Pin function P1n input pin P1n output pin IRQm input pin P12 The pin function depends on bit PCR1n in PCR1 P11 PCR1n 0 1 Pin function P1n input pin P1n output pin P10 TMOW The pin function depends on bit TMOW in PMR1 and bit PCR10 in PCR1 TMOW...

Page 161: ...e controlled by software When a PCR1 bit is cleared to 0 setting the corresponding PUCR1 bit to 1 turns on the MOS input pull up for that pin The MOS input pull up function is in the off state after a reset PCR1n 0 1 PUCR1n 0 1 MOS input pull up Off On Off n 7 to 4 2 to 0 Note Don t care ...

Page 162: ... F8 H FFD5 Port control register 2 PCR2 W H 00 H FFE5 9 3 3 Port Data Register 2 PDR2 Bit 7 6 5 4 3 2 1 0 P22 P21 P20 Initial value 1 1 1 1 1 0 0 0 Read Write R W R W R W Note Bits 7 to 3 are reserved they are always read as 1 and cannot be modified PDR2 is an 8 bit register that stores data for port 2 pins P22 to P20 If port 2 is read while PCR2 bits are set to 1 the values stored in PDR2 are rea...

Page 163: ...1 pins P22 to P20 functions as an input pin or output pin Setting a PCR2 bit to 1 makes the corresponding pin an output pin while clearing the bit to 0 makes the pin an input pin The settings in PCR2 and PDR2 are valid only when the corresponding pin is designated in SCR3 as a general I O pin Upon reset PCR2 is initialized to H 00 PCR2 is a write only register which is always read as all 1s ...

Page 164: ...Pin function P22 input pin P22 output pin TXD output pin P21 RXD The pin function depends on bit RE in SCR3 and bit PCR21 in PCR2 RE 0 1 PCR21 0 1 Pin function P21 input pin P21 output pin RXD input pin P20 SCK3 The pin function depends on bits CKE1 and CKE0 in SCR3 bit COM in SMR and bit PCR20 in PCR2 CKE1 0 1 CKE0 0 1 COM 0 1 PCR20 0 1 Pin function P20 input pin P20 output pin SCK3 output pin SC...

Page 165: ...Figure 9 3 Port 5 Pin Configuration 9 4 2 Register Configuration and Description Table 9 5 shows the port 5 register configuration Table 9 5 Port 5 Registers Name Abbrev R W Initial Value Address Port data register 5 PDR5 R W H 00 H FFD8 Port control register 5 PCR5 W H 00 H FFE8 Port pull up control register 5 PUCR5 R W H 00 H FFD1 Port mode register 5 PMR5 R W H 00 H FFE1 ...

Page 166: ...are cleared to 0 the pin states are read Upon reset PDR5 is initialized to H 00 9 4 4 Port Control Register 5 PCR5 Bit 7 6 5 4 3 2 1 0 PCR57 PCR56 PCR55 PCR54 PCR53 PCR52 PCR51 PCR50 Initial value 0 0 0 0 0 0 0 0 Read Write W W W W W W W W PCR5 is an 8 bit register for controlling whether each of the port 5 pins P57 to P50 functions as an input pin or output pin Setting a PCR5 bit to 1 makes the c...

Page 167: ... clearing the bit to 0 turns off the MOS pull up Upon reset PUCR5 is initialized to H 00 9 4 6 Port Mode Register 5 PMR5 Bit 7 6 5 4 3 2 1 0 WKP5 WKP4 WKP3 WKP2 WKP1 WKP0 Initial value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W PMR5 is an 8 bit read write register controlling the selection of pin functions for port 5 pins Upon reset PMR5 is initialized to H 00 Bit n P5n WKPn Pin Function S...

Page 168: ...direct bus driving is enabled P56 SDA The pin function depends on bit PCR56 in PCR5 and bit ICE in I2C ICE 0 1 PCR56 0 1 Pin function P56 input pin P56 output pin SDA I O pin The SDA output format is NMOS open drain and direct bus driving is enabled P55 WKP5 The pin function depends on bit PCR55 in PCR5 and bit WKP5 in PMR5 ADTRG WKP5 0 1 PCR55 0 1 Pin function P55 input pin P55 output pin WKP5 in...

Page 169: ...that can be controlled by software When a PCR5 bit is cleared to 0 setting the corresponding PUCR5 bit to 1 turns on the MOS pull up for that pin The MOS pull up function is in the off state after a reset PCR5n 0 1 PUCR5n 0 1 MOS input pull up Off On Off n 5 to 0 Note Don t care ...

Page 170: ...8F H FFDA Port control register 7 PCR7 W H 00 H FFEA 9 5 3 Port Data Register 7 PDR7 Bit 7 6 5 4 3 2 1 0 P76 P75 P74 Initial value 1 0 0 0 1 1 1 1 Read Write R W R W R W Note Bits 7 and 3 to 0 are reserved they are always read as 1 and cannot be modified PDR7 is an 8 bit register that stores data for port 7 pins P76 to P74 If port 7 is read while PCR7 bits are set to 1 the values stored in PDR7 ar...

Page 171: ...write only register which always reads as all 1s 9 5 5 Pin Functions Table 9 8 shows the port 7 pin functions Table 9 8 Port 7 Pin Functions Pin Pin Functions and Selection Method P76 TMOV The pin function depends on bit PCR76 in PCR7 and bits OS3 to OS0 in TCSRV OS3 to OS0 0000 Not 0000 PCR76 0 1 Pin function P76 input pin P76 output pin TMOV output pin P75 TMCIV The pin function depends on bit P...

Page 172: ...TIOC P82 FTIOB P81 FTIOA P80 FTCI Port 8 Figure 9 5 Port 8 Pin Configuration 9 6 2 Register Configuration and Description Table 9 9 shows the port 8 register configuration Table 9 9 Port 8 Registers Name Abbrev R W Initial Value Address Port data register 8 PDR8 R W H 00 H FFDB Port control register 8 PCR8 W H 00 H FFEB ...

Page 173: ...s are cleared to 0 the pin states are read Upon reset PDR8 is initialized to H 00 9 6 4 Port Control Register 8 PCR8 Bit 7 6 5 4 3 2 1 0 PCR87 PCR86 PCR85 PCR84 PCR83 PCR82 PCR81 PCR80 Initial value 0 0 0 0 0 0 0 0 Read Write W W W W W W W W PCR8 is an 8 bit register for controlling whether each of the port 8 pins P87 to P80 functions as an input or output pin Setting a PCR8 bit to 1 makes the cor...

Page 174: ...e pin function depends on bit PCR86 in PCR8 PCR86 0 1 Pin function P86 input pin P86 output pin P85 The pin function depends on bit PCR85 in PCR8 PCR85 0 1 Pin function P85 input pin P85 output pin P84 FTIOD The pin function depends on bit PCR84 in PCR8 and bit TIOR1 in timer W Timer W Setting 2 1 2 IOD2 0 1 IOD1 0 0 1 IOD0 0 1 Timer W Setting 1 above 2 above PCR84 0 1 Pin function FTIOD output P8...

Page 175: ...0 0 1 Timer W Setting 1 above 2 above PCR83 0 1 Pin function FTIOC output P83 input pin P83 output pin pin FTIOC input pin P82 FTIOB The pin function depends on bit PCR82 in PCR8 and bit TIOR0 in timer W Timer W Setting 2 1 2 IOB2 0 1 IOB1 0 0 1 IOB0 0 1 Timer W Setting 1 above 2 above PCR82 0 1 Pin function FTIOB output P82 input pin P82 output pin pin FTIOB input pin ...

Page 176: ... TIOR0 in timer W Timer W Setting 2 1 2 IOA2 0 1 IOA1 0 0 1 IOA0 0 1 Timer W Setting 1 above 2 above PCR81 0 1 Pin function FTIOA output P81 input pin P81 output pin pin FTIOA input pin P80 FTCI The pin function depends on bit PCR80 in PCR8 PCR80 0 1 Pin function P80 input pin P80 output pin FTCI input pin ...

Page 177: ...ration and Description Table 9 11 shows the port B register configuration Table 9 11 Port B Register Name Abbrev R W Address Port data register B PDRB R H FFDD 9 7 3 Port Data Register B PDRB Bit 7 6 5 4 3 2 1 0 PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 Read Write R R R R R R R R Reading PDRB always gives the pin states However if a port B pin is selected as an analog input channel by the A D converter s AD...

Page 178: ...7 4 Pin Functions Table 9 12 shows the port B pin functions Table 9 12 Port B Pin Functions Pin Pin Functions and Selection Method PBn ANn Always as below n 7 to 0 Pin function PBn input pin or ANn input pin ...

Page 179: ...he TMOW pin 10 1 1 Features Features of timer A are given below Choice of eight internal clock sources ø 8192 ø 4096 ø 2048 ø 512 ø 256 ø 128 ø 32 ø 8 Choice of four overflow periods 1 s 0 5 s 0 25 s 31 25 ms when timer A is used as a clock time base using a 32 768 kHz crystal oscillator An interrupt is requested when the counter overflows Any of eight clock signals can be output from pin TMOW 32 ...

Page 180: ...er A TCA Timer counter A IRRTA Timer A overflow interrupt request flag PSW Prescaler W PSS Prescaler S Note Can be selected only when the prescaler W output øW 128 is used as the TCA input clock Internal data bus Figure 10 1 Block Diagram of Timer A 10 1 3 Pin Configuration Table 10 1 shows the timer A pin configuration Table 10 1 Pin Configuration Name Abbrev I O Function Clock output TMOW Output...

Page 181: ... read write register for selecting the prescaler input clock and output clock Upon reset TMA is initialized to H 10 Bits 7 to 5 Clock Output Select TMA7 to TMA5 Bits 7 to 5 choose which of eight clock signals is output at the TMOW pin The system clock divided by 32 16 8 or 4 can be output in active mode and sleep mode A 32 768 kHz signal divided by 32 16 8 or 4 can be output in active mode sleep m...

Page 182: ...W 0 03125 s 1 0 0 PSW and TCA are reset 1 1 0 1 10 2 2 Timer Counter A TCA Bit 7 6 5 4 3 2 1 0 TCA7 TCA6 TCA5 TCA4 TCA3 TCA2 TCA1 TCA0 Initial value 0 0 0 0 0 0 0 0 Read Write R R R R R R R R TCA is an 8 bit read only up counter which is incremented by internal clock input The clock source for input to this counter is selected by bits TMA3 to TMA0 in timer mode register A TMA TCA values can be rea...

Page 183: ...imer A functions as an interval timer that generates an overflow output at intervals of 256 input clock pulses Note For details on interrupts see 3 3 Interrupts 10 3 2 Clock Time Base Operation When bit TMA3 in TMA is set to 1 timer A functions as a clock time base by counting clock signals output by prescaler W The overflow period of timer A is set by bits TMA1 and TMA0 in TMA A choice of four pe...

Page 184: ...d Halted Halted Halted Clock time base Reset Functions Functions Functions Functions Halted Halted TMA Reset Functions Retained Functions Retained Retained Retained Note When the clock time base function is selected as the internal clock of TCA in active mode or sleep mode the internal clock is not synchronous with the system clock so it is synchronized by a synchronizing circuit This may result i...

Page 185: ...of timer V are given below Choice of six internal clock sources ø 128 ø 64 ø 32 ø 16 ø 8 ø 4 or an external clock can be used as an external event counter Counter can be cleared by compare match A or B or by an external reset signal If the count stop function is selected the counter can be halted when cleared Timer output is controlled by two independent compare match signals enabling pulse output...

Page 186: ... TCRV0 Interrupt request control TCSRV CMIA CMIB OVI Internal data bus Notation TCORA Time constant register A TCORB Time constant register B TCNTV Timer counter V TCSRV Timer control status register V TCRV0 Timer control register V0 TCRV1 Timer control register V1 PSS Prescaler S CMIA Compare match interrupt A CMIB Compare match interrupt B OVI Overflow interupt Figure 11 1 Block Diagram of Timer...

Page 187: ...ger input to initiate counting 11 1 4 Register Configuration Table 11 2 shows the register configuration of timer V Table 11 2 Timer V Registers Name Abbrev R W Initial Value Address Timer control register V0 TCRV0 R W H 00 H FFA0 Timer control status register V TCSRV R W H 10 H FFA1 Time constant register A TCORA R W H FF H FFA2 Time constant register B TCORB R W H FF H FFA3 Timer counter V TCNTV...

Page 188: ... TCNTV is initialized to H 00 upon reset and in standby mode subsleep mode and subactive mode 11 2 2 Time Constant Registers A and B TCORA TCORB Bit 7 6 5 4 3 2 1 0 TCORn7 TCORn6 TCORn5 TCORn4 TCORn3 TCORn2 TCORn1 TCORn0 Initial value 1 1 1 1 1 1 1 1 Read Write R W R W R W R W R W R W R W R W n A or B TCORA and TCORB are 8 bit read write registers TCORA and TCNTV are compared at all times except d...

Page 189: ...ed from CMFB when CMFB is set to 1 in TCSRV Bit 7 CMIEB Description 0 Interrupt request CMIB from CMFB disabled Initial value 1 Interrupt request CMIB from CMFB enabled Bit 6 Compare Match Interrupt Enable A CMIEA Bit 6 enables or disables the interrupt request CMIA generated from CMFA when CMFA is set to 1 in TCSRV Bit 6 CMIEA Description 0 Interrupt request CMIA from CMFA disabled Initial value ...

Page 190: ... to 0 and bit ICKS0 in TCRV1 select the clock input to TCNTV Six internal clock sources divided from the system clock ø can be selected The counter increments on the falling edge If the external clock is selected there is a further selection of incrementing on the rising edge falling edge or both edges If TRGE is cleared to 0 after TCNTV is cleared it continues counting up TCRV0 TCRV1 Bit 2 CKS2 B...

Page 191: ...t 7 is a status flag indicating that TCNTV has matched TCORB This flag is set by hardware and cleared by software It cannot be set by software Bit 7 CMFB Description 0 Clearing conditions After reading CMFB 1 cleared by writing 0 to CMFB Initial value 1 Setting conditions Set when the TCNTV value matches the TCORB value Bit 6 Compare Match Flag A CMFA Bit 6 is a status flag indicating that TCNTV h...

Page 192: ...CORA or TCORB OS3 and OS2 select the output level for compare match B OS1 and OS0 select the output level for compare match A The two levels can be controlled independently If two compare matches occur simultaneously any conflict between the settings is resolved according to the following priority order toggle output 1 output 0 output When OS3 to OS0 are all cleared to 0 timer output is disabled A...

Page 193: ...ng edge is selected 1 Rising and falling edges are both selected Bit 2 TRGV Input Enable TRGE Bit 2 enables TCNTV counting to be triggered by input at the TRGV pin and enables TCNTV counting to be halted when TCNTV is cleared by compare match TCNTV stops counting when TRGE is set to 1 then starts counting when the edge selected by bits TVEG1 and TVEG0 is input at the TRGV pin Bit 2 TRGE Descriptio...

Page 194: ... or CMFB bit is set to 1 in TCSRV If CMIEA or CMIEB is set to 1 in TCRV0 a CPU interrupt is requested At the same time the output level selected by bits OS3 to OS0 in TCSRV is output from the TMOV pin When TCNT overflows from H FF to H 00 if OVIE is 1 in TCRV0 a CPU interrupt is requested If bits CCLR1 and CCLR0 in TCRV0 are set to 01 clear by compare match A or 10 clear by compare match B TCNTV i...

Page 195: ... Clock External clock Incrementation on the rising edge falling edge or both edges of the external clock can be selected by bits CKS2 to CKS0 in TCRV0 The external clock pulse width should be at least 1 5 system clocks ø when a single edge is counted and at least 2 5 system clocks when both edges are counted Shorter pulses will not be counted correctly Figure 11 3 shows the timing when both the ri...

Page 196: ... or CMFB is set to 1 when TCNTV matches TCORA or TCORB The internal compare match signal is generated in the last state in which the values match when TCNTV changes from the matching value to a new value Accordingly when TCNTV matches TCORA or TCORB the compare match signal is not generated until the next clock input to TCNTV Figure 11 5 shows the timing N N N 1 ø TCNTV TCORA or TCORB Compare matc...

Page 197: ...ure 11 6 shows the timing when the output is toggled by compare match A ø Compare match A signal Timer V output pin Figure 11 6 TMOV Output Timing TCNTV Clear Timing by Compare Match TCNTV can be cleared by compare match A or B as selected by bits CCLR1 and CCLR0 in TCRV0 Figure 117 shows the timing N H 00 ø Compare match A signal TCNTV Figure 11 7 Clear Timing by Compare Match ...

Page 198: ...ates Operation Mode Reset Active Sleep Sub active Sub sleep Standby TCNTV Reset Functions Functions Reset Reset Reset TCRV0 TCRV1 Reset Functions Functions Reset Reset Reset TCORA TCORB Reset Functions Functions Reset Reset Reset TCSRV Reset Functions Functions Reset Reset Reset 11 3 2 Interrupt Sources Timer V has three interrupt sources CMIA CMIB and OVI Table 11 4 lists the interrupt sources an...

Page 199: ... and set bit CCLR0 to 1 in TCRV0 so that TCNTV will be cleared by compare match with TCORA Set bits OS3 to OS0 to 0110 in TCSRV so that the output will go to 1 at compare match with TCORA and to 0 at compare match with TCORB Set bits CKS2 to CKS0 in TCRV0 and bit ICKS0 in TCRV1 to select the desired clock source With these settings a waveform is output without further software intervention with a ...

Page 200: ...A and to 0 at compare match with TCORB Set bits TVEG1 and TVEG0 to 10 in TCRV1 and set TRGE to 1 to select the falling edge of the TRGV input Set bits CKS2 to CKS0 in TCRV0 and bit ICKS0 in TCRV1 to select the desired clock source After these settings a pulse waveform will be output without further software intervention with a delay determined by TCORA from the TRGV input and a pulse width determi...

Page 201: ...f a TCNTV clear signal is generated in the T3 state of a TCNTV write cycle clearing takes precedence and the write to the counter is not carried out Figure 11 11 shows the timing ø Address TCNTV address TCNTV write cycle by CPU Internal write signal Counter clear signal TCNTV N H 00 T1 T2 T3 Figure 11 11 Contention between TCNTV Write and Clear ...

Page 202: ...e T3 state of a TCNTV write cycle the write takes precedence and the counter is not incremented Figure 11 12 shows the timing ø Address TCNTV address TCNTV write cycle by CPU Internal write signal TCNTV clock TCNTV N M TCNTV write data T1 T2 T3 Figure 11 12 Contention between TCNTV Write and Increment ...

Page 203: ...le the write to TCORA or TCORB takes precedence and the compare match signal is inhibited Figure 11 13 shows the timing ø Address TCORA address Internal write signal TCNTV TCORA N N N 1 M TCORA write data Inhibited T1 T2 T3 TCORA write cycle by CPU Compare match signal Figure 11 13 Contention between TCORA Write and Compare Match ...

Page 204: ...CNTV may be incremented by a switch between different internal clock sources Table 11 5 shows the relation between internal clock switchover timing by writing to bits CKS1 and CKS0 and TCNTV operation When TCNTV is internally clocked an increment pulse is generated from the falling edge of an internal clock signal which is divided from the system clock ø For this reason in a case like No 3 in tabl...

Page 205: ...Modifying Bits CKS1 and CKS0 TCNTV Operation 1 Goes from low level to low level 1 Clock before switching Clock after switching Count clock TCNTV N N 1 Write to CKS1 and CKS0 2 Goes from low to high 2 Clock before switching Clock after switching Count clock TCNTV N N 1 N 2 Write to CKS1 and CKS0 ...

Page 206: ...from high to high Clock before switching Clock after switching Count clock TCNTV N N 1 Write to CKS1 and CKS0 N 2 Notes 1 Including a transition from the low level to the stopped state or from the stopped state to the low level 2 Including a transition from the stopped state to the high level 3 Including a transition from the high level to the stopped state 4 The switchover is seen as a falling ed...

Page 207: ...output compare or input capture functions Four general registers usable as two pairs of registers one register of each pair operates as a buffer for the output compare or input capture register Four selectable operating modes Waveform output by compare match Selection of 0 output 1 output or toggle output Input capture function Rising edge falling edge or both edges selectable Counter clearing fun...

Page 208: ...r register for GRA in buffer mode GRD buffer register for GRB in buffer mode Counter clearing function GRA compare match GRA compare match Initial output value setting function Yes Yes Yes Yes Buffer function Yes Yes Compare 0 Yes Yes Yes Yes match output 1 Yes Yes Yes Yes Toggle Yes Yes Yes Yes Input capture function Yes Yes Yes Yes PWM mode Yes Yes Yes Interrupt sources Overflow Compare match in...

Page 209: ... interrupt enable register W 8 bits TSRW Timer status register W 8 bits TIOR Timer I O control register 8 bits TCNT Timer counter 16 bits GRA General register A input capture output compare register 16 bits GRB General register B input capture output compare register 16 bits GRC General register C input capture output compare register 16 bits GRD General register D input capture output compare reg...

Page 210: ... or input pin for GRA input capture Input capture output compare B FTIOB Input output Output pin for GRB output compare input pin for GRB input capture or PWM output pin in PWM mode Input capture output compare C FTIOC Input output Output pin for GRC output compare input pin for GRC input capture or PWM output pin in PWM mode Input capture output compare D FTIOD Input output Output pin for GRD out...

Page 211: ... FF82 Timer status register W TSRW R W 1 H 70 H FF83 Timer I O control register 0 TIOR0 R W H 88 H FF84 Timer I O control register 1 TIOR1 R W H 88 H FF85 Timer counter TCNT R W H 0000 H FF86 2 General register A GRA R W H FFFF H FF88 2 General register B GRB R W H FFFF H FF8A 2 General register C GRC R W H FFFF H FF8C 2 General register D GRD R W H FFFF H FF8E 2 Notes 1 Only 0 can be written to c...

Page 212: ...el at the pin is updated to the modified initial level Bit 6 Reserved This bit cannot be modified and is always read as 1 Bit 5 Buffer Operation B BUFEB Selects whether GRD operates as an input capture output compare register or the buffer register for GRB When GRD is used as the buffer register no input capture or compare match occurs for GRD Bit 5 BUFEB Description 0 GRD operates as an input cap...

Page 213: ...utput Initial value 1 FTIOC operates in PWM mode Note The period is specified in GRA Bit 0 PWM Mode B PWMB Selects whether the compare match output pin FTIOB operates normally or in PWM mode Bit 0 PWMB Description 0 FTIOB operates normally output compare output Initial value 1 FTIOB operates in PWM mode Note The period is specified in GRA 12 2 2 Timer Control Register W TCRW Bit 7 6 5 4 3 2 1 0 CC...

Page 214: ...ed the counter operates by the subclock in subactive or subsleep mode Bit 3 Timer Output Level Setting D TOD Sets the value output from the FTIOD pin after reset until the first compare match D TCNT and GRD matching signal is generated After a compare match is generated FTIOD outputs the value specified in timer I O control register 1 IOD2 to IOD0 Bit 3 TOD Description 0 FTIOD is 0 Initial value 1...

Page 215: ...cified in timer I O control register 0 IOA2 to IOA0 Bit 0 TOA Description 0 FTIOA is 0 Initial value 1 FTIOA is 1 12 2 3 Timer Interrupt Enable Register W TIERW Bit 7 6 5 4 3 2 1 0 OVIE IMIED IMIEC IMIEB IMIEA Initial value 0 1 1 1 0 0 0 0 Read Write R W R W R W R W R W TIERW is an 8 bit read write register that enables or disables the TCNT overflow interrupt request and general register GRA GRB G...

Page 216: ...Bit 2 IMIEC Description 0 IMIC interrupt requested by IMFC flag is disabled Initial value 1 IMIC interrupt requested by IMFC flag is enabled Bit 1 Input Capture Compare Match Interrupt Enable B IMIEB Enables or disables the IMIB interrupt requested by the IMFB flag of TSRW when IMFB is set to 1 Bit 1 IMIEB Description 0 IMIB interrupt requested by IMFB flag is disabled Initial value 1 IMIB interru...

Page 217: ...it cannot be set by software Bit 7 OVF Description 0 Clearing condition Initial value Read OVF when OVF 1 then write 0 in OVF 1 Setting condition TCNT overflowed from H FFFF to H 0000 Bits 6 to 4 Reserved These bits cannot be modified and are always read as 1 Bit 3 Input Capture Compare Match Flag D IMFD This status flag indicates a GRD compare match or input capture event has occurred This flag i...

Page 218: ...d by software and set by hardware it cannot be set by software Bit 1 IMFB Description 0 Clearing condition Initial value Read IMFB when IMFB 1 then write 0 in IMFB 1 Setting conditions TCNT GRB when GRB functions as an output compare register The TCNT value is transferred to GRB by an input capture signal when GRB functions as an input capture register Bit 0 Input Capture Compare Match Flag A IMFA...

Page 219: ...ed to H 88 by a reset Bit 7 Reserved This bit cannot be modified and is always read as 1 Bits 6 to 4 I O Control B2 to B0 IOB2 to IOB0 These bits select the GRB function Bit 6 IOB2 Bit 5 IOB1 Bit 4 IOB0 Function 0 0 0 GRB is an output No output at compare match Initial value 1 compare register 0 output at GRB compare match 1 1 0 1 output at GRB compare match 1 1 Output toggles at GRB compare match...

Page 220: ...tput conforms to the TOA setting in TCRW until the first compare match 2 Don t care 12 2 6 Timer I O Control Register 1 TIOR1 Bit 7 6 5 4 3 2 1 0 IOD2 IOD1 IOD0 IOC2 IOC1 IOC0 Initial value 1 0 0 0 1 0 0 0 Read Write R W R W R W R W R W R W TIOR1 is an 8 bit read write register that selects the output compare or input capture function for GRC and GRD and specifies the functions of the FTIOC and FT...

Page 221: ...to the TOD setting in TCRW until the first compare match 2 Don t care Bit 3 Reserved This bit cannot be modified and is always read as 1 Bits 2 to 0 I O Control C2 to C0 IOC2 to IOC0 These bits select the GRC function Bit 2 IOC2 Bit 1 IOC1 Bit 0 IOC0 Function 0 0 0 GRC is an output No output at compare match Initial value 1 compare register 0 output at GRC compare match 1 1 0 1 output at GRC compa...

Page 222: ... R W R W R W R W R W R W R W R W R W R W R W Each general register is a 16 bit read write register that can function as either an output compare register or an input capture register The function is selected by settings in TIOR0 and TIOR1 When a general register is used as an output compare register its value is constantly compared with the TCNT value When the two values match a compare match the ...

Page 223: ...ata bus These registers must be written or read in 16 bit units 8 bit access is not allowed Figure 12 2 shows the interface between the CPU and a 16 bit register Bus interface L H CPU On chip data bus TCNTH TCNTL Module data bus Figure 12 2 16 Bit Register Interface CPU and TCNT 16 bits 12 3 2 8 Bit Registers The registers other than TCNT GRA GRB GRC and GRD are 8 bit registers and are connected t...

Page 224: ...ed for input capture or output compare Buffer Operation If a compare match is generated when a GR is used as an output compare register the corresponding buffer register value is transferred to the GR If input capture is generated when a GR is used as an input capture register the GR value is transferred to the buffer register and the TCNT value is transferred to the GR PWM Mode PWM waveforms are ...

Page 225: ...o start the timer counter Yes No Figure 12 4 Counter Setup Procedure Example After a reset TCNT is initialized to H 0000 and set as a free running counter A free running counter starts incrementing the count when the CST bit in TMRW is set to 1 The input clock source can be selected from four internal clocks and an external clock by the CKS2 to CKS0 bits in TCRW When the count overflows from H FFF...

Page 226: ...RA set bit CCLR in TCRW to 1 and set the count period in GRA When the count matches GRA the IMFA flag in TSRW is set to 1 and TCNT is cleared to H 0000 If the IMIEA bit in TSRW is set to 1 at this time an interrupt request is sent to the CPU After the compare match TCNT continues counting from H 0000 Figure 12 6 illustrates periodic counting TCNT value GRA H 0000 CST bit IMFA Time Flag cleared by ...

Page 227: ...n outputs the selected initial value until the first compare match occurs 2 Set the compare match timing in GR 3 Set the CST bit in TMRW to 1 to start the timer counter Figure 12 7 Setup Procedure for Outputting Signals by Compare Match Example Figure 12 8 shows an example of 0 and 1 output TCNT operates as a free running counter 1 output is selected for compare match A and 0 output is selected fo...

Page 228: ... Toggle output Toggle output Figure 12 9 Toggle Output 1 TOA 0 TOB 1 Figure 12 10 shows another example of toggle output TCNT operates as a periodic counter cleared by compare match A Toggle output is selected for both compare match A and B TCNT value H FFFF H 0000 FTIOA FTIOB Time GRB GRA Toggle output Toggle output Counter cleared by compare match with GRA Figure 12 10 Toggle Output 2 TOA 0 TOB ...

Page 229: ...ows an example of the procedure for setting up input capture Select input capture signal source Input setup Start counter Input capture operation 1 2 1 Set TIOR to select the input capture function for a general register and select the input capture signal source and the capture edges rising edge falling edge or both edges of the input capture signal 2 Set the CST bit in TMRW to 1 to start the tim...

Page 230: ...oth edges of FTIOA and the falling edge of FTIOB are selected as capture edges TCNT operates as a free running counter TCNT value H FFFF H 1000 H 0000 FTIOA GRA Time H AA55 H 55AA H F000 H 1000 H F000 H 55AA GRB H AA55 FTIOB Figure 12 12 Input Capture Example ...

Page 231: ... When a compare match occurs the buffer register value is transferred to the corresponding general register Figure 12 13 shows the compare buffer operation Buffer register General register TCNT Comparator Compare match signal Figure 12 13 Compare Buffer Operation When GR Operates as an Input Capture Register When an input capture occurs the general register value is transferred to the correspondin...

Page 232: ...peration Start counter Buffer operation 1 2 3 1 Set TIOR to select the input capture or output compare function for a general register 2 Set the BUFEA or BUFEB bit in TMRW to select the buffer operation for a general register 3 Set the CST bit in TMRW to 1 to start the timer counter Figure 12 15 Setup Procedure for Buffer Operation Example ...

Page 233: ...re match B and 0 at compare match A Every time compare match B occurs the FTIOB output level changes and the value of buffer register GRD is transferred to GRB For details on PWM mode refer to the description of PWM Operation in this section TCNT value GRA H 0000 GRD Time GRB H 0200 H 0520 FTIOB H 0200 H 0450 H 0520 H 0450 GRB H 0450 H 0520 H 0200 Figure 12 16 Buffer Operation Example Output Compa...

Page 234: ...rates as a free running counter and FTIOA captures both rising and falling edges of the input signal Every time compare match A occurs the GRA value is transferred to GRC and the TCNT value is stored in GRA TCNT value H DA91 H 0245 H 0000 GRC Time H 0245 FTIOA GRA H 5480 H 0245 H FFFF H 5480 H 5480 H DA91 Figure 12 17 Buffer Operation Example Input Capture ...

Page 235: ...t pin set to PWM mode If the same value is set in the period register and the duty register the output does not change when a compare match occurs Up to three phase PWM waveforms can be output Figure 12 18 shows an example of a procedure for setting up PWM mode Select counter clock PWM mode Select counter clear source Select PWM mode PWM mode 1 2 3 Select output level 4 Set GRs 5 Start counter 6 1...

Page 236: ...H 0000 FTIOB FTIOC FTIOD Time GRD Counter cleared by compare match A Figure 12 19 PWM Mode Example 1 Figure 12 20 shows another example of operation in PWM mode The output signals go to 0 and TCNT is cleared at compare match A and the output signals go to 1 at compare match B C and D TOB TOC and TOD 0 initial output values are set to 1 TCNT value GRA GRB GRC H 0000 FTIOB FTIOC FTIOD Time GRD Count...

Page 237: ... FTIOB Time GRB Duty 100 Write to GRB Write to GRB When compare match for the period register occurs at the same time as that for the duty register the output signal will not change TCNT value GRA H 0000 FTIOB Time GRB Duty 100 Write to GRB Write to GRB Write to GRB When compare match for the period register occurs at the same time as that for the duty register the output signal will not change Du...

Page 238: ... match for the period register occurs at the same time as that for the duty register the output signal will not change TCNT value GRA H 0000 FTIOB Time GRB Duty 0 Write to GRB Write to GRB When compare match for the period register occurs at the same time as that for the duty register the output signal will not change Duty 100 Write to GRB Write to GRB Write to GRB Figure 12 22 PWM Mode Example 4 ...

Page 239: ...unt Timing for Internal Clock Source TCNT TCNT input clock External clock φ N N 1 N 2 Rising edge Rising edge Figure 12 24 Count Timing for External Clock Source Output Compare Timing The compare match signal is generated in the last state in which TCNT and the general register match when TCNT changes from the matching value to the next value When the compare match signal is generated the output v...

Page 240: ... the rising edge falling edge or both edges can be selected through settings in TIOR0 and TIOR1 Figure 12 26 shows the timing when the falling edge is selected The pulse width of the input capture signal must be at least two system clock φ cycles shorter pulses will not be detected correctly TCNT Input capture input ø N 1 N N 1 N 2 N GRA to GRD Input capture signal Figure 12 26 Input Capture Timin...

Page 241: ...d by compare match A TCNT Compare match signal φ GRA N N H 0000 Figure 12 27 Timing of Counter Clearing by Compare Match Buffer Operation Timing Figures 12 28 and 12 29 show the buffer operation timing GRC GRD Compare match signal TCNT φ GRA GRB N N 1 M M Figure 12 28 Buffer Operation Timing Compare Match ...

Page 242: ... the general register The compare match signal is generated in the last state in which the values match when TCNT is updated from the matching count to the next count Therefore when TCNT matches a general register the compare match signal is generated only after the next TCNT clock pulse is input Figure 12 30 shows the timing of the IMFA to IMFD flag setting at compare match GRA to GRD TCNT TCNT i...

Page 243: ...g setting at input capture GRA to GRD TCNT Input capture signal φ N N IMFA to IMFD IRRTW Figure 12 31 Timing of IMFA to IMFD Flag Setting at Input Capture Timing of Status Flag Clearing When the CPU reads a status flag while it is set to 1 then writes 0 in the status flag the status flag is cleared Figure 12 32 shows the status flag clearing timing IMFA to IMFD Write signal Address φ TSRW address ...

Page 244: ...en TCNT is updated from the matching count to the next count The actual counter frequency is therefore given by the following formula f φ N 1 f counter frequency φ system clock frequency N value set in GRA Contention between TCNT Write and Clear If a counter clear signal occurs in the T2 state of a TCNT write cycle clearing of the counter takes priority and the write is not performed Figure 12 33 ...

Page 245: ... in the T2 state of a TCNT write cycle writing takes priority and TCNT is not incremented Figure 12 34 shows this timing TCNT input clock Write signal Address φ TCNT address TCNT TCNT write cycle T1 T2 N M TCNT write data Figure 12 34 Contention between TCNT Write and Increment ...

Page 246: ...iting takes priority and the buffer operation data transfer from the buffer register to the general register is not performed Figure 12 35 shows this timing Compare match signal Write signal Address φ GR address Buffer register GR write cycle T1 T2 X GR N M GR write data Figure 12 35 Contention between General Register Write and Compare Match in Buffer Operation ...

Page 247: ...d data before being updated in the buffer register is transferred to the general data in a buffer operation Figure 12 36 shows this timing Compare match signal Write signal Address φ Buffer register address Buffer register Buffer register write cycle T1 T2 X GR N N M Buffer register write data Figure 12 36 Contention between Buffer Register Write and Compare Match ...

Page 248: ...ng occurs in the T2 state of a general register write cycle the compare match signal is generated Figure 12 37 shows this timing Compare match signal Write signal Address φ GR address GR GR write cycle T1 T2 N TCNT N N 1 M GR write data Figure 12 37 Contention between General Register Write and Compare Match ...

Page 249: ...l register write cycle writing to GR takes priority and input capture data transfer from TCNT to GR is not performed Figure 12 38 shows this timing Input capture signal Write signal Address φ GR address GR GR write cycle T1 T2 X TCNT N X 1 M GR write data Figure 12 38 Contention between General Register Write and Input Capture ...

Page 250: ...the buffer register takes priority and input capture data transfer from GR to the buffer register is not performed Figure 12 39 shows this timing Input capture signal Write signal Buffer register Address φ Buffer register address TCNT Buffer register write cycle T1 T2 N X GR M M Y Buffer register write data Figure 12 39 Contention between Buffer Register Write and Input Capture ...

Page 251: ...ws this timing Input capture signal Read signal Address φ GR address GR GR read cycle T1 T2 N Internal data bus N M TCNT M Figure 12 40 Contention between General Register Read and Input Capture TCNT Read Timing Error This LSI takes two states two system clock φ cycles to access timer W Therefore when φ is selected as the TCNT input clock and TCNT is read the read timing will include 1 φ second er...

Page 252: ...n clock signal level low to high is assumed to be a clock rising edge a count clock pulse is generated and TCNT erroneously increments the count Figure 12 41 shows this timing TCNT Previous clock N N 1 N 2 N 3 New clock Count clock The change in signal level at clock switching is assumed to be a rising edge and TCNT increments the count Figure 12 41 Internal Clock Switching and TCNT Operation Inte...

Page 253: ...able Choice of eight internal clock sources ø 64 ø 128 ø 256 ø 512 ø 1024 ø 2048 ø 4096 ø 8192 and the internal oscillator Reset signal generated on counter overflow An overflow period of 1 to 256 times the selected clock can be set 13 1 2 Block Diagram Figure 13 1 shows a block diagram of the watchdog timer ø Internal reset signal PSS TCWD TMWD TCSRWD Internal data bus Notation TCSRWD Timer contr...

Page 254: ...en to only when the write condition is satisfied For the write conditions see the individual bit descriptions TCSRWD is an 8 bit read write register that performs TCSRWD and TCWD write control and watchdog timer operation control and indicates the operation status Bit 7 Bit 6 Write Inhibit B6WI Bit 7 controls writing of data to bit 6 of TCSRWD Bit 7 B6WI Description 0 Writing to bit 6 is enabled 1...

Page 255: ... 3 Bit 2 Write Inhibit B2WI Bit 3 controls writing of data to bit 2 of TCSRWD Bit 3 B2WI Description 0 Writing to bit 2 is enabled 1 Writing to bit 2 is disabled Initial value This bit is always read as 1 Data is not stored if written to this bit Bit 2 Watchdog Timer On WDON Bit 2 controls watchdog timer operation Bit 2 WDON Description 0 Watchdog timer operation is disabled Initial value Clearing...

Page 256: ...pin or by a 0 write by software Bit 0 WRST Description 0 Clearing conditions Initial value Reset by RES pin When 0 is written to WRST while writing 0 to B0WI when TCSRWE 1 1 Setting condition When TCW overflows and an internal reset signal is generated 13 2 2 Timer Counter WD TCWD Bit 7 6 5 4 3 2 1 0 TCWD7 TCWD6 TCWD5 TCWD4 TCWD3 TCWD2 TCWD1 TCWD0 Initial value 0 0 0 0 0 0 0 0 Read Write R W R W R...

Page 257: ... 7 to 4 are reserved they are always read as 1 and cannot be modified Bits 3 to 0 Clock Select 3 to 0 CKS3 to CKS0 Bits 3 to 0 select the clock to be input to TCWD Bit 3 CKS3 Bit 2 CKS2 Bit 1 CKS1 Bit 0 CKS0 Description 1 0 0 0 Internal clock ø 64 1 Internal clock ø 128 1 0 Internal clock ø 256 1 Internal clock ø 512 1 0 0 Internal clock ø 1024 1 Internal clock ø 2048 1 0 Internal clock ø 4096 1 I...

Page 258: ...internal reset signal is output for a period of 512 øosc clock cycles TCWD is a writable counter and when a value is set in TCWD the count up starts from that value An overflow period in the range of 1 to 256 input clock cycles can therefore be set according to the TCWD value Figure 13 2 shows an example of watchdog timer operation Example With 30 ms overflow period when ø 4 MHz ø 8192 selected 4 ...

Page 259: ...g Modes Operating mode Reset Active Sleep Subactive Subsleep Standby TCWD Reset Functions Functions Halted Halted Halted TCSRWD Reset Functions Functions Functions Retained Retained TMWD Reset Functions Retained Functions Retained Retained Note The watchdog timer functions if the internal oscillator is selected as the clock source ...

Page 260: ...244 ...

Page 261: ...th standard asynchronous communication LSIs such as a Universal Asynchronous Receiver Transmitter UART or Asynchronous Communication Interface Adapter ACIA A multiprocessor communication function is also provided enabling serial data communication among processors There is a choice of 12 data transfer formats Data length 7 or 8 bits Stop bit length 1 or 2 bits Parity Even odd or none Multiprocesso...

Page 262: ...ission and reception units are both double buffered allowing continuous transmission and reception On chip baud rate generator allowing any desired bit rate to be selected Choice of an internal or external clock as the transmit receive clock source Six interrupt sources transmit end transmit data empty receive data full overrun error framing error and parity error ...

Page 263: ...ation RSR RDR TSR TDR SMR SCR3 SSR BRR BRC Receive shift register Receive data register Transmit shift register Transmit data register Serial mode register Serial control register 3 Serial status register Bit rate register Bit rate counter Interrupt request TEI TXI RXI ERI Internal clock ø 64 ø 16 ø 4 ø External clock BRC Baud rate generator Figure 14 1 SCI3 Block Diagram ...

Page 264: ...4 1 4 Register Configuration Table 14 2 shows the SCI3 register configuration Table 14 2 Registers Name Abbrev R W Initial Value Address Serial mode register SMR R W H 00 H FFA8 Bit rate register BRR R W H FF H FFA9 Serial control register 3 SCR3 R W H 00 H FFAA Transmit data register TDR R W H FF H FFAB Serial status register SSR R W H 84 H FFAC Receive data register RDR R H 00 H FFAD Transmit sh...

Page 265: ...by the CPU 14 2 2 Receive Data Register RDR Bit 7 6 5 4 3 2 1 0 RDR7 RDR6 RDR5 RDR4 RDR3 RDR2 RDR1 RDR0 Initial value 0 0 0 0 0 0 0 0 Read Write R R R R R R R R RDR is an 8 bit register that stores received serial data When reception of one byte of data is finished the received data is transferred from RSR to RDR and the receive operation is completed RSR is then enabled for reception RSR and RDR ...

Page 266: ...as been written to TDR if bit TDRE is set to 1 TSR cannot be read or written directly by the CPU 14 2 4 Transmit Data Register TDR Bit 7 6 5 4 3 2 1 0 TDR7 TDR6 TDR5 TDR4 TDR3 TDR2 TDR1 TDR0 Initial value 1 1 1 1 1 1 1 1 Read Write R W R W R W R W R W R W R W R W TDR is an 8 bit register that stores transmit data When TSR is found to be empty the transmit data written in TDR is transferred to TSR ...

Page 267: ...er 7 or 8 bits as the data length to be used in asynchronous mode In synchronous mode the data length is always 8 bits irrespective of the bit 6 setting Bit 6 CHR Description 0 8 bit data Initial value 1 7 bit data Note When 7 bit data is selected the MSB bit 7 of TDR is not transmitted Bit 5 Parity Enable PE Bit 5 selects whether a parity bit is to be added during transmission and checked during ...

Page 268: ... Bit 3 selects 1 bit or 2 bits as the stop bit length in asynchronous mode The STOP bit setting is only valid in asynchronous mode When synchronous mode is selected the STOP bit setting is invalid since stop bits are not added Bit 3 STOP Description 0 1 stop bit 1 Initial value 1 2 stop bits 2 Notes 1 In transmission a single 1 bit stop bit is added at the end of a transmit character 2 In transmis...

Page 269: ... R W R W R W R W R W R W SCR3 is an 8 bit register for selecting transmit or receive operation the asynchronous mode clock output interrupt request enabling or disabling and the transmit receive clock source SCR3 can be read or written by the CPU at any time SCR3 is initialized to H 00 upon reset and in standby subactive or subsleep mode Bit 7 Transmit interrupt Enable TIE Bit 7 selects enabling o...

Page 270: ...alue 1 Transmit operation enabled 2 TXD pin is transmit data pin 3 Notes 1 Bit TDRE in SSR is fixed at 1 2 When transmit data is written to TDR in this state bit TDR in SSR is cleared to 0 and serial data transmission is started Be sure to carry out serial mode register SMR settings to decide the transmission format before setting bit TE to 1 3 When bit TXD in PMR7 is set to 1 When bit TXD is clea...

Page 271: ...d RXI and ERI requests when bits TIE and RIE in serial control register SCR are set to 1 and setting of the RDRF FER and OER flags are enabled Bit 2 Transmit End Interrupt Enable TEIE Bit 2 selects enabling or disabling of the transmit end interrupt request TEI if there is no valid transmit data in TDR when MSB data is to be sent Bit 2 TEIE Description 0 Transmit end interrupt request TEI disabled...

Page 272: ... a frequency 16 times the bit rate 14 2 7 Serial Status Register SSR Bit 7 6 5 4 3 2 1 0 TDRE RDRF OER FER PER TEND MPBR MPBT Initial value 1 0 0 0 0 1 0 0 Read Write R W R W R W R W R W R R R W Note Only a write of 0 for flag clearing is possible SSR is an 8 bit register containing status flags that indicate the operational status of SCI3 and multiprocessor bits SSR can be read or written by the ...

Page 273: ...SR Initial value Bit 6 Receive Data Register Full RDRF Bit 6 indicates that received data is stored in RDR Bit 6 RDRF Description 0 There is no receive data in RDR Initial value Clearing conditions After reading RDRF 1 cleared by writing 0 to RDRF When RDR data is read by an instruction 1 There is receive data in RDR Setting condition When reception ends normally and receive data is transferred fr...

Page 274: ...aming Error FER Bit 4 indicates that a framing error has occurred during reception in asynchronous mode Bit 4 FER Description 0 Reception in progress or completed 1 Initial value Clearing condition After reading FER 1 cleared by writing 0 to FER 1 A framing error has occurred during reception 2 Setting condition When the stop bit at the end of the receive data is checked for a value of 1 at the en...

Page 275: ...ts previous state 2 Receive data in which it a parity error has occurred is still transferred to RDR but bit RDRF is not set Reception cannot be continued with bit PER set to 1 In synchronous mode neither transmission nor reception is possible when bit PER is set to 1 Bit 2 Transmit End TEND Bit 2 indicates that bit TDRE is set to 1 when the last bit of a transmit character is sent Bit 2 is a read...

Page 276: ...s invalid when synchronous mode is selected when the multiprocessor communication function is disabled and when not transmitting Bit 0 MPBT Description 0 Multiprocessor bit value in transmit data is 0 Initial value 1 Multiprocessor bit value in transmit data is 1 14 2 8 Bit Rate Register BRR Bit 7 6 5 4 3 2 1 0 BRR7 BRR6 BRR5 BRR4 BRR3 BRR2 BRR1 BRR0 Initial value 1 1 1 1 1 1 1 1 Read Write R W R ...

Page 277: ...2 48 0 7 0 00 0 9 2 34 19200 0 2 8 51 0 2 13 78 0 3 0 00 0 4 2 34 31250 0 1 0 00 0 1 4 86 0 1 22 88 0 2 0 00 38400 0 1 18 62 0 1 14 67 0 1 0 00 ø MHz 3 6864 4 4 9152 5 Bit Rate bits s n N Error n N Error n N Error n N Error 110 2 64 0 70 2 70 0 03 2 86 0 31 2 88 0 25 150 1 191 0 00 1 207 0 16 1 255 0 00 2 64 0 16 300 1 95 0 00 1 103 0 16 1 127 0 00 1 129 0 16 600 0 191 0 00 0 207 0 16 0 255 0 00 1...

Page 278: ... 00 0 12 0 16 31250 0 5 0 00 0 5 2 40 0 6 5 33 0 7 0 00 38400 0 4 2 34 0 4 0 00 0 5 0 00 0 6 6 99 ø MHz 9 8304 10 12 12 888 Bit Rate bits s n N Error n N Error n N Error n N Error 110 2 174 0 26 2 177 0 25 2 212 0 03 2 217 0 08 150 2 127 0 00 2 129 0 16 2 155 0 16 2 159 0 00 300 1 255 0 00 2 64 0 16 2 77 0 16 2 79 0 00 600 1 127 0 00 1 129 0 16 1 155 0 16 1 159 0 00 1200 0 255 0 00 1 64 0 16 1 77 ...

Page 279: ...0 00 0 51 0 16 19200 0 22 0 93 0 23 0 00 0 25 0 16 31250 0 13 0 00 0 14 1 70 0 15 0 00 38400 0 11 0 00 0 12 0 16 A setting can be made but an error will result Notes 1 The value set in BRR is given by the following equation N 106 1 ø 64 22n 1 B where B Bit rate bit s N Baud rate generator BRR setting 0 N 255 ø Operating frequency MHz n Value set in bits CKS1 and CKS0 in SMR The relation between n ...

Page 280: ...peed mode Table 14 5 Maximum Bit Rate for Each Frequency Asynchronous Mode Setting ø MHz Maximum Bit Rate bits s n N 2 62500 0 0 2 097152 65536 0 0 2 4576 76800 0 0 3 93750 0 0 3 6864 115200 0 0 4 125000 0 0 4 9152 153600 0 0 5 156250 0 0 6 187500 0 0 6 144 192000 0 0 7 3728 230400 0 0 8 250000 0 0 9 8304 307200 0 0 10 312500 0 0 12 375000 0 0 12 288 384000 0 0 14 437500 0 0 14 7456 460800 0 0 16 ...

Page 281: ...50 2 124 2 249 3 124 3 124 500 1 249 2 124 2 249 2 249 1k 1 124 1 249 2 124 2 99 2 5k 0 199 1 99 1 199 1 249 1 199 5k 0 99 0 199 1 99 1 124 1 99 10k 0 49 0 99 0 199 0 249 0 159 25k 0 19 0 39 0 79 0 99 0 79 50k 0 9 0 19 0 39 0 49 0 39 100k 0 4 0 9 0 19 0 24 0 15 250k 0 1 0 3 0 7 0 9 0 7 500k 0 0 0 1 0 3 0 4 0 3 1M 0 0 0 1 0 1 2M 0 0 2 5M 0 0 0 0 Blank Cannot be set A setting can be made but an erro...

Page 282: ...ate bit s N Baud rate generator BRR setting 0 N 255 ø Operating frequency MHz n Baud rate generator input clock number n 0 1 2 or 3 The relation between n and the clock is shown in table 14 7 Table 14 7 Relation between n and Clock SMR Setting n Clock CKS1 CKS0 0 ø 0 0 1 ø 4 0 1 2 ø16 1 0 3 ø 64 1 1 ...

Page 283: ...tect framing errors parity errors overrun errors and the break state An internal or external clock can be selected as the SCI clock source When an internal clock is selected the SCI operates using the on chip baud rate generator and can output a serial clock signal with a frequency matching the bit rate When an external clock is selected the external clock input must have a frequency 16 times the ...

Page 284: ... 1 mode 2 bits 1 0 multiprocessor 7 bit data 1 bit 1 format 2 bits 1 0 Synchronous mode 8 bit data No No No Note Don t care Table 14 9 SMR and SCR3 Settings and Clock Source Selection SMR SCR3 Transmit Receive Clock Bit 7 COM Bit 1 CKE1 Bit 0 CKE0 Mode Clock Source SCK3 Pin Function 0 0 0 Asynchronous Internal I O port SCK3 pin not used 1 mode Outputs clock with same frequency as bit rate 1 0 Exte...

Page 285: ...until reception of the next RSR data is completed TXI TDRE TIE When TSR is found to be empty on completion of the previous transmission and the transmit data placed in TDR is transferred to TSR bit TDRE is set to 1 If bit TIE is set to 1 at this time TXI is enabled and an interrupt is requested See figure 14 2 b The TXI interrupt routine writes the next transmit data to TDR and clears bit TDRE to ...

Page 286: ... Interrupt TDR next transmit data TSR transmission in progress TDRE 0 TXD pin TDR TSR transmission completed transfer TDRE 1 TXI request when TIE 1 TXD pin Figure 14 2 b TDRE Setting and TXI Interrupt TDR TSR transmission in progress TEND 0 TXD pin TDR TSR reception completed TEND 1 TEI request when TEIE 1 TXD pin Figure 14 2 c TEND Setting and TEI Interrupt ...

Page 287: ... Transmit receive data Parity bit Stop bit s 7 or 8 bits One transfer data unit character or frame 1 bit or none 1 or 2 bits Mark state 1 MSB LSB Figure 14 3 Data Format in Asynchronous Communication In asynchronous communication the communication line is normally in the mark state high level SCI3 monitors the communication line and when it detects a space low level identifies this as a start bit ...

Page 288: ...P STOP 1 2 3 4 5 6 7 8 9 10 11 12 0 0 0 0 S 8 bit data STOP 0 0 0 1 S 8 bit data STOP STOP 0 1 0 0 S 8 bit data P STOP 0 1 0 1 S 8 bit data P STOP STOP 1 0 0 0 S 7 bit data STOP 1 0 0 1 S 7 bit data STOP STOP 1 1 0 0 S 7 bit data P STOP 1 1 0 1 S 7 bit data P STOP STOP 0 1 0 S 8 bit data MPB STOP 0 1 1 S 8 bit data MPB STOP STOP 1 1 0 S 7 bit data MPB STOP 1 1 1 S 7 bit data MPB STOP STOP Note Don...

Page 289: ...igure 14 4 1 character 1 frame 0 D0 D1 D2 D3 D4 D5 D6 D7 0 1 1 1 Clock Serial data Figure 14 4 Phase Relationship between Output Clock and Transfer Data Asynchronous Mode 8 Bit Data Parity 2 Stop Bits 14 4 3 Data Transfer Operations SCI3 Initialization Before data is transferred on SCI3 bits TE and RE in SCR3 must first be cleared to 0 and then SCI3 must be initialized as follows Note If the opera...

Page 290: ...rmat in the serial mode register SMR Write the value corresponding to the transfer rate in BRR This operation is not necessary when an external clock is selected 1 2 3 4 Wait for at least the interval required to transmit or receive one bit then set TE or RE in the serial control register SCR3 Setting RE enables the RxD pin to be used and when transmitting setting bit TXD in PMR7 enables the TXD o...

Page 291: ...register SSR and check that bit TDRE is set to 1 then write transmit data to the transmit data register TDR When data is written to TDR bit TDRE is cleared to 0 automatically When continuing data transmission be sure to read TDRE 1 to confirm that a write can be performed before writing data to TDR When data is written to TDR bit TDRE is cleared to 0 automatically If a break is to be output when d...

Page 292: ... bit has been sent starts transmission of the next frame If bit TDRE is set to 1 bit TEND in SSR is set to 1 and the mark state in which 1s are transmitted is established after the stop bit has been sent If bit TEIE in SCR3 is set to 1 at this time a TEI request is made Figure 14 7 shows an example of the operation when transmitting in asynchronous mode 1 frame Start bit Start bit Transmit data Tr...

Page 293: ...g A Read bits OER PER and FER in the serial status register SSR to determine if there is an error If a receive error has occurred execute receive error processing Read SSR and check that bit RDRF is set to 1 If it is read the receive data in RDR When the RDR data is read bit RDRF is cleared to 0 automatically When continuing data reception finish reading of bit RDRF and RDR before receiving the st...

Page 294: ...essing If a receive error has occurred read bits OER PER and FER in SSR to identify the error and after carrying out the necessary error processing ensure that bits OER PER and FER are all cleared to 0 Reception cannot be resumed if any of these bits is set to 1 In the case of a framing error a break can be detected by reading the value of the RXD pin 4 Figure 14 8 Example of Data Reception Flowch...

Page 295: ...is stored in RDR If bit RIE is set to 1 in SCR3 an RXI interrupt is requested If the error checks identify a receive error bit OER PER or FER is set to 1 depending on the kind of error Bit RDRF retains its state prior to receiving the data If bit RIE is set to 1 in SCR3 an ERI interrupt is requested Table 14 12 shows the conditions for detecting a receive error and receive data processing Note No ...

Page 296: ... in response to framing error Figure 14 9 Example of Operation when Receiving in Asynchronous Mode 8 Bit Data Parity 1 Stop Bit 14 5 Operation in Synchronous Mode In synchronous mode SCI3 transmits and receives data in synchronization with clock pulses This mode is suitable for high speed serial communication SCI3 has separate transmission and reception units allowing full duplex communication wit...

Page 297: ... and ends with the MSB After output of the MSB the communication line retains the MSB state When receiving in synchronous mode SCI3 latches receive data at the rising edge of the serial clock The data transfer format uses a fixed 8 bit data length Parity and multiprocessor bits cannot be added 14 5 2 Clock Either an internal clock generated by the baud rate generator or an external clock input at ...

Page 298: ... bit TEND in SSR Clear bit TE to 0 in SCR3 No TDRE 1 Yes Continue data transmission No TEND 1 Yes Yes No Read the serial status register SSR and check that bit TDRE is set to 1 then write transmit data to the transmit data register TDR When data is written to TDR bit TDRE is cleared to 0 automatically the clock is output and data transmission is started When continuing data transmission be sure to...

Page 299: ... to TSR and starts transmission of the next frame If bit TDRE is set to 1 SCI3 sets bit TEND to 1 in SSR and after sending the MSB bit 7 retains the MSB state If bit TEIE in SCR3 is set to 1 at this time a TEI request is made After transmission ends the SCK3 pin is fixed at the high level Note Transmission is not possible if an error flag OER FER or PER that indicates the data reception status is ...

Page 300: ... register SSR to determine if there is an error If an overrun error has occurred execute overrun error processing Read SSR and check that bit RDRF is set to 1 If it is read the receive data in RDR When the RDR data is read bit RDRF is cleared to 0 automatically When continuing data reception finish reading of bit RDRF and RDR before receiving the MSB bit 7 of the current frame When the data in RDR...

Page 301: ... set to 1 Bit RDRF remains set to 1 If bit RIE is set to 1 in SCR3 an ERI interrupt is requested See table 14 12 for the conditions for detecting an overrun error and receive data processing Note No further receive operations are possible while a receive error flag is set Bits OER FER PER and RDRF must therefore be cleared to 0 before resuming reception Figure 14 14 shows an example of the operati...

Page 302: ...d SSR and check that bit RDRF is set to 1 If it is read the receive data in RDR When the RDR data is read bit RDRF is cleared to 0 automatically When continuing data transmission reception finish reading of bit RDRF and RDR before receiving the MSB bit 7 of the current frame Before transmitting the MSB bit 7 of the current frame also read TDRE 1 to confirm that a write can be performed then write ...

Page 303: ... communication each receiver is assigned its own ID code The serial communication cycle consists of two cycles an ID transmission cycle in which the receiver is specified and a data transmission cycle in which the transfer data is sent to the specified receiver These two cycles are differentiated by means of the multiprocessor bit 1 indicating an ID transmission cycle and 0 a data transmission cyc...

Page 304: ...Using Multiprocessor Format Sending Data H AA to Receiver A There is a choice of four data transfer formats If a multiprocessor format is specified the parity bit specification is invalid See table 14 11 for details For details on the clock used in multiprocessor communication see section 14 4 Operation in Asynchronous Mode Multiprocessor Transmitting Figure 14 17 shows an example of a flowchart f...

Page 305: ... 0 or 1 and write transmit data to the transmit data register TDR When data is written to TDR bit TDRE is cleared to 0 automatically When continuing data transmission be sure to read TDRE 1 to confirm that a write can be performed before writing data to TDR When data is written to TDR bit TDRE is cleared to 0 automatically If a break is to be output when data transmission ends set the port PCR to ...

Page 306: ...1 and the mark state in which 1s are transmitted is established after the stop bit has been sent If bit TEIE in SCR3 is set to 1 at this time a TEI request is made Figure 14 18 shows an example of the operation when transmitting using the multiprocessor format 1 frame Start bit Start bit Transmit data Transmit data MPB MPB Stop bit Stop bit Mark state 1 frame 0 1 D0 D1 D7 0 1 1 1 1 0 D0 D1 D7 0 1 ...

Page 307: ...sing Read SSR and check that bit RDRF is set to 1 If it is read the receive data in RDR and compare it with this receiver s own ID If the ID is not this receiver s set bit MPIE to 1 again When the RDR data is read bit RDRF is cleared to 0 automatically Read SSR and check that bit RDRF is set to 1 then read the data in RDR If a receive error has occurred read bits OER and FER in SSR to identify the...

Page 308: ... OER and FER to 0 in SSR Yes OER 1 Yes Yes FER 1 Break No No No Overrun error processing Framing error processing A Figure 14 19 Example of Multiprocessor Data Reception Flowchart cont Figure 14 20 shows an example of the operation when receiving using the multiprocessor format ...

Page 309: ...frame Start bit Start bit Receive data ID2 Receive data Data2 MPB MPB Stop bit Stop bit Mark state idle state 1 frame 0 1 D0 D1 D7 1 1 1 1 0 a When data does not match this receiver s ID b When data matches this receiver s ID D0 D1 D7 ID2 Data2 ID1 0 Serial data MPIE RDRF LSI operation RXI request MPIE cleared to 0 User processing RDRF cleared to 0 RXI request RDRF cleared to 0 RDR data read When ...

Page 310: ...alue of bit TDRE in SSR is 1 Therefore if the transmit data empty interrupt request TXI is enabled by setting bit TIE to 1 in SCR3 before transmit data is transferred to TDR a TXI interrupt will be requested even if the transmit data is not ready Also the initial value of bit TEND in SSR is 1 Therefore if the transmit end interrupt request TEI is enabled by setting bit TEIE to 1 in SCR3 before tra...

Page 311: ... is set to 1 then write the transmit data to TDR once only not two or more times 14 8 2 Operation when a Number of Receive Errors Occur Simultaneously If a number of receive errors are detected simultaneously the status flags in SSR will be set to the states shown in table 14 14 If an overrun error is detected data transfer from RSR to RDR will not be performed and the receive data will be lost Ta...

Page 312: ...an I O port and 1 is output To detect a break during transmission clear bit TE to 0 after setting PCR 1 and PDR 0 When bit TE is cleared to 0 the transmission unit is initialized regardless of the current transmission state the TXD pin functions as an I O port and 0 is output from the TXD pin 14 8 5 Receive Error Flags and Transmit Operation Synchronous Mode Only When a receive error flag OER PER ...

Page 313: ...ation 1 M 0 5 L 0 5 F 100 1 2N D 0 5 N Equation 1 where N Ratio of bit rate to clock N 16 D Clock duty D 0 5 to 1 0 L Frame length L 9 to 12 F Absolute value of clock frequency deviation Substituting 0 for F absolute value of clock frequency deviation and 0 5 for D clock duty in equation 1 a receive margin of 46 875 is given by equation 2 When D 0 5 and F 0 M 0 5 1 2 16 100 46 875 Equation 2 Howev...

Page 314: ...me the next frame of data may be read This is illustrated in figure 14 22 Communication line RDRF RDR Frame 1 Frame 2 Frame 3 Data 1 Data 1 RDR read RDR read Data 1 is read at point A Data 2 Data 3 Data 3 A Data 2 is read at point B B Figure 14 22 Relation between RDR Read Timing and Data In this case only a single RDR read operation not two or more should be performed after first checking that bi...

Page 315: ...hen receiving I2 C bus format Automatic loading of acknowledge bit when transmitting I2 C bus format Wait function in master mode I2 C bus format A wait can be inserted by driving the SCL pin low after data transfer excluding acknowledgement The wait can be cleared by clearing the interrupt flag Wait function in slave mode I2 C bus format A wait request can be generated by driving the SCL pin low ...

Page 316: ...ise canceler Noise canceler Clock control Bus state decision circuit Arbitration decision circuit Output data control circuit Address comparator SAR SARX Interrupt generator ICDRS ICDRR ICDRT ICSR ICMR ICCR Internal data bus Interrupt request SCL SDA Notation ICCR ICMR ICSR ICDR SAR SARX PS I2 C bus control register I2 C bus mode register I2C bus status register I2 C bus data register Slave addres...

Page 317: ...VDD VCC SCL SDA Figure 15 2 I2 C Bus Interface Connections Example H8 3664 Series Chip as Master 15 1 3 Pin Configuration Table 15 1 summarizes the input output pins used by the I2 C bus interface Table 15 1 I2 C Bus Interface Pins Name Abbreviation I O Function Serial clock SCL I O IIC serial clock input output Serial data SDA I O IIC serial data input output ...

Page 318: ...0 H FFC5 I2 C bus data register ICDR R W Undefined H FFC6 I2 C bus mode register ICMR R W H 00 H FFC7 Slave address register SAR R W H 00 H FFC7 Second slave address register SARX R W H 01 H FFC6 Timer serial control register TSCR R W H 00 H FFFC Note The register that can be written or read depends on the ICE bit in the I2 C bus control register The slave address register can be accessed when ICE...

Page 319: ...ial value Read Write 7 ICDRR7 R 6 ICDRR6 R 5 ICDRR5 R 4 ICDRR4 R 3 ICDRR3 R 0 ICDRR0 R 2 ICDRR2 R 1 ICDRR1 R ICDRS Bit Initial value Read Write 7 ICDRS7 6 ICDRS6 5 ICDRR5 4 ICDRS4 3 ICDRS3 0 ICDRS0 2 ICDRS2 1 ICDRS1 ICDRT Bit Initial value Read Write 7 ICDRT7 W 6 ICDRT6 W 5 ICDRT5 W 4 ICDRT4 W 3 ICDRT3 W 0 ICDRT0 W 2 ICDRT2 W 1 ICDRT1 W TDRE RDRF internal flags Bit Initial value Read Write RDRF 0 ...

Page 320: ... 0 following transmission reception of one frame of data using ICDRS data is transferred automatically from ICDRS to ICDRR If the number of bits in a frame excluding the acknowledge bit is less than 8 transmit data and receive data are stored differently Transmit data should be written justified toward the MSB side when MLS 0 and toward the LSB side when MLS 1 Receive data bits read from the LSB s...

Page 321: ...itions In transmit mode TRS 1 when a start condition is detected in the bus line state after a start condition is issued in master mode with the I2 C bus format or serial format selected When data is transferred from ICDRT to ICDRS Data transfer from ICDRT to ICDRS when TRS 1 and TDRE 0 and ICDRS is empty When a switch is made from receive mode TRS 0 to transmit mode TRS 1 after detection of a sta...

Page 322: ...is cleared to 0 in ICCR SAR is initialized to H 00 by a reset Bits 7 to 1 Slave Address SVA6 to SVA0 Set a unique address in bits SVA6 to SVA0 differing from the addresses of other slave devices connected to the I2 C bus Bit 0 Format Select FS Used together with the FSX bit in SARX to select the communication format The FS bit also specifies whether or not SAR slave address recognition is performe...

Page 323: ...Address SVAX6 to SVAX0 Set a unique address in bits SVAX6 to SVAX0 differing from the addresses of other slave devices connected to the I2 C bus Bit 0 Format Select X FSX Used together with the FS bit in SAR to select the communication format The FSX bit also specifies whether or not SARX slave address recognition is performed in slave mode For details see the description of the FS bit in SAR 15 2...

Page 324: ...rtion Bit WAIT Selects whether to insert a wait between the transfer of data and the acknowledge bit in master mode with the I2 C bus format When WAIT is set to 1 after the fall of the clock for the final data bit the IRIC flag is set to 1 in ICCR and a wait state begins with SCL at the low level When the IRIC flag is cleared to 0 in ICCR the wait ends and the acknowledge bit is transferred If WAI...

Page 325: ...1 0 ø 48 104 kHz 167 kHz 208 kHz 333 kHz 1 ø 64 78 1 kHz 125 kHz 156 kHz 250 kHz 1 0 0 ø 80 62 5 kHz 100 kHz 125 kHz 200 kHz 1 ø 100 50 0 kHz 80 0 kHz 100 kHz 160 kHz 1 0 ø 112 44 6 kHz 71 4 kHz 89 3 kHz 143 kHz 1 ø 128 39 1 kHz 62 5 kHz 78 1 kHz 125 kHz 1 0 0 0 ø 56 89 3 kHz 143 kHz 179 kHz 286 kHz 1 ø 80 62 5 kHz 100 kHz 125 kHz 200 kHz 1 0 ø 96 52 1 kHz 83 3 kHz 104 kHz 167 kHz 1 ø 128 39 1 kHz...

Page 326: ...er including the acknowledge bit Bit 2 Bit 1 Bit 0 Bits Frame BC2 BC1 BC0 Synchronous Serial Format I2 C Bus Format 0 0 0 8 9 Initial value 1 1 2 1 0 2 3 1 3 4 1 0 0 4 5 1 5 6 1 0 6 7 1 7 8 15 2 5 I2 C Bus Control Register ICCR Bit Initial value Read Write Note Only 0 can be written to clear the flag 7 ICE 0 R W 6 IEIC 0 R W 5 MST 0 R W 4 TRS 0 R W 3 ACKE 0 R W 0 SCP 1 W 2 BBSY 0 R W 1 IRIC 0 R W ...

Page 327: ...les interrupts from the I2 C bus interface to the CPU Bit 6 IEIC Description 0 Interrupts disabled Initial value 1 Interrupts enabled Bit 5 Master Slave Select MST Bit 4 Transmit Receive Select TRS MST selects whether the I2 C bus interface operates in master mode or slave mode TRS selects whether the I2 C bus interface operates in transmit mode or receive mode In master mode with the I2 C bus for...

Page 328: ...en in MST after reading MST 0 in case of clearing condition 2 Bit 4 TRS Description 0 Receive mode Initial value Clearing conditions 1 When 0 is written by software in cases other than setting condition 3 2 When 0 is written in TRS after reading TRS 1 in case of clearing condition 3 3 When bus arbitration is lost after transmission is started in I2 C bus format master mode 1 Transmit mode Setting ...

Page 329: ...uction to write 1 in BBSY and 0 in SCP A retransmit start condition is issued in the same way To issue a stop condition use a MOV instruction to write 0 in BBSY and 0 in SCP It is not possible to write to BBSY in slave mode the I2 C bus interface must be set to master transmit mode before issuing a start condition MST and TRS should both be set to 1 before writing 1 in BBSY and 0 in SCP Bit 2 BBSY...

Page 330: ...s received after bus arbitration is lost when the AL flag is set to 1 5 When 1 is received as the acknowledge bit when the ACKE bit is 1 when the ACKB bit is set to 1 I2 C bus format slave mode 1 When the slave address SVA SVAX matches when the AAS and AASX flags are set to 1 and at the end of data transfer up to the subsequent retransmission start condition or stop condition detection when the TD...

Page 331: ...er States MST TRS BBSY ESTP STOP IRTR AASX AL AAS ADZ ACKB State 1 0 1 0 0 0 0 0 0 0 0 0 0 Idle state flag clearing required 1 1 0 0 0 0 0 0 0 0 0 Start condition issuance 1 1 1 0 0 1 0 0 0 0 0 Start condition established 1 1 0 1 0 0 0 0 0 0 0 0 1 Master mode wait 1 1 0 1 0 0 1 0 0 0 0 0 1 Master mode transmit receive end 0 0 1 0 0 0 1 0 1 1 0 1 0 0 Arbitration lost 0 0 1 0 0 0 0 0 1 0 0 SAR match...

Page 332: ...ster ICSR Bit Initial value Read Write Note Only 0 can be written to clear the flags 7 ESTP 0 R W 6 STOP 0 R W 5 IRTR 0 R W 4 AASX 0 R W 3 AL 0 R W 0 ACKB 0 R W 2 AAS 0 R W 1 ADZ 0 R W ICSR is an 8 bit readable writable register that performs flag confirmation and acknowledge confirmation and control ICSR is initialized to H 00 by a reset Bit 7 Error Stop Condition Detection Flag ESTP Indicates th...

Page 333: ...rupt request to the CPU and the source is completion of reception transmission of one frame in continuous transmission reception When the IRTR flag is set to 1 the IRIC flag is also set to 1 at the same time IRTR flag setting is performed when the TDRE or RDRF flag is set to 1 IRTR is cleared by reading IRTR after it has been set to 1 then writing 0 in IRTR IRTR is also cleared automatically when ...

Page 334: ...dicates that arbitration was lost in master mode The I2 C bus interface monitors the bus When two or more master devices attempt to seize the bus at nearly the same time if the I2 C bus interface detects data differing from the data it sent it sets AL to 1 to indicate that the bus has been taken by another master AL is cleared by reading AL after it has been set to 1 then writing 0 in AL In additi...

Page 335: ... 3 In master mode 1 Setting condition When the slave address or general call address is detected in slave receive mode and FS 0 Bit 1 General Call Address Recognition Flag ADZ In I2 C bus format slave receive mode this flag is set to 1 if the first frame following a start condition is the general call address H 00 ADZ is cleared by reading ADZ after it has been set to 1 then writing 0 in ADZ In ad...

Page 336: ... mode 1 is output at acknowledge output timing Transmit mode Indicates that the receiving device has not acknowledged the data signal is 1 15 2 7 Timer Serial Control Register TSCR Bit 7 6 5 4 3 2 1 0 IICRST IICX Initial value 1 1 1 1 1 1 0 0 Read Write R W R W TSCR is an 8 bit readable writable register that controls the I2 C interface operating mode TSCR is initialized to H FC by a reset Bits 7 ...

Page 337: ...he symbols used in figures 15 3 to 15 5 are explained in table 15 4 S SLA R W A DATA A A A P 1 1 1 1 n 7 1 m a I2C bus format FS 0 or FSX 0 b I2C bus format start condition retransmission FS 0 or FSX 0 n transfer bit count n 1 to 8 m transfer frame count m 1 S SLA R W A DATA 1 1 1 n1 7 1 m1 S SLA R W A DATA A A P 1 1 1 n2 7 1 m2 1 1 1 A A n1 and n2 transfer bit count n1 and n2 1 to 8 m1 and m2 tra...

Page 338: ...e device returns an acknowledge signal The transmission procedure and operations synchronize with the ICDR writing are described below 1 Set the ICE bit in ICCR to 1 Set bits MLS WAIT and CKS2 to CKS0 in ICMR and bit IICX in TSCR according to the operating mode 2 Read the BBSY flag in ICCR to confirm that the bus is free 3 Set bits MST and TRS to 1 in ICCR to select master transmit mode 4 Write 1 ...

Page 339: ...end of the transfer and so the IRIC flag is cleared to 0 After writing ICDR clear IRIC immediately not to execute other interrupt handling routine The master device sequentially sends the transmission clock and the data written to ICDR Transmission of the next frame is performed in synchronization with the internal clock 10 When one frame of data has been transmitted the IRIC flag is set to 1 at t...

Page 340: ...smit mode to receive mode and set the WAIT bit in ICMR to 1 Also clear the bit in ICSR to ACKB 0 acknowledge data setting 2 When ICDR is read dummy data read reception is started and the receive clock is output and data received in synchronization with the internal clock In order to detect wait operation set the IRIC flag in ICCR must be cleared to 0 After reading ICDR clear IRIC immediately not t...

Page 341: ...tep 5 to 9 10 Set the ACKB bit in ICSR to 1 so as to return No acknowledge data Also set the TRS bit to 1 to switch from receive mode to transmit mode 11 Clear IRIC flag to 0 to release from the Wait State 12 When one frame of data has been received the IRIC flag is set to 1 at the rise of the 9th receive clock pulse 13 Clear the WAIT bit to 0 to switch from wait mode to no wait mode Read ICDR and...

Page 342: ...ccording to the operating mode 2 When the start condition output by the master device is detected the BBSY flag in ICCR is set to 1 3 When the slave address matches in the first frame following the start condition the device operates as the slave device specified by the master device If the 8th data bit R W is 0 the TRS bit in ICCR remains cleared to 0 and slave receive operation is performed 4 At...

Page 343: ... to 0 SDA master output SDA slave output 2 1 2 1 4 3 6 5 8 7 9 Bit 7 Bit 6 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 IRIC ICDRS ICDRR RDRF SCL master output Start condition issuance SCL slave output Interrupt request generation Address R W Address R W 5 ICDR read 5 IRIC clearance User processing Slave address Data 1 4 A R W Figure 15 8 Example of Slave Receive Mode Operation Timing 1 MLS ACK...

Page 344: ...bit in ICMR and the MST and TRS bits in ICCR according to the operating mode 2 When the slave address matches in the first frame following detection of the start condition the slave device drives SDA low at the 9th clock pulse and returns an acknowledge signal At the same time the IRIC flag in ICCR is set to 1 If the IEIC bit in ICCR has been set to 1 an interrupt request is sent to the CPU If the...

Page 345: ...ed and the TDRE internal flag and the IRIC and IRTR flags are set to 1 again 5 To continue transmission clear the IRIC flag to 0 then write the next data to be transmitted into ICDR The TDRE flag is cleared to 0 Transmit operations can be performed continuously by repeating steps 4 and 5 To end transmission write H FF to ICDR When SDA is changed from low to high when SCL is high and the stop condi...

Page 346: ...1 shows the IRIC set timing and SCL control a When WAIT 0 and FS 0 or FSX 0 I2C bus format no wait SCL SDA IRIC User processing Clear IRIC Write to ICDR transmit or read ICDR receive 1 A 8 1 1 A 7 1 8 9 7 b When WAIT 1 and FS 0 or FSX 0 I2C bus format wait inserted SCL SDA IRIC User processing Clear IRIC Clear IRIC Write to ICDR transmit or read ICDR receive SCL SDA IRIC User processing c When FS ...

Page 347: ...SDA input signal is sampled on the system clock but is not passed forward to the next circuit unless the outputs of both latches agree If they do not agree the previous value is held System clock period Sampling clock C D Q Latch C D Q Latch SCL or SDA input signal Match detector Internal SCL or SDA signal Sampling clock Figure 15 12 Block Diagram of Noise Canceler 15 3 8 Sample Flowcharts Figures...

Page 348: ...he status of the SCL and SDA lines 7 Wait for 1 byte to be transmitted 10 Wait for 1 byte to be transmitted 11 Test for end of tranfer 12 Stop condition issuance 8 Test the acknowledge bit transferred from slave device 5 Wait for a start condition Read IRIC in ICCR Read ACKB in ICSR IRIC 1 ACKB 0 Transmit mode Write transmit data in ICDR Clear IRIC in ICCR Read IRIC in ICCR Read ACKB in ICSR Clear...

Page 349: ...wait insertion 12 Wait for 1 byte to be received 13 Set WAIT 0 Read ICDR Clear IRIC Note After setting WAIT 0 IRIC should be cleared to 0 14 Stop condition issuance 8 Wait for the next data to be received 8th clock falling edge 5 Wait for 1 byte to be received 9th clock rising edge Read IRIC in ICCR Read ICDR Clear IRIC in ICCR IRIC 1 IRIC 1 Yes Last receive Last receive Set ACKB 1 in ICSR Set TRS...

Page 350: ...et ACKB 1 in ICSR Read ICDR Read IRIC in ICCR Read ICDR IRIC 1 Clear IRIC in ICCR End General call address processing Description omitted Slave transmit mode 1 Select slave receive mode 2 Wait for the first byte to be received slave address 3 Start receiving The first read is a dummy read 4 Wait for the transfer to end 5 Set acknowledge data for the last receive 6 Start the last receive 7 Wait for...

Page 351: ...Read ACKB in ICSR Set TRS 0 in ICCR End of transmission ACKB 1 Yes No No Yes End 1 2 3 Read ICDR 5 4 1 Set transmit data for the second and subsequent bytes 2 Wait for 1 byte to be transmitted 3 Test for end of transfer 4 Set slave receive mode 5 Dummy read to release the SCL line Figure 15 16 Flowchart for Slave Transmit Mode Example ...

Page 352: ...ead access to ICDR when ICE 1 and TRS 0 including automatic transfer from ICDRS to ICDRR Table 15 5 shows the timing of SCL and SDA output in synchronization with the internal clock Timings on the bus are determined by the rise and fall times of signals affected by the bus load capacitance series resistance and parallel resistance Table 15 5 I2 C Bus Timing SCL and SDA Output Item Symbol Output Ti...

Page 353: ...ns 300 ns 1 17 5tcyc Normal mode 1000 ns 1000 ns 1000 ns 1000 ns 1000 ns High speed mode 300 ns 300 ns 300 ns 300 ns 300 ns The I2 C bus interface specifications for the SCL and SDA rise and fall times are under 1000 ns and 300 ns The I2 C bus interface SCL and SDA output timing is prescribed by tScyc and tcyc as shown in table 15 6 However because of the rise and fall times the I2 C bus interface...

Page 354: ...tSDASO 1tSCLLO 2 3tcyc Standard mode 1000 250 3100 3325 3400 3513 master tSr High speed mode 300 100 400 625 700 813 tSDASO 1tSCLL 2 3tcyc Standard mode 1000 250 3100 3325 2400 3513 slave tSr High speed mode 300 100 400 625 700 813 tSDAHO 3tcyc Standard mode 0 0 600 375 300 188 High speed mode 0 0 600 375 300 188 Notes 1 Does not meet the I2 C bus interface specification Remedial action such as th...

Page 355: ...n generated and the bus has been released then read ICDR with TRS cleared to 0 Note that if the receive data ICDR data is read in the interval between execution of the instruction for issuance of the stop condition writing of 0 to BBSY and SCP in ICCR and the actual generation of the stop condition the clock may not be output correctly in subsequent master transmission Notes on Start Condition Iss...

Page 356: ... BBSY 1 SCP 0 ICSR 1 1 Wait for end of 1 byte transfer 2 Determine whether SCL is low 3 Issue restart condition instruction for transmission 4 Determine whether start condition is generated or not 5 Set transmit data slave address R W 2 3 4 5 Yes Yes No No IRIC 1 Yes SCL Low Start condition issuance No No Other processing Note Program so that processing from 3 to 5 is executed continuously 9 Figur...

Page 357: ... pin type four input channels High speed conversion Conversion time minimum 4 4 µs per channel with 16 MHz system clock Two operating modes Single mode A D conversion of one channel Scan mode continuous A D conversion on one to four channels Four 16 bit data registers A D conversion results are transferred for storage into data registers corresponding to the channels Sample and hold function Two c...

Page 358: ...nalog multi plexer Sample and hold circuit Comparator Control circuit ø 4 ø 8 ADI interrupt signal AVCC AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 Legend Note The 42 pin type does not have pins AN4 AN5 AN6 and AN7 ADCR ADCSR ADDRA ADDRB ADDRC ADDRD A D control register A D control status register A D data register A A D data register B A D data register C A D data register D ADTRG Figure 16 1 A D Converter B...

Page 359: ...r Pins Pin Name Abbrevi ation I O Function Analog power supply pin AVCC Input Analog power supply Analog input pin 0 AN0 Input Group 0 analog inputs Analog input pin 1 AN1 Input Analog input pin 2 AN2 Input Analog input pin 3 AN3 Input Analog input pin 4 AN4 Input Group 1 analog inputs Analog input pin 5 AN5 Input Analog input pin 6 AN6 Input Analog input pin 7 AN7 Input A D external trigger input...

Page 360: ...ister Descriptions 16 2 1 A D Data Registers A to D ADDRA to ADDRD Bit ADDRn Initial value 14 AD8 0 R 12 AD6 0 R 10 AD4 0 R 8 AD2 0 R 6 AD0 0 R 0 0 R 4 0 R 2 0 R 15 AD9 0 R 13 AD7 0 R 11 AD5 0 R 9 AD3 0 R 7 AD1 0 R 1 0 R 5 0 R 3 0 R A D conversion data 10 bit data giving an A D conversion result Reserved bits Read Write n A to D The four A D data registers ADDRA to ADDRD are 16 bit read only regis...

Page 361: ...A D Control Status Register ADCSR Bit Initial value Read Write 7 ADF 0 R W 6 ADIE 0 R W 5 ADST 0 R W 4 SCAN 0 R W 3 CKS 0 R W 0 CH0 0 R W 2 CH2 0 R W 1 CH1 0 R W Note Only 0 can be written to clear the flag A D end flag Indicates end of A D conversion A D interrupt enable Enables and disables A D end interrupts A D start Starts or stops A D conversion Scan mode Selects single mode or scan mode Clo...

Page 362: ...rts or stops A D conversion The ADST bit remains set to 1 during A D conversion It can also be set to 1 by external trigger input at the ADTRG pin Bit 5 ADST Description 0 A D conversion is stopped Initial value 1 Single mode A D conversion starts ADST is automatically cleared to 0 when conversion ends Scan mode A D conversion starts and continues cycling among the selected channels until ADST is ...

Page 363: ...election Description CH2 CH1 CH0 Single Mode Scan Mode 0 0 0 AN0 Initial value AN0 1 AN1 AN0 AN1 1 0 AN2 AN0 to AN2 1 AN3 AN0 to AN3 1 0 0 AN4 AN4 1 AN5 AN4 AN5 1 0 AN6 AN4 to AN6 1 AN7 AN4 to AN7 Note 1 can not be set on the 42 pin type 16 2 3 A D Control Register ADCR Bit Initial value Read Write 7 TRGE 0 R W 6 1 5 1 4 1 3 1 0 0 R W 2 1 1 1 Trigger enable Enables or disables starting of A D conv...

Page 364: ...itten but must not be set to 1 16 3 CPU Interface ADDRA to ADDRD are 16 bit registers but they are connected to the CPU by an 8 bit data bus Therefore although the upper byte can be be accessed directly by the CPU the lower byte is read through an 8 bit temporary register TEMP An A D data register is read as follows When the upper byte is read the upper byte value is transferred directly to the CP...

Page 365: ...ace Module data bus CPU H AA ADDRnH H AA ADDRnL H 40 Lower byte read Bus interface Module data bus CPU H 40 ADDRnH H AA ADDRnL H 40 TEMP H 40 TEMP H 40 n A to D n A to D Figure 16 2 A D Data Register Access Operation Reading H AA40 ...

Page 366: ... D conversion After making the necessary changes set the ADST bit to 1 to start A D conversion again The ADST bit can be set at the same time as the mode or channel is changed Typical operations when channel 1 AN1 is selected in single mode are described next Figure 16 3 shows a timing diagram for this example 1 Single mode is selected SCAN 0 input channel AN1 is selected CH2 CH1 0 CH0 1 the A D i...

Page 367: ...version result 1 Read conversion result A D conversion result 2 Note Vertical arrows indicate instructions executed by software A D conversion starts ADDRA ADDRB ADDRC ADDRD State of channel 1 AN1 State of channel 2 AN2 State of channel 3 AN3 Idle Idle Idle Idle Figure 16 3 Example of A D Converter Operation Single Mode Channel 1 Selected ...

Page 368: ...irst channel in the group The ADST bit can be set at the same time as the mode or channel selection is changed Typical operations when three channels in group 0 AN0 to AN2 are selected in scan mode are described next Figure 16 4 shows a timing diagram for this example 1 Scan mode is selected SCAN 1 scan group 0 is selected CH2 0 analog input channels AN0 to AN2 are selected CH1 1 CH0 0 and A D con...

Page 369: ...ansfer A D conversion result 1 A D conversion result 4 A D conversion result 2 A D conversion result 3 1 2 A D conversion time Notes 2 1 ADDRA ADDRB ADDRC ADDRD State of channel 1 AN1 State of channel 2 AN2 State of channel 3 AN3 Vertical arrows indicate instructions executed by software Data currently being converted is ignored Figure 16 4 Example of A D Converter Operation Scan Mode Channels AN0...

Page 370: ... time The length of tD varies depending on the timing of the write access to ADCSR The total conversion time therefore varies within the ranges indicated in table 16 4 In scan mode the values given in table 16 4 apply to the first conversion In the second and subsequent conversions the conversion time is fixed at 128 states when CKS 0 or 66 states when CKS 1 φ Address bus Write signal Input sampli...

Page 371: ...iming A D conversion can be externally triggered When the TRGE bit is set to 1 in ADCR external trigger input is enabled at the ADTRG pin A rising or falling edge on the ADTRG input pin sets the ADST bit to 1 in ADCSR starting A D conversion Other operations in both single and scan modes are the same as if the ADST bit had been set to 1 by software Figure 16 6 shows the timing φ ADTRG Internal tri...

Page 372: ... input voltage required to raise digital output from minimum voltage value 0000000000 to 0000000001 figure 16 8 Full scale error Deviation from ideal A D conversion characteristic of analog input voltage required to raise digital output from 1111111110 to 1111111111 figure 16 8 Quantization error Intrinsic error of the A D converter 1 2 LSB figure 16 7 Nonlinearity error Deviation from ideal A D c...

Page 373: ...Digital output Ideal A D conversion characteristic Figure 16 7 A D Converter Accuracy Definitions 1 FS Offset error Nonlinearity error Actual A D conversion characteristic Analog input voltage Digital output Ideal A D conversion characteristic Full scale error Figure 16 8 A D Converter Accuracy Definitions 2 ...

Page 374: ...ignal source is not a problem A large external capacitor however acts as a low pass filter This may make it impossible to track analog signals with high dv dt e g a variation of 5 mV µs figure 16 9 To convert high speed analog signals or to use scan mode insert a low impedance buffer 3 Effect on Absolute Accuracy Attaching an external capacitor creates a coupling with ground so if there is noise o...

Page 375: ... without using the internal power supply step down circuit 17 2 When Using the Internal Power Supply Step Down Circuit Connect the external power supply to the VCC pin and connect a capacitance of approximately 0 1 µF between CVCC and VSS as shown in figure 17 1 The internal step down circuit is made effective simply by adding this external circuit Notes 1 In the external circuit interface the ext...

Page 376: ... external power supply is then input directly to the internal power supply Note The permissible range for the power supply voltage is 3 0 V to 3 6 V Operation cannot be guaranteed if a voltage outside this range less than 3 0 V or more than 3 6 V is input VCL VSS Internal logic Step down circuit Internal power supply VCC VCC 3 0 to 3 6 V Figure 17 2 Power Supply Connection when Internal Step Down ...

Page 377: ...r 20 to 75 C Storage temperature Tstg 55 to 125 C Note Permanent damage may occur to the chip if maximum ratings are exceeded Normal operation should be under the conditions specified in Electrical Characteristics Exceeding these values can result in incorrect operation and reduced reliability 18 2 Electrical Characteristics F ZTAT Version 18 2 1 Power Supply Voltage and Operating Ranges Power Sup...

Page 378: ...00 3 0 4 0 5 5 VCC V ø kHz AVCC 3 3 V to 5 5 V Active mode Sleep mode When MA2 0 in SYSCR2 AVCC 3 3 V to 5 5 V Subactive mode Subsleep mode AVCC 3 3 V to 5 5 V Active mode Sleep mode When MA2 1 in SYSCR2 Analog Power Supply Voltage and A D Converter Accuracy Guarantee Range 10 0 2 0 16 0 3 3 4 0 5 5 AVCC V ø MHz VCC 3 0 V to 5 5 V Active mode Sleep mode ...

Page 379: ...9 VCC VCC 0 3 RXD SCL SDA P10 to P12 P14 to P17 P20 to P22 0 7 VCC VCC 0 3 V VCC 4 0 V to 5 5 V P50 to P57 P74 to P76 P80 to P87 0 8 VCC VCC 0 3 PB0 to PB7 0 7 VCC AVCC 0 3 V VCC 4 0 V to 5 5 V 0 8 VCC AVCC 0 3 OSC1 VCC 0 5 VCC 0 3 V VCC 4 0 V to 5 5 V VCC 0 3 VCC 0 3 Input low voltage VIL RES NMI WKP0 to WKP5 IRQ0 to IRQ3 ADTRG TMRIV 0 3 0 2 VCC V VCC 4 0 V to 5 5 V TMCIV FTCI FTIOA to FTIOD SCK3...

Page 380: ...22 0 6 V VCC 4 0 V to 5 5 V IOL 1 6 mA P50 to P57 P74 to P76 0 4 IOL 0 4 mA P80 to P87 1 5 V VCC 4 0 V to 5 5 V IOL 20 0 mA 1 0 VCC 4 0 V to 5 5 V IOL 10 0 mA 0 4 VCC 4 0 V to 5 5 V IOL 1 6 mA 0 4 IOL 0 4 mA SCL SDA 0 6 V VCC 4 0 V to 5 5 V IOL 6 0 mA 0 4 IOL 3 0 mA Input output leakage current IIL OSC1 RES NMI WKP0 to WKP5 IRQ0 to IRQ3 ADTRG TRGV TMRIV TMCIV FTCI FTIOA to FTIOD RXD SCK3 SCL SDA 1...

Page 381: ...lue IOPE2 VCC 1 8 2 7 mA Active mode 2 VCC 5 0 V fOSC 16 MHz 1 2 Active mode 2 VCC 3 0 V fOSC 10 MHz Reference value Sleep mode current ISLEEP1 VCC 11 5 17 0 mA Sleep mode 1 VCC 5 0 V fOSC 16 MHz dissipation 6 5 Sleep mode 1 VCC 3 0 V fOSC 10 MHz Reference value ISLEEP2 VCC 1 7 2 5 mA Sleep mode 2 VCC 5 0 V fOSC 16 MHz 1 1 Sleep mode 2 VCC 3 0 V fOSC 10 MHz Reference value Subactive mode current d...

Page 382: ...fers Mode RES Pin Internal State Other Pins Oscillator Pins Active mode 1 VCC Operates VCC System clock oscillator ceramic or crystal Active mode 2 Operates ø 64 Subclock oscillator Pin X1 VSS Sleep mode 1 VCC Only timers operate VCC Sleep mode 2 Only timers operate ø 64 Subactive mode VCC Operates VCC System clock oscillator ceramic or crystal Subsleep mode VCC Only time base operates VCC Subcloc...

Page 383: ... 5 5 V Port 8 20 0 SCL and SDA 6 0 Port 8 10 0 Output pins except port 8 SCL and SDA 0 5 Allowable output low current total Output pins except port 8 SCL and SDA IOL 40 0 mA VCC 4 0 V to 5 5 V Port 8 SCL and SDA 80 0 Output pins except port 8 SCL and SDA 20 0 Port 8 SCL and SDA 40 0 Allowable output high All output pins IOH 2 0 mA VCC 4 0 V to 5 5 V current per pin 0 2 Allowable output high All ou...

Page 384: ...4 tOSC 2 cycle time 12 8 µs Subclock oscillation frequency fW X1 X2 32 768 kHz Watch clock øW cycle time tW X1 X2 30 5 µs Subclock øSUB cycle time tsubcyc 2 8 tW 2 Instruction cycle time 2 tcyc tsubcyc Oscillation stabilization time crystal oscillator trc OSC1 OSC2 10 0 ms Oscillation stabilization time ceramic oscillator trc OSC1 OSC2 5 0 ms Oscillation stabilization time trcx X1 X2 2 0 s Externa...

Page 385: ...ode operation Input pin high width tIH NMI IRQ0 to IRQ3 WKP0 to WKP5 TMCIV TMRIV TRGV ADTRG FTCI FTIOA to FTIOD 2 tcyc tsubcyc Figure 18 3 Input pin low width tIL NMI IRQ0 to IRQ3 WKP0 to WKP5 TMCIV TMRIV TRGV ADTRG FTIOA to FTIOD 2 tcyc tsubcyc Notes 1 When an external clock is input the minimum system clock oscillator frequency is 1 0 MHz 2 Determined by MA2 MA1 MA0 SA1 and SA0 of system control...

Page 386: ...d SDA tSf 300 ns SCL and SDA input spike pulse removal time tSP 1tcyc ns SDA input bus free time tBUF 5tcyc ns Start condition input hold time tSTAH 3tcyc ns Retransmission start condition input setup time tSTAS 3tcyc ns Setup time for stop condition input tSTOS 3tcyc ns Data input setup time tSDAS 0 5tcyc ns Data input hold time tSDAH 0 ns Capacitive load of SCL and SDA cb 0 400 pF SCL and SDA ou...

Page 387: ...Input clock Asynchro nous tScyc SCK3 4 tcyc Figure 18 5 cycle Synchro nous 6 Input clock pulse width tSCKW SCK3 0 4 0 6 tScyc Figure 18 5 Transmit data delay tTXD TXD 1 tcyc VCC 4 0 V to 5 5 V Figure 18 6 time synchronous 1 Receive data setup tRXS RXD 62 5 ns VCC 4 0 V to 5 5 V Figure 18 6 time synchronous 100 0 Receive data hold tRXH RXD 62 5 ns VCC 4 0 V to 5 5 V Figure 18 6 time synchronous 100...

Page 388: ...5 0 V fOSC 16 MHz supply current AISTOP1 AVCC 50 µA 2 Reference value AISTOP2 AVCC 5 0 µA 3 Analog input capacitance CAIN AN0 to AN7 30 0 pF Allowable signal source impedance RAIN AN0 to AN7 5 0 kΩ Resolution 10 10 10 bit Conversion time single mode 134 tcyc AVCC 3 3 V to 5 5 V Nonlinearity error 7 5 LSB Offset error 7 5 LSB Full scale error 7 5 LSB Quantization error 0 5 LSB Absolute accuracy 8 0...

Page 389: ...ive and sleep modes while the A D converter is idle 3 AISTOP2 is the current at reset and in standby subactive and subsleep modes while the A D converter is idle 18 2 5 Watchdog Timer Table 18 7 Watchdog Timer Characteristics VCC 3 0 V to 5 5 V VSS 0 0 V Ta 20 C to 75 C unless otherwise specified Applicable Values Test Reference Item Symbol Pins Min Typ Max Unit Condition Figure On chip oscillator...

Page 390: ...ogramming count NWEC 100 Times Programming Wait time after SWE bit setting x 1 µs 1 Wait time after PSU bit setting y 50 µs 1 Wait time after P bit setting z1 1 n 6 28 30 32 µs 1 4 z2 7 n 1000 198 200 202 µs z3 Additional programming 8 10 12 µs Wait time after P bit clear α 5 µs 1 Wait time after PSU bit clear β 5 µs 1 Wait time after PV bit setting γ 4 µs 1 Wait time after dummy write ε 2 µs 1 Wa...

Page 391: ...1 is set The program verify time is not included 3 The time required to erase one block Indicates the time for which the E bit in flash memory control register 1 FLMCR1 is set The erase verify time is not included 4 Programming time maximum value tP MAX wait time after P bit setting z maximum number of writes N 5 Set the maximum number of writes N according to the actual set values of z1 z2 and z3...

Page 392: ...8 3 1 Power Supply Voltage and Operating Ranges Power Supply Voltage and Oscillation Frequency Range 10 0 2 0 16 0 2 7 4 0 5 5 VCC V øOSC MHz 32 768 2 7 4 0 5 5 VCC V øW kHz AVCC 3 0 V to 5 5 V Active mode Sleep mode AVCC 3 0 V to 5 5 V All operating modes ...

Page 393: ... 5 5 VCC V ø kHz AVCC 3 0 V to 5 5 V Active mode Sleep mode When MA2 0 in SYSCR2 AVCC 3 0 V to 5 5 V Subactive mode Subsleep mode AVCC 3 0 V to 5 5 V Active mode Sleep mode When MA2 1 in SYSCR2 Analog Power Supply Voltage and A D Converter Accuracy Guarantee Range 10 0 2 0 16 0 3 0 4 0 5 5 AVCC V ø MHz AVCC 2 7 V to 5 5 V VCC 3 0 V to 5 5 V Active mode Sleep mode ...

Page 394: ...9 VCC VCC 0 3 RXD SCL SDA P10 to P12 P14 to P17 P20 to P22 0 7 VCC VCC 0 3 V VCC 4 0 V to 5 5 V P50 to P57 P74 to P76 P80 to P87 0 8 VCC VCC 0 3 PB0 to PB7 0 7 VCC AVCC 0 3 V VCC 4 0 V to 5 5 V 0 8 VCC AVCC 0 3 OSC1 VCC 0 5 VCC 0 3 V VCC 4 0 V to 5 5 V VCC 0 3 VCC 0 3 Input low voltage VIL RES NMI WKP0 to WKP5 IRQ0 to IRQ3 ADTRG TMRIV 0 3 0 2 VCC V VCC 4 0 V to 5 5 V TMCIV FTCI FTIOA to FTIOD SCK3...

Page 395: ...22 0 6 V VCC 4 0 V to 5 5 V IOL 1 6 mA P50 to P57 P74 to P76 0 4 IOL 0 4 mA P80 to P87 1 5 V VCC 4 0 V to 5 5 V IOL 20 0 mA 1 0 VCC 4 0 V to 5 5 V IOL 10 0 mA 0 4 VCC 4 0 V to 5 5 V IOL 1 6 mA 0 4 IOL 0 4 mA SCL SDA 0 6 V VCC 4 0 V to 5 5 V IOL 6 0 mA 0 4 IOL 3 0 mA Input output leakage current IIL OSC1 RES NMI WKP0 to WKP5 IRQ0 to IRQ3 ADTRG TRGV TMRIV TMCIV FTCI FTIOA to FTIOD RXD SCK3 SCL SDA 1...

Page 396: ...alue IOPE2 VCC 1 8 2 7 mA Active mode 2 VCC 5 0 V fOSC 16 MHz 1 2 Active mode 2 VCC 3 0 V fOSC 10 MHz Reference value Sleep mode current ISLEEP1 VCC 7 1 13 0 mA Sleep mode 1 VCC 5 0 V fOSC 16 MHz dissipation 4 0 Sleep mode 1 VCC 3 0 V fOSC 10 MHz Reference value ISLEEP2 VCC 1 1 2 0 mA Sleep mode 2 VCC 5 0 V fOSC 16 MHz 0 5 Sleep mode 2 VCC 3 0 V fOSC 10 MHz Reference value Subactive mode current d...

Page 397: ...fers Mode RES Pin Internal State Other Pins Oscillator Pins Active mode 1 VCC Operates VCC System clock oscillator ceramic or crystal Active mode 2 Operates ø 64 Subclock oscillator Pin X1 VSS Sleep mode 1 VCC Only timers operate VCC Sleep mode 2 Only timers operate ø 64 Subactive mode VCC Operates VCC System clock oscillator ceramic or crystal Subsleep mode VCC Only time base operates VCC Subcloc...

Page 398: ... 5 5 V Port 8 20 0 SCL and SDA 6 0 Port 8 10 0 Output pins except port 8 SCL and SDA 0 5 Allowable output low current total Output pins except port 8 SCL and SDA IOL 40 0 mA VCC 4 0 V to 5 5 V Port 8 SCL and SDA 80 0 Output pins except port 8 SCL and SDA 20 0 Port 8 SCL and SDA 40 0 Allowable output high All output pins IOH 2 0 mA VCC 4 0 V to 5 5 V current per pin 0 2 Allowable output high All ou...

Page 399: ... 64 tOSC 2 cycle time 12 8 µs Subclock oscillation frequency fW X1 X2 32 768 kHz Watch clock øW cycle time tW X1 X2 30 5 µs Subclock øSUB cycle time tsubcyc 2 8 tW 2 Instruction cycle time 2 tcyc tsubcyc Oscillation stabilization time crystal oscillator trc OSC1 OSC2 10 0 ms Oscillation stabilization time ceramic oscillator trc OSC1 OSC2 5 0 ms Oscillation stabilization time trcx X1 X2 2 0 s Exter...

Page 400: ...ode operation Input pin high width tIH NMI IRQ0 to IRQ3 WKP0 to WKP5 TMCIV TMRIV TRGV ADTRG FTCI FTIOA to FTIOD 2 tcyc tsubcyc Figure 18 3 Input pin low width tIL NMI IRQ0 to IRQ3 WKP0 to WKP5 TMCIV TMRIV TRGV ADTRG FTIOA to FTIOD 2 tcyc tsubcyc Notes 1 When an external clock is input the minimum system clock oscillator frequency is 1 0 MHz 2 Determined by MA2 MA1 MA0 SA1 and SA0 of system control...

Page 401: ...d SDA tSf 300 ns SCL and SDA input spike pulse removal time tSP 1tcyc ns SDA input bus free time tBUF 5tcyc ns Start condition input hold time tSTAH 3tcyc ns Retransmission start condition input setup time tSTAS 3tcyc ns Setup time for stop condition input tSTOS 3tcyc ns Data input setup time tSDAS 0 5tcyc ns Data input hold time tSDAH 0 ns Capacitive load of SCL and SDA cb 0 400 pF SCL and SDA ou...

Page 402: ...Input clock Asynchro nous tScyc SCK3 4 tcyc Figure 18 5 cycle Synchro nous 6 Input clock pulse width tSCKW SCK3 0 4 0 6 tScyc Figure 18 5 Transmit data delay tTXD TXD 1 tcyc VCC 4 0 V to 5 5 V Figure 18 6 time synchronous 1 Receive data setup tRXS RXD 62 5 ns VCC 4 0 V to 5 5 V Figure 18 6 time synchronous 100 0 Receive data hold tRXH RXD 62 5 ns VCC 4 0 V to 5 5 V Figure 18 6 time synchronous 100...

Page 403: ...5 0 V fOSC 16 MHz supply current AISTOP1 AVCC 50 µA 2 Reference value AISTOP2 AVCC 5 0 µA 3 Analog input capacitance CAIN AN0 to AN7 30 0 pF Allowable signal source impedance RAIN AN0 to AN7 5 0 kΩ Resolution 10 10 10 bit Conversion time single mode 134 tcyc AVCC 3 0 V to 5 5 V Nonlinearity error 7 5 LSB Offset error 7 5 LSB Full scale error 7 5 LSB Quantization error 0 5 LSB Absolute accuracy 8 0...

Page 404: ...ive and sleep modes while the A D converter is idle 3 AISTOP2 is the current at reset and in standby subactive and subsleep modes while the A D converter is idle 18 3 5 Watchdog Timer Table 18 14 Watchdog Timer Characteristics VCC 2 7 V to 5 5 V VSS 0 0 V Ta 20 C to 75 C unless otherwise specified Applicable Values Test Reference Item Symbol Pins Min Typ Max Unit Condition Figure On chip oscillato...

Page 405: ... tCPL tCPr OSC1 tCPf Figure 18 1 System Clock Input Timing tREL VIL RES tREL VIL VCC 0 7 VCC OSC1 Figure 18 2 RES Low Width Timing VIH VIL tIL NMI IRQ0 to IRQ3 WKP0 to WKP5 ADTRG TMCI FTIOA to FTIOD TMCIV TMRIV TRGV tIH Figure 18 3 Input Timing ...

Page 406: ...tSCLH tSCLL SDA Sr tSTAS tSP tSTOS tSDAS P Note S P and Sr represent the following S Start condition P Stop condition Sr Retransmission start condition Figure 18 4 I2 C Bus Interface Input Output Timing tScyc tSCKW SCK3 Figure 18 5 SCK3 Input Clock Timing ...

Page 407: ... or V IL OL VOL SCK3 TXD transmit data RXD receive data Note Output timing reference levels Output high Output low Load conditions are shown in figure 18 7 V 2 0 V V 0 8 V OH OL Figure 18 6 Serial Interface 3 Synchronous Mode Input Output Timing ...

Page 408: ...392 18 5 Output Load Circuit VCC 2 4 kΩ 12 kΩ 30 pF LSI output pin Figure 18 7 Output Load Condition ...

Page 409: ...flow flag in CCR C C carry flag in CCR disp Displacement Transfer from the operand on the left to the operand on the right or transition from the state on the left to the state on the right Addition of the operands on both sides Subtraction of the operand on the right from the operand on the left Multiplication of the operands on both sides Division of the operand on the left by the operand on the...

Page 410: ... Notation Symbol Description Changed according to execution result Undetermined no guaranteed value 0 Cleared to 0 1 Set to 1 Not affected by execution of the instruction Varies depending on conditions described in notes ...

Page 411: ... MOV W d 16 ERs Rd MOV W d 24 ERs Rd MOV W ERs Rd MOV W aa 16 Rd MOV W aa 24 Rd MOV W Rs ERd MOV W Rs d 16 ERd MOV W Rs d 24 ERd xx 8 Rd8 Rs8 Rd8 ERs Rd8 d 16 ERs Rd8 d 24 ERs Rd8 ERs Rd8 ERs32 1 ERs32 aa 8 Rd8 aa 16 Rd8 aa 24 Rd8 Rs8 ERd Rs8 d 16 ERd Rs8 d 24 ERd ERd32 1 ERd32 Rs8 ERd Rs8 aa 8 Rs8 aa 16 Rs8 aa 24 xx 16 Rd16 Rs16 Rd16 ERs Rd16 d 16 ERs Rd16 d 24 ERs Rd16 ERs Rd16 ERs32 2 ERd32 aa ...

Page 412: ...d MOVTPE Rs aa 16 ERd32 2 ERd32 Rs16 ERd Rs16 aa 16 Rs16 aa 24 xx 32 Rd32 ERs32 ERd32 ERs ERd32 d 16 ERs ERd32 d 24 ERs ERd32 ERs ERd32 ERs32 4 ERs32 aa 16 ERd32 aa 24 ERd32 ERs32 ERd ERs32 d 16 ERd ERs32 d 24 ERd ERd32 4 ERd32 ERs32 ERd ERs32 aa 16 ERs32 aa 24 SP Rn16 SP 2 SP SP ERn32 SP 4 SP SP 2 SP Rn16 SP SP 4 SP ERn32 SP Cannot be used in the H8 3664 Series Cannot be used in the H8 3664 Serie...

Page 413: ...SUBS L 2 ERd SUBS L 4 ERd DEC B Rd DEC W 1 Rd DEC W 2 Rd Rd8 xx 8 Rd8 Rd8 Rs8 Rd8 Rd16 xx 16 Rd16 Rd16 Rs16 Rd16 ERd32 xx 32 ERd32 ERd32 ERs32 ERd32 Rd8 xx 8 C Rd8 Rd8 Rs8 C Rd8 ERd32 1 ERd32 ERd32 2 ERd32 ERd32 4 ERd32 Rd8 1 Rd8 Rd16 1 Rd16 Rd16 2 Rd16 ERd32 1 ERd32 ERd32 2 ERd32 Rd8 decimal adjust Rd8 Rd8 Rs8 Rd8 Rd16 xx 16 Rd16 Rd16 Rs16 Rd16 ERd32 xx 32 ERd32 ERd32 ERs32 ERd32 Rd8 xx 8 C Rd8 R...

Page 414: ...Rd8 decimal adjust Rd8 Rd8 Rs8 Rd16 unsigned multiplication Rd16 Rs16 ERd32 unsigned multiplication Rd8 Rs8 Rd16 signed multiplication Rd16 Rs16 ERd32 signed multiplication Rd16 Rs8 Rd16 RdH remainder RdL quotient unsigned division ERd32 Rs16 ERd32 Ed remainder Rd quotient unsigned division Rd16 Rs8 Rd16 RdH remainder RdL quotient signed division ERd32 Rs16 ERd32 Ed remainder Rd quotient signed di...

Page 415: ...n ERn d ERn ERn ERn aa d PC aa NEG B Rd NEG W Rd NEG L ERd EXTU W Rd EXTU L ERd EXTS W Rd EXTS L ERd 0 Rd8 Rd8 0 Rd16 Rd16 0 ERd32 ERd32 0 bits 15 to 8 of Rd16 0 bits 31 to 16 of ERd32 bit 7 of Rd16 bits 15 to 8 of Rd16 bit 15 of ERd32 bits 31 to 16 of ERd32 B W L W L W L 2 2 2 2 2 2 2 2 2 2 2 2 2 2 Normal Advanced 0 0 0 0 0 0 ...

Page 416: ... W xx 16 Rd XOR W Rs Rd XOR L xx 32 ERd XOR L ERs ERd NOT B Rd NOT W Rd NOT L ERd Rd8 xx 8 Rd8 Rd8 Rs8 Rd8 Rd16 xx 16 Rd16 Rd16 Rs16 Rd16 ERd32 xx 32 ERd32 ERd32 ERs32 ERd32 Rd8 xx 8 Rd8 Rd8 Rs8 Rd8 Rd16 xx 16 Rd16 Rd16 Rs16 Rd16 ERd32 xx 32 ERd32 ERd32 ERs32 ERd32 Rd8 xx 8 Rd8 Rd8 Rs8 Rd8 Rd16 xx 16 Rd16 Rd16 Rs16 Rd16 ERd32 xx 32 ERd32 ERd32 ERs32 ERd32 Rd8 Rd8 Rd16 Rd16 Rd32 Rd32 B B W W L L B ...

Page 417: ...d SHLL L ERd SHLR B Rd SHLR W Rd SHLR L ERd ROTXL B Rd ROTXL W Rd ROTXL L ERd ROTXR B Rd ROTXR W Rd ROTXR L ERd ROTL B Rd ROTL W Rd ROTL L ERd ROTR B Rd ROTR W Rd ROTR L ERd B W L B W L B W L B W L B W L B W L B W L B W L 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 Normal Advanced MSB LSB 0 C MSB LSB 0 C ...

Page 418: ... xx 3 ERd BTST xx 3 aa 8 BTST Rn Rd BTST Rn ERd BTST Rn aa 8 BLD xx 3 Rd xx 3 of Rd8 1 xx 3 of ERd 1 xx 3 of aa 8 1 Rn8 of Rd8 1 Rn8 of ERd 1 Rn8 of aa 8 1 xx 3 of Rd8 0 xx 3 of ERd 0 xx 3 of aa 8 0 Rn8 of Rd8 0 Rn8 of ERd 0 Rn8 of aa 8 0 xx 3 of Rd8 xx 3 of Rd8 xx 3 of ERd xx 3 of ERd xx 3 of aa 8 xx 3 of aa 8 Rn8 of Rd8 Rn8 of Rd8 Rn8 of ERd Rn8 of ERd Rn8 of aa 8 Rn8 of aa 8 xx 3 of Rd8 Z xx 3 ...

Page 419: ...x 3 aa 8 BIXOR xx 3 Rd BIXOR xx 3 ERd BIXOR xx 3 aa 8 xx 3 of ERd C xx 3 of aa 8 C xx 3 of Rd8 C xx 3 of ERd C xx 3 of aa 8 C C xx 3 of Rd8 C xx 3 of ERd24 C xx 3 of aa 8 C xx 3 of Rd8 C xx 3 of ERd24 C xx 3 of aa 8 C xx 3 of Rd8 C C xx 3 of ERd24 C C xx 3 of aa 8 C C xx 3 of Rd8 C C xx 3 of ERd24 C C xx 3 of aa 8 C C xx 3 of Rd8 C C xx 3 of ERd24 C C xx 3 of aa 8 C C xx 3 of Rd8 C C xx 3 of ERd24...

Page 420: ...16 BHS d 16 BCS d 8 BLO d 8 BCS d 16 BLO d 16 BNE d 8 BNE d 16 BEQ d 8 BEQ d 16 BVC d 8 BVC d 16 BVS d 8 BVS d 16 BPL d 8 BPL d 16 BMI d 8 BMI d 16 BGE d 8 BGE d 16 BLT d 8 BLT d 16 BGT d 8 BGT d 16 BLE d 8 BLE d 16 Always Never C Z 0 C Z 1 C 0 C 1 Z 0 Z 1 V 0 V 1 N 0 N 1 N V 0 N V 1 Z N V 0 Z N V 1 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 4 6 4 6 4 6 4 6 4 6 4 6 4 6 4 6 4 6...

Page 421: ...on Code I H N Z V C xx Rn ERn d ERn ERn ERn aa d PC aa JMP ERn JMP aa 24 JMP aa 8 BSR d 8 BSR d 16 JSR ERn JSR aa 24 JSR aa 8 RTS PC ERn PC aa 24 PC aa 8 PC SP PC PC d 8 PC SP PC PC d 16 PC SP PC ERn PC SP PC aa 24 PC SP PC aa 8 PC SP 2 2 4 4 2 4 2 2 2 4 6 Normal Advanced 8 6 8 6 8 8 8 10 8 10 8 10 12 10 ...

Page 422: ...d 16 ERd STC CCR d 24 ERd STC CCR ERd STC CCR aa 16 STC CCR aa 24 ANDC xx 8 CCR ORC xx 8 CCR XORC xx 8 CCR NOP PC SP CCR SP vector PC CCR SP PC SP Transition to power down state xx 8 CCR Rs8 CCR ERs CCR d 16 ERs CCR d 24 ERs CCR ERs CCR ERs32 2 ERs32 aa 16 CCR aa 24 CCR CCR Rd8 CCR ERd CCR d 16 ERd CCR d 24 ERd ERd32 2 ERd32 CCR ERd CCR aa 16 CCR aa 24 CCR xx 8 CCR CCR xx 8 CCR CCR xx 8 CCR PC PC ...

Page 423: ...cases see section A 3 Combinations of Instructions and Addressing Modes 2 n is the value set in register R4L or R4 1 Set to 1 when a carry or borrow occurs at bit 11 otherwise cleared to 0 2 Set to 1 when a carry or borrow occurs at bit 27 otherwise cleared to 0 3 Retains its previous value when the result is zero otherwise cleared to 0 4 Set to 1 when the adjustment produces a carry otherwise ret...

Page 424: ...ND LDC BEQ TRAPA BLD BILD BST BIST BVC MOV BPL JMP BMI EEPMOV ADDX SUBX BGT JSR BLE MOV ADD ADDX CMP SUBX OR XOR AND MOV Instruction when most significant bit of BH is 0 Instruction when most significant bit of BH is 1 Instruction code Table A 2 2 Table A 2 2 Table A 2 2 Table A 2 2 Table A 2 2 BVS BLT BGE BSR Table A 2 2 Table A 2 2 Table A 2 2 Table A 2 2 Table A 2 2 Table A 2 2 Table A 2 2 Tabl...

Page 425: ... CMP LDC STC BCC OR OR BPL BGT Instruction code BVS SLEEP BVC BGE Table A 2 3 Table A 2 3 Table A 2 3 ADD MOV SUB CMP BNE AND AND INC EXTU DEC BEQ INC EXTU DEC BCS XOR XOR SHLL SHLR ROTXL ROTXR NOT BLS SUB SUB BRN ADD ADD INC EXTS DEC BLT INC EXTS DEC BLE SHAL SHAR ROTL ROTR NEG BMI 1st byte 2nd byte AH BH AL BL SUB ADDS SHLL SHLR ROTXL ROTXR NOT SHAL SHAR ROTL ROTR NEG ...

Page 426: ...IVXS BTST BTST BTST BTST OR XOR BOR BIOR BXOR BIXOR BAND BIAND AND BLD BILD BST BIST Instruction when most significant bit of DH is 0 Instruction when most significant bit of DH is 1 Instruction code 1 1 1 1 2 2 2 2 BOR BIOR BXOR BIXOR BAND BIAND BLD BILD BST BIST Notes 1 2 r is the register designation field aa is the absolute address field 1st byte 2nd byte AH BH AL BL 3rd byte CH DH CL DL 4th b...

Page 427: ...umber of states required for execution of an instruction can be calculated from these two tables as follows Execution states I SI J SJ K SK L SL M SM N SN Examples When instruction is fetched from on chip ROM and an on chip RAM is accessed BSET 0 FF00 From table A 4 I L 2 J K M N 0 From table A 3 SI 2 SL 2 Number of states required for execution 2 2 2 2 8 When instruction is fetched from on chip R...

Page 428: ...ion Instruction Cycle On Chip Memory On Chip Peripheral Module Instruction fetch SI 2 Branch address read SJ Stack operation SK Byte data access SL 2 or 3 Word data access SM Internal operation SN 1 Note Depends on which on chip module is accessed See section B 1 Register Addresses ...

Page 429: ...S ADDS W 1 Rd 1 ADDS W 2 Rd 1 ADDX ADDX B xx 8 Rd 1 ADDX B Rs Rd 1 AND AND B xx 8 Rd 1 AND B Rs Rd 1 ANDC ANDC xx 8 CCR 1 BAND BAND xx 3 Rd 1 BAND xx 3 Rd 2 1 BAND xx 3 aa 8 2 1 Bcc BRA d 8 BT d 8 2 BRN d 8 BF d 8 2 BHI d 8 2 BLS d 8 2 BCC d 8 BHS d 8 2 BCS d 8 BLO d 8 2 BNE d 8 2 BEQ d 8 2 BVC d 8 2 BVS d 8 2 BPL d 8 2 BMI d 8 2 BGE d 8 2 BLT d 8 2 BGT d 8 2 BLE d 8 2 BCLR BCLR xx 3 Rd 1 BCLR xx ...

Page 430: ...ILD xx 3 aa 8 2 1 BIOR BIOR xx 3 Rd 1 BIOR xx 3 Rd 2 1 BIOR xx 3 aa 8 2 1 BIST BIST xx 3 Rd 1 BIST xx 3 Rd 2 2 BIST xx 3 aa 8 2 2 BIXOR BIXOR xx 3 Rd 1 BIXOR xx 3 Rd 2 1 BIXOR xx 3 aa 8 2 1 BLD BLD xx 3 Rd 1 BLD xx 3 Rd 2 1 BLD xx 3 aa 8 2 1 BNOT BNOT xx 3 Rd 1 BNOT xx 3 Rd 2 2 BNOT xx 3 aa 8 2 2 BNOT Rn Rd 1 BNOT Rn Rd 2 2 BNOT Rn aa 8 2 2 BOR BOR xx 3 Rd 1 BOR xx 3 Rd 2 1 BOR xx 3 aa 8 2 1 BSET ...

Page 431: ... Rd 1 BTST Rn Rd 2 1 BTST Rn aa 8 2 1 BXOR BXOR xx 3 Rd 1 BXOR xx 3 Rd 2 1 BXOR xx 3 aa 8 2 1 CMP CMP B xx 8 Rd 1 CMP B Rs Rd 1 CMP W Rs Rd 1 DAA DAA B Rd 1 DAS DAS B Rd 1 DEC DEC B Rd 1 DIVXU DIVXU B Rs Rd 1 12 EEPMOV EEPMOV 2 2n 2 1 INC INC B Rd 1 JMP JMP Rn 2 JMP aa 16 2 2 JMP aa 8 2 1 2 JSR JSR Rn 2 1 JSR aa 16 2 1 2 JSR aa 8 2 1 1 LDC LDC xx 8 CCR 1 LDC Rs CCR 1 MOV MOV B xx 8 Rd 1 MOV B Rs R...

Page 432: ... Rd 1 1 MOV B Rs d 16 Rd 2 1 MOV B Rs Rd 1 1 2 MOV B Rs aa 8 1 1 MOV B Rs aa 16 2 1 MOV W xx 16 Rd 2 MOV W Rs Rd 1 MOV W Rs Rd 1 1 MOV W d 16 Rs Rd 2 1 MOV W Rs Rd 1 1 2 MOV W aa 16 Rd 2 1 MOV W Rs Rd 1 1 MOV W Rs d 16d 2 1 MOV W Rs Rd 1 1 2 MOV W Rs aa 16 2 1 MULXU MULXU B Rs Rd 1 12 NEG NEG B Rd 1 NOP NOP 1 NOT NOT B Rd 1 OR OR B xx 8 Rd 1 OR B Rs Rd 1 ORC ORC xx 8 CCR 1 ROTL ROTL B Rd 1 ROTR RO...

Page 433: ...Operation N RTE RTE 2 2 2 RTS RTS 2 1 2 SHAL SHAL B Rd 1 SHAR SHAR B Rd 1 SHLL SHLL B Rd 1 SHLR SHLR B Rd 1 SLEEP SLEEP 1 STC STC CCR Rd 1 SUB SUB B Rs Rd 1 SUB W Rs Rd 1 SUBS SUBS W 1 Rd 1 SUBS W 2 Rd 1 POP POP Rd 1 1 2 PUSH PUSH Rs 1 1 2 SUBX SUBX B xx 8 Rd 1 SUBX B Rs Rd 1 XOR XOR B xx 8 Rd 1 XOR B Rs Rd 1 XORC XORC xx 8 CCR 1 ...

Page 434: ...BSR JMP JSR RTS TRAPA RTE SLEEP LDC STC ANDC ORC XORC NOP Data transfer instructions Arithmetic operations Logical operations Shift operations Bit manipulations Branching instructions System control instructions Block data transfer instructions BWL BWL WL B B B xx Rn ERn d 16 ERn d 24 ERn ERn ERn aa 8 aa 16 aa 24 d 8 PC d 16 PC aa 8 BWL BWL BWL B L BWL B BW BWL WL BWL BWL BWL B B B BWL B W W BWL W...

Page 435: ...2 General register D GRD 16 H FF8E Timer W 16 1 2 Flash memory control register 1 FLMCR1 8 H FF90 ROM 8 2 Flash memory control register 2 FLMCR2 8 H FF91 ROM 8 2 Flash memory power control register FLPWCR 8 H FF92 ROM 8 2 Erase block register 1 EBR1 8 H FF93 ROM 8 2 Flash memory enable register FENR 8 H FF9B ROM 8 2 Timer control register V0 TCRV0 8 H FFA0 Timer V 8 3 Timer control status register...

Page 436: ... I2 C bus status register ICSR 8 H FFC5 IIC 8 2 I2 C bus data register ICDR 8 H FFC6 IIC 8 2 Second slave address register SARX 8 H FFC6 IIC 8 2 I2 C bus mode register ICMR 8 H FFC7 IIC 8 2 Slave address register SAR 8 H FFC7 IIC 8 2 Address break control register ABRKCR 8 H FFC8 Address break 8 2 Address break status register ABRKSR 8 H FFC9 Address break 8 2 Break address register H BARH 8 H FFC...

Page 437: ...rt control register 8 PCR8 8 H FFEB I O port 8 2 System control register 1 SYSCR1 8 H FFF0 Power down 8 2 System control register 2 SYSCR2 8 H FFF1 Power down 8 2 Interrupt edge select register 1 IEGR1 8 H FFF2 Interrupts 8 2 Interrupt edge select register 2 IEGR2 8 H FFF3 Interrupts 8 2 Interrupt enable register 1 IENR1 8 H FFF4 Interrupts 8 2 Interrupt flag register 1 IRR1 8 H FFF6 Interrupts 8 ...

Page 438: ...C13 GRC12 GRC11 GRC10 GRC9 GRC8 GRC7 GRC6 GRC5 GRC4 GRC3 GRC2 GRC1 GRC0 GRD GRD15 GRD14 GRD13 GRD12 GRD11 GRD10 GRD9 GRD8 GRD7 GRD6 GRD5 GRD4 GRD3 GRD2 GRD1 GRD0 FLMCR1 SWE ESU PSU EV PV E P ROM FLMCR2 FLER FLPWCR PDWND EBR1 EB4 EB3 EB2 EB1 EB0 FENR FLSHE TCRV0 CMIEB CMIEA OVIE CCLR1 CCLR0 CKS2 CKS1 CKS0 Timer V TCSRV CMFB CFMA OVF OS3 OS2 OS1 OS0 TCORA TCORA7 TCORA6 TCORA5 TCORA4 TCORA3 TCORA2 TC...

Page 439: ...P IIC ICSR ESTP STOP IRTR AASX AL AAS ADZ ACKB ICDR ICDR7 ICDR6 ICDR5 ICDR4 ICDR3 ICDR2 ICDR1 ICDR0 SARX SVAX7 SVAX6 SVAX5 SVAX4 SVAX3 SVAX2 SVAX1 SVAX0 ICMR MLS WAIT CKS2 CKS1 CKS0 BC2 BC1 BC0 SAR SVA7 SVA6 SVA5 SVA4 SVA3 SVA2 SVA1 SVA0 ABRKCR RTINTE CSEL1 CSEL0 ACMP2 ACMP1 ACMP0 DCMP1 DCMP0 Address break ABRKSR ABIF ABIE BARH BARH7 BARH6 BARH5 BARH4 BARH3 BARH2 BARH1 BARH0 BARL BARL7 BARL6 BARL5...

Page 440: ...53 PCR52 PCR51 PCR50 PCR7 PCR6 PCR5 PCR4 PCR8 PCR87 PCR86 PCR85 PCR84 PCR83 PCR82 PCR81 PCR80 SYSCR1 SSBY STS2 STS1 STS0 NESEL Power down SYSCR2 SMSEL LSON DTON MA2 MA1 MA0 SA1 SA0 IEGR1 NMIEG IEG3 IEG2 IEG1 IEG0 Interrupts IEGR2 WPEG5 WPEG4 WPEG3 WPEG2 WPEG1 WPEG0 IENR1 IENDT IENTA IENWP IEN3 IEN2 IEN1 IEN0 IRR1 IRRDT IRRTA IRRI3 IRRI2 IRRI1 IRRI0 IWPR IWPF5 IWPF4 IWPF3 IWPF2 IWPF1 IWPF0 MSTCR1 M...

Page 441: ...eset and SBY goes low in a reset and in standby mode PDR PUCR PMR PCR SBY RES PUCR Port pull up control register PMR Port mode register PDR Port data register PCR Port control register IRQ TRGV Internal data bus Pull up MOS Figure C 1 Port 1 Block Diagram P17 ...

Page 442: ...DR PUCR PMR PCR SBY RES PUCR Port pull up control register PMR Port mode register PDR Port data register PCR Port control register IRQ Internal data bus Pull up MOS Figure C 2 Port 1 Block Diagram P16 to P14 ...

Page 443: ...427 PDR PUCR PCR SBY RES PUCR Port pull up control register PDR Port data register PCR Port control register Internal data bus Pull up MOS Figure C 3 Port 1 Block Diagram P12 P11 ...

Page 444: ...R PUCR PMR PCR SBY RES PUCR Port pull up control register PMR Port mode register PDR Port data register PCR Port control register Internal data bus TMOW Timer A Pull up MOS Figure C 4 Port 1 Block Diagram P10 ...

Page 445: ...429 PDR PMR PCR SBY PMR Port mode register PDR Port data register PCR Port control register Internal data bus TxD SCI3 Figure C 5 Port 2 Block Diagram P22 ...

Page 446: ...430 PDR PCR SBY PDR Port data register PCR Port control register RE Internal data bus RxD SCI3 Figure C 6 Port 2 Block Diagram P21 ...

Page 447: ...431 PDR PCR SBY PDR Port data register PCR Port control register SCKIE Internal data bus SCKI SCI3 SCKOE SCKO Figure C 7 Port 2 Block Diagram P20 ...

Page 448: ...432 PDR PCR SBY ICE SDAO SCLO SDAI SCLI IIC PDR Port data register PCR Port control register Internal data bus Figure C 8 Port 5 Block Diagram P57 P56 ...

Page 449: ...DR PUCR PMR PCR SBY RES PUCR Port pull up control register PMR Port mode register PDR Port data register PCR Port control register WKP Internal data bus ADTRG Pull up MOS Figure C 9 Port 5 Block Diagram P55 ...

Page 450: ...R PUCR PMR PCR SBY RES PUCR Port pull up control register PMR Port mode register PDR Port data register PCR Port control register WKP Internal data bus Pull up MOS Figure C 10 Port 5 Block Diagram P54 to P50 ...

Page 451: ...435 PDR PCR SBY OS3 OS2 OS1 OS0 TMOV PDR Port data register PCR Port control register Internal data bus Timer V Figure C 11 Port 7 Block Diagram P76 ...

Page 452: ...436 PDR PCR SBY TMCIV PDR Port data register PCR Port control register Internal data bus Timer V Figure C 12 Port 7 Block Diagram P75 ...

Page 453: ...437 PDR PCR SBY TMRIV PDR Port data register PCR Port control register Internal data bus Timer V Figure C 13 Port 7 Block Diagram P74 ...

Page 454: ...438 PDR PCR SBY PDR Port data register PCR Port control register Internal data bus Figure C 14 Port 8 Block Diagram P87 to P85 ...

Page 455: ...439 PDR PCR SBY PDR Port data register PCR Port control register Internal data bus FTIOA FTIOB FTIOC FTIOD Timer W Output control signals A to D Figure C 15 Port 8 Block Diagram P84 to P81 ...

Page 456: ...440 PDR PCR SBY FTCI PDR Port data register PCR Port control register Internal data bus Timer W Figure C 16 Port 8 Block Diagram P80 ...

Page 457: ...441 DEC VIN CH3 to CH0 A D converter Internal data bus Figure C 17 Port B Block Diagram PB7 to PB0 ...

Page 458: ...pedance Retained Retained High impedance Functions Functions P57 to P50 High impedance Retained Retained High impedance Functions Functions P76 to P74 High impedance Retained Retained High impedance Functions Functions P87 to P80 High impedance Retained Retained High impedance Functions Functions PB7 to PB0 High impedance High impedance High impedance High impedance High impedance High impedance N...

Page 459: ...64BP Mask ROM version Standard product HD6433664H HD6433664FP HD6433664BP H8 3663 Mask ROM version Standard product HD6433663H HD6433663FP HD6433663BP H8 3662 Mask ROM version Standard product HD6433662H HD6433662FP HD6433662BP H8 3661 Mask ROM version Standard product HD6433661H HD6433661FP HD6433661BP H8 3660 Mask ROM version Standard product HD6433660H HD6433660FP HD6433660BP ...

Page 460: ...s apply Hitachi Code JEDEC EIAJ Weight reference value FP 64A Conforms 1 2 g Unit mm Dimension including the plating thickness Base material dimension 0 10 0 15 M 17 2 0 3 48 33 49 64 1 16 32 17 17 2 0 3 0 35 0 06 0 8 3 05 Max 14 2 70 0 8 1 6 0 8 0 3 0 17 0 05 0 10 0 15 0 10 1 0 0 37 0 08 0 15 0 04 Figure F 1 FP 64A Package Dimensions ...

Page 461: ...rms 0 4 g Unit mm Dimension including the plating thickness Base material dimension M 12 0 0 2 10 48 33 1 16 17 32 64 49 0 22 0 05 0 08 0 5 12 0 0 2 0 10 1 70 Max 0 17 0 05 0 5 0 2 0 8 1 0 1 45 0 10 0 10 1 25 0 20 0 04 0 15 0 04 Figure F 2 FP 64E Package Dimensions ...

Page 462: ...EC EIAJ Weight reference value DP 42S Conforms 4 8 g Unit mm 0 25 0 10 0 05 0 15 15 24 37 3 38 6 Max 1 0 14 0 14 6 Max 0 51 Min 5 10 Max 2 54 Min 0 48 0 10 1 78 0 25 42 22 1 21 1 38 Max Figure F 3 DP 42S Package Dimensions ...

Page 463: ...arch 2000 2nd Edition September 2000 Published by Electronic Devices Sales Marketing Group Semiconductor Integrated Circuits Hitachi Ltd Edited by Technical Documentation Group Hitachi Kodaira Semiconductor Co Ltd Copyright Hitachi Ltd 2000 All rights reserved Printed in Japan ...

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