Hitachi H8/3660, Hardware Manual

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12.4.2 Operation Timing
TCNT Count Timing: Figure 12.23 shows the TCNT count timing when the internal clock
source is selected. Figure 12.24 shows the timing when the external clock source is selected. The
pulse width of the external clock signal must be at least two system clock (
φ
) cycles; shorter pulses
will not be counted correctly.
TCNT
TCNT input
clock
Internal
clock
φ
N N+1 N+2
Falling edge
Figure 12.23 Count Timing for Internal Clock Source
TCNT
TCNT input
clock
External
clock
φ
N N+1 N+2
Rising edge Rising edge
Figure 12.24 Count Timing for External Clock Source
Output Compare Timing: The compare match signal is generated in the last state in which
TCNT and the general register match (when TCNT changes from the matching value to the next
value). When the compare match signal is generated, the output value selected in TIOR is output
at the compare match output pin (FTIOA, FTIOB, FTIOC, or FTIOD). When TCNT matches a
general register, the compare match signal is generated only after the next counter clock pulse is
input.