MC9S12XHY-Family Reference Manual, Rev. 1.01
Freescale Semiconductor
259
Chapter 7
S12XE Clocks and Reset Generator (S12XECRGV2)
7.1
Introduction
This specification describes the function of the Clocks and Reset Generator (S12XECRG).
7.1.1
Features
The main features of this block are:
•
Phase Locked Loop (IPLL) frequency multiplier with internal filter
— Reference divider
— Post divider
— Configurable internal filter (no external pin)
— Optional frequency modulation for defined jitter and reduced emission
— Automatic frequency lock detector
— Interrupt request on entry or exit from locked condition
— Self Clock Mode in absence of reference clock
•
System Clock Generator
— Clock Quality Check
— User selectable fast wake-up from Stop in Self-Clock Mode for power saving and immediate
program execution
— Clock switch for either Oscillator or PLL based system clocks
•
Computer Operating Properly (COP) watchdog timer with time-out clear window.
•
System Reset generation from the following possible sources:
— Power on reset
— Low voltage reset
— Illegal address reset
— COP reset
— Loss of clock reset
Table 7-1. Revision History
Revision
Number
Revision
Date
Sections
Affected
Description of Changes
V02.00
18 Sep. 2009
Initial release derived from S12XECRG V01.04 plus modifications for LCD
clock output.
electronic components distributor
