Electrical Characteristics
MC9S12XHY-Family Reference Manual, Rev. 1.01
Freescale Semiconductor
751
The 1/3, 1/2 and 2/3 VLCD voltage levels are buffered internally with an asymmetric output stage, as
shown in
Figure A-6.
Figure A-6. Buffer configuration (left) and buffer output stage (right)
The switching matrix applies a capacitive load (LCD elements) to the buffer output. The charge excites the
buffer output voltage V
Buf
from the target output voltage which can be 1/3, 1/2 or 2/3 VLCD. After a
positive spike on V
Buf
a frontplane or backplane is discharged by an active load with a constant current.
After a negative spike on V
Buf
the output is charged through a transistor which is switched on and which
behaves like a resistor. Simplified output voltage transients are shown in
Figure A-7.
. The shown
transients emphasize the spikes and the voltage recovery. They are not to scale. The buffer output
characteristic is shown in
Figure A-8.
. The resistive output characteristic is also valid if an output is
forced to GND or VLCD.
switch
matrix
to LCD
V
Buf
V
Buf
VLCD
VDDX
output MOSFET
active load
I
out
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