Background Debug Module (S12XBDMV2)
MC9S12XHY-Family Reference Manual Rev. 1.01
Freescale Semiconductor
213
Figure 5-9. BDM Target-to-Host Serial Bit Timing (Logic 1)
High-Impedance
Earliest
Start of
Next Bit
R-C Rise
10 Cycles
10 Cycles
Host Samples
BKGD Pin
Perceived
Start of Bit Time
BKGD Pin
BDM Clock
(Target MCU)
Host
Drive to
BKGD Pin
Target System
Speedup
Pulse
High-Impedance
High-Impedance
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