Freescale Semiconductor MC9S12XHY Series, Reference Manual

Page: 57 / 802

Device Overview MC9S12XHY-Family
MC9S12XHY-Family Reference Manual, Rev. 1.01
Freescale Semiconductor 57
Vector base + $C0 IIC bus I bit IBCR(IBIE)
Vector base + $BE
to
Vector base + $BC
Reserved
Vector base + $BA FLASH Fault Detect I bit FCNFG2 (SFDIE, DFDIE)
Vector base + $B8 FLASH I bit FCNFG (CCIE)
Vector base + $B6 CAN0 wake-up I bit CANRIER (WUPIE)
Vector base + $B4 CAN0 errors I bit CANRIER (CSCIE, OVRIE)
Vector base + $B2 CAN0 receive I bit CANRIER (RXFIE)
Vector base + $B0 CAN0 transmit I bit CANTIER (TXEIE[2:0])
Vector base+ $AE TIM1 timer channel 0 I bit TIM1TIE (C0I)
Vector base + $AC TIM1 timer channel 1 I bit TIM1TIE (C1I)
Vector base+ $AA TIM1 timer channel 2 I bit TIM1TIE (C2I)
Vector base+ $A8 TIM1 timer channel 3 I bit TIM1TIE (C3I)
Vector base+ $A6 TIM1 timer channel 4 I bit TIM1TIE (C4I)
Vector base + $A4 TIM1 timer channel 5 I bit TIM1TIE (C5I)
Vector base+ $A2 TIM1 timer channel 6 I bit TIM1TIE (C6I)
Vector base+ $A0 TIM1 timer channel 7 I bit TIM1TIE (C7I)
Vector base+ $9E TIM1 timer overflow I bit TIM1TSRC2 (TOF)
Vector base+ $9C TIM1 Pulse accumulator A overflow I bit TIM1PACTL (PAOVI)
Vector base + $9A TIM1 Pulse accumulator input edge I bit TIM1PACTL (PAI)
Vector base+ $98 Reserved
Vector base + $96 Motor Control Timer Overflow I-Bit MCCTL1 (MCOCIE)
Vector base + $94
to
Vector base + $90
Reserved
Vector base + $8E Port T I bit PIET (PIET7-PIET0)
Vector base+ $8C PWM emergency shutdown I bit PWMSDN (PWMIE)
Vector base + $8A SSD0 I bit MDC0CTL(MCZIE,AOVIE)
Vector base + $88 SSD1 I bit MDC1CTL(MCZIE,AOVIE)
Vector base + $86 SSD2 I bit MDC2CTL(MCZIE,AOVIE)
Vector base + $84 SSD3 I bit MDC3CTL(MCZIE,AOVIE)
Vector base + $82 Reserved
Vector base + $80 Low-voltage interrupt (LVI) I bit VREGCTRL (LVIE)
Vector base + $7E Autonomous periodical interrupt (API) I bit VREGAPICTRL (APIE)
Table 1-11. Interrupt Vector Locations (Sheet 2 of 3)
Vector Address
(1)
Interrupt Source
CCR
Mask
Local Enable
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