Inter-Integrated Circuit (IICV3) Block Description
MC9S12XHY-Family Reference Manual, Rev. 1.01
Freescale Semiconductor
401
Figure 12-5. SCL Divider and SDA Hold
The equation used to generate the divider values from the IBFD bits is:
SCL Divider = MUL x {2 x (s [(SCL_Tap -1) x tap2tap] + 2)}
The SDA hold delay is equal to the CPU clock period multiplied by the SDA Hold value shown in
Table 12-7
. The equation used to generate the SDA Hold value from the IBFD bits is:
SDA Hold = MUL x {s [(SDA_Tap - 1) x tap2tap] + 3}
The equation for SCL Hold values to generate the start and stop conditions from the IBFD bits is:
SCL Hold(start) = MUL x [scl (SCL_Tap - 1) x tap2tap]
SCL Hold(stop) = MUL x [sc (SCL_Tap - 1) x tap2tap]
Table 12-7. IIC Divider and Hold Values (Sheet 1 of 6)
IBC[7:0]
(hex)
SCL Divider
(clocks)
SDA Hold
(clocks)
SCL Hold
(start)
SCL Hold
(stop)
MUL=1
SCL Divider
SDA Hold
SCL
SDA
SDA
SCL
START condition
STOP condition
SCL Hold(start)
SCL Hold(stop)
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