S12XE Clocks and Reset Generator (S12XECRGV2)
MC9S12XHY-Family Reference Manual, Rev. 1.01
Freescale Semiconductor
263
7.3.2
Register Descriptions
This section describes in address order all the S12XECRG registers and their individual bits.
7.3.2.1
S12XECRG Synthesizer Register (SYNR)
The SYNR register controls the multiplication factor of the IPLL and selects the VCO frequency range.
Read: Anytime
Write: Anytime except if PLLSEL = 1
NOTE
Write to this register initializes the lock detector bit.
NOTE
f
VCO
must be within the specified VCO frequency lock range. F.
BUS
(Bus
Clock) must not exceed the specified maximum. If POSTDIV = $00 then
f
PLL
is same as f
VCO
(divide by one).
The VCOFRQ[1:0] bit are used to configure the VCO gain for optimal stability and lock time. For correct
IPLL operation the VCOFRQ[1:0] bits have to be selected according to the actual target VCOCLK
frequency as shown in
Table 7-2
. Setting the VCOFRQ[1:0] bits wrong can result in a non functional IPLL
(no locking and/or insufficient stability).
Module Base + 0x0000
7
6
5
4
3
2
1
0
R
VCOFRQ[1:0]
SYNDIV[5:0]
W
Reset
0
0
0
0
0
0
0
0
Figure 7-3. S12XECRG Synthesizer Register (SYNR)
Table 7-2. VCO Clock Frequency Selection
VCOCLK Frequency Ranges
VCOFRQ[1:0]
32MHz <= f
VCO
<= 48MHz
00
48MHz < f
VCO
<= 80MHz
01
Reserved
10
80MHz < f
VCO
<= 120MHz
11
f
VCO
2
f
OSC
×
SYNDIV
1
+
(
)
REFDIV
1
+
(
)
-------------------------------------
×
=
f
PLL
f
VCO
2
POSTDIV
×
------------------------------------
=
f
BUS
f
PLL
2
-------------
=
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