Force SPARC/CPCI-520G, Technical Reference Manual

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Hardware Description Ethernet and EBus2 Devices – PCIO
SPARC/CPCI-52x(G) Page 77
6.3.2 EBus2 Interface – PCIO
The PCIO also provides the interface to the EBus2. EBus2 is a generic
slave 8-bit wide DMA bus (pseudo ISA bus) to which off-the-shelf pe-
ripherals can be connected.
Base addresses
of PCIO chip
select signals The base addresses of all 8 PCIO chip select signals in the 4 GByte PCI
address space is determined by the following 2 registers of PCIO’s con-
figuration address space:
PCIO chip select
signals The PCIO PCI-to-EBus2 controller delivers 8 decoded chip select sig-
nals:
• EBus_CS#0 (16-MByte space)
• and EBus_CS#1…EBus_CS#7 (each 1 MByte space).
It thereby supports up to 8 single- or multi-function Intel-style 8-bit de-
vices with a minimum of glue logic. The resulting memory map in the
PCI address space (with the base address registers in the reset value con-
figuration) is described in the table below.
After power up, the Base-520(G) PCIO is in boot mode and uses
EBus_CS#0
for the initial code fetch (OpenBoot). Therefore, the boot
PROM is hardwired to
EBus_CS#0
.
Table 36 PCIO EBus2 base address registers
PCIO
configuration
space address
Size Description Reset Value
010
16
32 EBus2 base address register 0: base address for
EB_CS#0
(16 MBytes)
F000.0000
16
014
16
32 EBus2 base address register 1: base address for
EBus_CS#1…EBus_CS#7
(each 1 MByte)
F100.0000
16
Table 37 EBus2 memory map in the PCI bus 4 GByte address space
PCI addr. range Description
EBus_
CS#
F000.0000
16
…F01F.FFFF
16
Boot PROM or boot flash EPROM, see “Boot PROM, Boot
and User Flash EPROM” on page 79 0
F020.0000
16
…F0FF.FFFF
16
User flash, see “Boot PROM, Boot and User Flash
EPROM” on page 79 0
F100.0000
16
…F10F.FFFF
16
“RTC/NVRAM – M48T58” on page 83 1