Force SPARC/CPCI-520G, Technical Reference Manual

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Hardware Description Ethernet and EBus2 Devices – PCIO
SPARC/CPCI-52x(G) Page 79
6.3.3 Boot PROM, Boot and User Flash EPROM
The PCIO’s 16-MByte chip select signal
EBus_CS#0
is decoded to
3 chip select signals for
• 1 boot PROM device or 1 boot flash EPROM device (2 MByte
address space).
• and up to 2 user flash EPROM devices (remaining 14 MBytes
address space).
For the base address of
EBus_CS#0
see section 6.3.2 “EBus2 Interface
– PCIO” on page 77.
Flash decoding The Boot and User Flash Size Control Register indicates the
EBus_CS#0
decoding according to the assembled flash devices (see
section 6.3.10 “SCR: Boot and User Flash” on page 89). The decoding is
shown in the table below.
Table 39 Boot and user flash address space configuration
PCI addr. range Configuration Device type
F000.0000
16
…F00F.FFFF
16
Default config. with SW6-2 = OFF 1 MByte boot PROM
one 27C080, 1Mbx8
read-only device
F020.0000
16
…F03F.FFFF
16
2 MByte user flash EPROM
one 29F016, 2Mbx8, 5V
write-protectable via SW4-4
F040.0000
16
…F0FF.FFFF
16
12 MByte unused
F000.0000
16
…F01F.FFFF
16
Alternative config. with SW6-2 = ON 2 MByte boot flash EPROM
one 29F016, 2Mbx8, 5V
write-protectable via SW4-3
F020.0000
16
…F03F.FFFF
16
2 MByte user flash EPROM
one 29F016, 2Mbx8, 5V
write-protectable via SW4-4
F040.0000
16
…F0FF.FFFF
16
12 MByte unused