Force SPARC/CPCI-520G, Technical Reference Manual

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Ethernet and EBus2 Devices – PCIO Hardware Description
Page 90 SPARC/CPCI-52x(G)
xROM_SIZE
(ro)
USERROM_SIZE
and
BOOTROM_SIZE
indicate the decoding of the
user and boot flash EPROM, respectively.
= 00
2
,
01
2
reserved
= 10
2
Offset range 00.0000
16
… 0F.FFFF
16
= 11
2
(default) Offset range
00.0000
16
… 1F.FFFF
16
Boot device
selection For information on selecting the boot device, see “SW_PLCC_TSOP
(r/w)” on page 91.
6.3.11 SCR: Watchdog, Temperature Sensors, and Reset
Watchdog An on-board watchdog can be enabled by SW6-4 (ON = enabled, see
page 28). To start the watchdog timer after enabling it via SW6-4, it is
necessary to trigger
WDI
in the Watchdog Timer Trigger Register once.
The watchdog monitors the processor activity. When the watchdog timer
interval expires, i.e. the watchdog timer is no longer triggered periodical-
ly, the watchdog timer activates its
WDO output and a watchdog timer in-
terrupt can be generated if
IE_WDT
in the Watchdog and Temperature
Control and Status Register is set appropriately. The generation of an in-
terrupt is indicated by the Reset Status Register.
Temperature
sensors The 2 temperature sensors connected to the I
2
C Bus can be programmed
to generate a temperature control interrupt (see also section 6.3.13 “SCR:
I2C-Bus” on page 95).
The temperature sensors may be programmed in such a way that either
the
O.S.
output signal is operating in the comparator mode or the inter-
rupt mode. The state of the
O.S.
output signal is indicated by the
IS_TEMPn (ro) bits in the Miscellaneous Control and Status Register.
• In the comparator mode O.S.
– is cleared (
0
) when the current temperature exceeds an upper tem-
perature limit T
OS
.
– is set (
1
) only when the current temperature falls below a lower
limit T
HYST
.
• In the interrupt mode
O.S.
Table 47 Boot and User Flash Size Control Register
F160.0002
16
Bit 7 6 5 4 3 2 1 0
Value
1 1 1 1 USERROM_SIZE BOOTROM_SIZE