Force SPARC/CPCI-520G, Technical Reference Manual

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Hardware Description Ethernet and EBus2 Devices – PCIO
SPARC/CPCI-52x(G) Page 95
6.3.13 SCR: I
2
C-Bus
The SPARC/CPCI-52x(G) is equipped with an I
2
C bus consisting of a
data line and a clock line which are software-controlled. For further infor-
mation on the I
2
C Bus, refer to the I
2
C Bus specification. The figure be-
low shows the I
2
C Bus interface implementation in detail.
Figure 25 I
2
C Bus interface
Accessible
devices The devices listed in the table below can be accessed via the I
2
C Bus.
They are I
2
C Bus slaves and are identified by unique addresses also listed
in the table below:
The ID-PROMs are used to store board specific parameters. The temper-
ature sensors can be programmed for temperature monitoring and protec-
tion against overheating. To locate the temperature sensors see figure 7
“Location diagram of the Base-520(G) (schematic)” on page 22.
The devices can be accessed via the I
2
C Bus and can be read and written
via the I2C Bus Control and Status Register.
I2C_
SDAO
I2C_
SDAI
I2C_
SCL
0 1 2
I
2
C Bus data line SDA
I
2
C Bus clock line SCL
I2C Bus Control and Status Register
Table 54 I
2
C Bus slave addresses
I
2
C Bus Slave
Address Description
1001.111
2
Temperature sensor #1 LM75
1001.110
2
Temperature sensor #2 LM75
1010.000
2
ID PROM of the Base-520(G) – X
ICOR
X24C04 Serial E
2
PROM
1010.010
2
ID PROM of I/O-52x(G) – X
ICOR
X24C04 Serial E
2
PROM